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  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
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  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
  • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
• • H—ELECTRICITY
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
  • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
  • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
  • H01L21/2652—Through-implantation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/62—Electrodes ohmically coupled to a semiconductor
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/01—Manufacture or treatment
  • H10D8/021—Manufacture or treatment of breakdown diodes
  • H10D8/022—Manufacture or treatment of breakdown diodes of Zener diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/01—Manufacture or treatment
  • H10D8/021—Manufacture or treatment of breakdown diodes
  • H10D8/024—Manufacture or treatment of breakdown diodes of Avalanche diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/20—Breakdown diodes, e.g. avalanche diodes
  • H10D8/25—Zener diodes 

Definitions

• Zener diodes are two-terminal electronic devices which act as conventional diodes when forward-biased, i.e., with unidirectional conduction, but when reverse- biased above a certain threshold voltage, conduct in the reverse direction.
• the term "Zener diode” is traditionally applied to devices comprised of p-n junctions formed in conventional semiconductor materials, e.g., Si, which junctions undergo avalanche breakdown at reverse bias potentials above about 5 volts, for example, and such devices may be utilized in voltage regulating and circuit protection circuitry.
• a current (I) vs. voltage (V) plot of an idealized Zener diode is illustrated in FIG. 1, from which it is evident that, when reverse-biased above a certain voltage, i.e., the Zener threshold voltage, generally above 5 V, for example, for Si-based devices, a sudden rise in the reverse current occurs.
• a Zener diode functions as an ordinary rectifier, but, when reverse-biased, exhibits a knee, or sharp break, in its I-V plot.
• a characteristic of Zener avalanche or breakdown is that once conduction occurs under reverse-bias, the voltage across the device remains essentially constant upon further increase of reverse current, up to a maximum allowable dissipation rating. As a consequence of this characteristic behavior, Zener diodes find utility, inter alia, as voltage regulators, voltage references, and overvoltage protectors.
• Zener diode During a surge event, it is desired to limit the voltage drop across the device to a minimum value. Accordingly, an important characteristic of a Zener diode is its reverse surge capability.
• a semiconductor device such as a Zener diode
• the semiconductor device includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween.
• a first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed.
• a polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer.
• a first conductive layer is disposed on the polysilicon layer.
• a second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.
• a method is provided of fabricating a semiconductor device.
• the method includes forming a first oxide layer over a portion of a semiconductor substrate formed from a first semiconductor material having a first conductivity type such that a remaining portion of the semiconductor substrate is exposed.
• a protective layer is formed on a first surface of the semiconductor substrate and the first oxide layer.
• a dopant of the second conductivity type is introduced into the semiconductor substrate through the protective layer to form a junction layer that defines a junction with the semiconductor substrate.
• a first conductive layer is formed over the junction layer.
• a second conductive layer is formed on a second surface of the semiconductor substrate opposing the first a surface of the semiconductor substrate.
• FIG. 1 shows a current (I) vs. voltage (V) plot of an idealized Zener diode.
• FIG. 2 shows one example of a Zener diode having an improved reverse surge capability and a reduced leakage current.
• FIGs. 3-9 show one example of a sequence of process steps that may be employed to fabricate the Zener diode shown in FIG. 2. Detailed Description
• Zener diode As detailed below, a Zener diode is provided which has an improved reverse surge capability and a reduced leakage current. Although this improvement will be described in terms of one illustrative Zener diode design, the methods and techniques described herein are equally applicable to a wide variety of Zener diode configurations as well as other types of transient voltage suppressors.
• FIG. 2 shows one example of a Zener diode having an improved reverse surge capability.
• Zener diode 100 includes a semiconductor substrate 110 heavily doped with a dopant of a first conductivity type, which in this example is a P-type dopant.
• a junction layer 120 of a second conductivity type is formed in the substrate 110.
• the junction layer 120 has an N+-type conductivity.
• a P-N junction is located at the interface between the semiconductor substrate 110 and the junction layer 120.
• a polysilicon layer 130 is disposed on the junction layer.
• a first conductive material 140 that serves as an electrode is disposed on the polysilicon layer 130.
• a second conductive material 150 that also serves as an electrode is disposed on a back surface of the substrate 1 10.
• the Zener diode 100 also includes a first oxide layer 160 disposed on the substrate 110 and which is formed and etched as part of the photolithographic process used to form the junction layer 120.
• a second oxide layer 170 such as a low temperature oxide (LTO), a first portion of which is disposed on the first oxide layer 160 and a second portion of which is interposed between the polysilicon layer 130 and the first conductive material 140.
• LTO low temperature oxide
• the second oxide layer 170 is formed and etched as part of the photolithographic process used to form the first conductive material 140.
• the polysilicon layer 130 is advantageously formed prior to junction layer 120.An implantation or other doping process is then used to deposit a dopant onto the polysilicon layer 130. A subsequent thermal process is applied to drive the dopant through the polysilicon layer 130 and into the substrate 110. The use of the polysilicon layer 130 in this manner has been found to improve both the reverse surge capability and the leakage current of the Zener diode. [0012] Without being bound by any theory of operation, the polysilicon layer is believed to reduce defects that are created by the doping process used to form the junction layer 120.
• defects are typically created to a certain depth within the substrate. These defects may adversely impact the reverse surge performance and the leakage current of the resulting device.
• defects in the substrate can be reduced.
• FIG. 3 is a cross sectional view of a semiconductor substrate and an oxide layer.
• substrate 210 is a low resistivity, P + -type ⁇ 11 1> orientation monocrystalline silicon having a resistivity in the range of approximately lxlO "3 ohm- cm to 5xl0 "3 ohm-cm.
• the silicon crystal lattice orientation can be optionally ⁇ 100>.
• substrate 210 is comprised of other types of semiconductor material, such as gallium arsenide.
• an N- type substrate can also be used with corresponding adjustments to the fabrication process.
• the P+ -type silicon substrate is doped with boron. Of course, it is understood that other dopants can also be used in the alternative.
• oxide layer 220 is formed.
• oxide layer 220 may be produced by exposing the wafer to an environment of approximately 1000°C. for about 200 minutes and to approximately 1200°C. for an additional 200 minutes. During this time the heated semiconductor materials are exposed to a mixture of nitrogen and oxygen gas.
• a layer of silicon dioxide ranging in thickness from about 1400 angstroms to about 1800 angstroms is grown on the surface of the structure. It is understood that other processes for forming an oxide layer can be used in connection with the present invention. Further, the oxide layer can be of a different thickness.
• a photolithography step is performed to create an opening in the oxide layer.
• a photoresist material 222 is applied to the surface of the oxide layer 220.
• the photoresist is applied at a thickness of about 1.3 microns.
• the photoresist material 222 is exposed to light through a pattern mask, and the exposed portions of the photoresist material are then removed from the surface of the oxide layer.
• the oxide is etched from the surface of the structure using a Reactive Ion Etching ("RIE") technique according to the pattern detail that was transferred to the photoresist. It is also understood that other oxide etching process can be used as an alternative to a reactive ion etching process. Oxide regions under the photoresist covered areas are not removed in the etching process.
• RIE Reactive Ion Etching
• the center portion of the oxide layer 220 is etched as described above to form window 215.
• Sections 220a correspond to the portions of oxide layer 220 that have not been etched.
• the remaining photoresist is removed from the wafer with a photoresist stripping solution before the next step.
• Polysilicon which may be undoped, is next deposited over the substrate 210 and at least a portion of the oxide layer 220a to form polysilicon layer 250.
• polysilicon layer 250 may have a thickness between 1 and 4 microns.
• An ion implantation process is next performed.
• the remaining oxide that has not been etched away forms a hard mask to prevent ions from passing therethrough so that they do not enter the substrate 210.
• the remaining photoresist material approximately 1.3 microns thick, may be left on the wafer until after the ion implantation procedure to aid the oxide in absorption of ions in the region outside of the exposed window.
• the ion implantation process is indicated in FIG. 5 by arrows 225.
• the arrows 225 represent an N+-type dopant such as phosphorous or arsenic that is introduced onto the polysilicon layer 250.
• the N+-type dopant is introduced using ion implantation of phosphorous at a dose of 1.72x1013 ions/cm 2 at an energy of 140 KeV, forming a layer approximately 1 micron deep.
• a significantly lower energy may be used in the ion implantation process.
• a subsequent diffusion step is performed at elevated temperatures to drive the implanted ions further into the substrate 210, thereby forming the N+-type junction layer 240 as shown in FIG. 6.
• an oxide layer 260 is formed over the polysilicon layer 250.
• the oxide layer 260 is a low temperature oxide (LTO) layer 260.
• LTO low temperature oxide
• FIG. 8 shows the sections 260a of the LTO layer 260 after being etched using a photolithographic technique as described above to form an opening for the deposition of an optional passivation layer (not shown) and a conductive material.
• the conductive material 280 which is shown in FIG. 9, may be a suitable metal such as silver, for example.
• the conductive material 280 is formed over the portion of the polysilicon layer 250 exposed by the opening in the LTO layer 260. Conductive material 280 is also formed over the sections 260a of the LTO layer 260.
• a series of Zener diodes were manufactured using a polysilicon layer of different thicknesses to demonstrate the improvements in the reverse surge capability and leakage current that can be achieved.
• the results are shown in Table 1 for a series of 5 V diodes and a series of 7V diodes. Three samples were manufactured in each series, one with no polysilicon which serves as a control, one with a polysilicon layer 1 micron in thickness and one with a polysilicon layer 2 microns thick. The minimum, average and maximum reverse surge capability and leakage current were measured for each device. As Table 1 shows, the reverse surge capability increases as the polysilicon thickness increases. Likewise, the leakage current decreases as the polysilicon thickness increases, thereby completing the device structure.
• Zener diodes were also manufactured with polysilicon layers thicker than 2 microns. For these devices the reverse surge capability was found to decrease as polysilicon thickness increases beyond two microns. This is presumably because of poor thermal dissipation caused by the polysilicon layer. Accordingly, the trade-off between fewer junction defects and poor heat dissipation resulted in an optimal polysilicon thickness of about 1 to 2 um for the 5 and 7 V Zener diodes.
• a polysilicon layer thickness of 1-4 um, and more particularly a layer thickness of 1-2 um may provide a significant increase in the reverse surge capability as well as a decrease in the leakage current.
• both layers that define the P-N junction may be formed in the semiconductor substrate by ion implantation or the like.
• a material other than polysilicon may be used to form the layer through which the dopants are introduced to form the junction layer.
• Any appropriate material may be employed which can serve as a protective layer protecting the substrate surface from damage arising during the doping process, without also forming a barrier to dopant diffusion.
• An advantage of using a material such as polysilicon, which is electrically conducting, is that it does not need to be removed after completion of the doping process. For instance, while an oxide layer may be used instead of a polysilicon layer, the oxide layer will need to be removed after the structure is doped since it is not an electrically conducting material.

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