WO2015043315A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2015043315A1
WO2015043315A1 PCT/CN2014/083562 CN2014083562W WO2015043315A1 WO 2015043315 A1 WO2015043315 A1 WO 2015043315A1 CN 2014083562 W CN2014083562 W CN 2014083562W WO 2015043315 A1 WO2015043315 A1 WO 2015043315A1
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Prior art keywords
layer
array substrate
base substrate
substrate
area
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PCT/CN2014/083562
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English (en)
French (fr)
Inventor
蔡振飞
罗丽平
郝昭慧
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/432,638 priority Critical patent/US10134769B2/en
Publication of WO2015043315A1 publication Critical patent/WO2015043315A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to an array substrate, a method of manufacturing the same, and a display device. Background technique
  • the liquid crystal display device mainly includes a liquid crystal display panel and a driving device for driving the liquid crystal display panel.
  • the liquid crystal display panel mainly includes a first substrate and a second substrate disposed opposite to each other; for example, the first substrate and the second substrate are an array substrate and a color film substrate, respectively.
  • the array substrate includes a plurality of data lines disposed in a crosswise manner and a plurality of scan lines to define a plurality of pixel regions.
  • a thin film transistor is disposed in each pixel region.
  • the driving device includes a gate driving circuit that outputs a scanning signal to the scanning line and a source driving circuit that outputs the data signal to the data line.
  • the end of the data line 1 is bonded to the bonding area 2 of the base substrate, that is, the area connected to the source driving circuit or other control circuit, and the area between the adjacent bonding areas 2 is In the non-bonding region 3, the base substrate is covered with the passivation layer 5 in both the bonding region 2 and the non-bonding region 3, thereby preventing the data line 1 from being oxidized and physically damaged.
  • a via 4 is formed in the passivation layer 5, and a source driving circuit or other control circuit is connected to the data line 1 through the via 4.
  • a data line 1 and an active layer 8 are further disposed between the passivation layer 5 and the gate insulating layer 7, such that the height and non-sticking of the passivation layer in the bonding region 2
  • the height of the passivation layer in the region 3 differs by ⁇ 1.
  • an array substrate including: a substrate substrate; and a plurality of data lines disposed on the substrate; wherein the substrate includes a plurality of ends that are attached to the ends of the data lines The bonding area and the non-bonding area between the adjacent bonding areas, wherein the passivation layer in the non-bonding area and the base substrate are provided with a raised layer.
  • the array substrate further includes a gate metal layer disposed on the substrate; the elevated layer and the gate metal layer are disposed in the same layer and have the same material.
  • an active layer is disposed between the end of the data line and the substrate; the thickness of the elevated layer is equal to the sum of the thickness of the data line and the active layer. In one example, the length of the elevated layer is equal to or greater than the length of the conforming region. In one example, the thickness of the elevated layer is set such that the non-bonding region and the passivation layer in the conforming region are flush.
  • a second aspect provides a method for fabricating an array substrate, comprising: providing a substrate, wherein the substrate is provided with a plurality of data lines, and the substrate includes a portion of each of the data lines a plurality of bonding regions and a non-bonding region between adjacent bonding regions; and forming a high-rise layer in the non-bonding region of the base substrate.
  • the above manufacturing method further includes: forming a gate on the base substrate; sequentially forming a gate insulating layer, an active layer, a data line, a source/drain metal layer, and a passivation on the base substrate on which the gate is formed Layers and vias.
  • the gate and the elevated layer are simultaneously formed on a base substrate.
  • the simultaneously forming the gate on the base substrate and the raising the upper layer comprises: depositing a metal thin film on the substrate; forming the gate and the elevated layer pattern by a patterning process.
  • the forming the gate and the high-rise pattern by a patterning process include: coating a photoresist on the metal film; exposing and developing through the mask to form a corresponding upper layer and a gate a photoresist retaining region of the pole and a photoresist removing region corresponding to a region outside the region; removing the metal thin film in the photoresist removing region by an etching process; and stripping the remaining photoresist.
  • the elevated layer is the same material as the gate.
  • the thickness of the elevated layer is equal to the sum of the thickness of the data line and the active layer.
  • a display device comprising the array substrate of any of the above.
  • 1 is a plan view of a bonding area and a non-bonding area of a known array substrate
  • FIG. 2 is a schematic structural view showing a phenomenon in which a passivation layer is detached from the array substrate in FIG. 1;
  • Figure 3 is a cross-sectional view of Figure 1 in the direction of AA; 4 is a plan view of a bonding area and a non-bonding area of the array substrate in the embodiment of the present invention; and FIG. 5 is a cross-sectional view of FIG. 4 in the AA direction.
  • the present disclosure provides an array substrate capable of improving the phenomenon of passivation layer detachment; further, the present disclosure also provides a method of fabricating the array substrate and a display device using the array substrate.
  • the array substrate provided by the embodiment of the present invention includes: a substrate substrate (not shown);
  • the base substrate includes a plurality of bonding regions 2 that are bonded to the ends of the respective data lines 1 and a non-bonding region 3 between the adjacent bonding regions 2; the bonding region 2 and the non-bonding region
  • the outermost layer of 3 is a passivation layer 5; an upper layer 6 is provided between the passivation layer 5 in the non-bonding region 3 and the base substrate.
  • the passivation layer and the non-bonding region 3 in the bonding region 2 are reduced or eliminated.
  • the difference in height of the passivation layer is such that the passivation layer in the bonding region 2 and the passivation layer in the non-bonding region 3 are planarized (ie, flush with each other), thereby solving the problem of the passivation layer falling off and reducing the wiring.
  • the occurrence of undesirable phenomena improves the reliability of the product.
  • the active layer 8 is disposed between the end of the data line 1 and the substrate.
  • the thickness of the elevated layer 6 is, for example, approximately equal to the sum of the thicknesses of the data line 1 and the active layer 8.
  • the passivation layer in the junction region 2 and the passivation layer in the non-bond region 3 are almost flat.
  • the length of the elevated layer 6 is equal to or greater than the length of the conforming region 2, for example, may be slightly longer than the length of the conforming region 2, thereby reducing or eliminating passivation in the conforming region 2 over a larger area.
  • the difference in height between the layer and the passivation layer in the non-bonding region 3 avoids the peeling of the passivation layer as much as possible.
  • a method for fabricating the above array substrate is further provided, and correspondingly, the main difference between the method for fabricating the array substrate in the prior art is that the method for fabricating the array substrate further includes forming any one of the above. Steps to increase the level of 6.
  • the above preparation methods include:
  • the base substrate is provided with a plurality of data lines, the base substrate including a plurality of bonding regions that are in contact with the ends of the respective data lines and located in the adjacent bonding regions Non-fit area;
  • An elevated layer is formed in the non-bonding region of the base substrate.
  • the above-mentioned elevated layer 6 may be formed separately, for example, a resin layer is separately formed between the passivation layer of the non-bonding region 3 and the substrate substrate as the elevated layer 6.
  • the upper layer 6 and the other layers are formed at the same time, for example, the upper layer 6 and the gate are disposed in the same layer and have the same material material, so that the upper layer 6 can be formed at the same time as the gate electrode is formed, thereby reducing the process difficulty and saving the production cost.
  • the following is an example in which the upper layer 6 is formed while forming the gate electrode as an example.
  • a gate insulating layer 7, an active layer 8, a data line 1, a source/drain metal layer (not shown), a passivation layer 5, and via holes 4 are sequentially formed.
  • simultaneously forming a gate on the base substrate and raising the upper layer 6 includes the following steps:
  • a substrate wherein the substrate may be a glass substrate or a quartz substrate or the like; 102) depositing a metal film on the substrate; for example, depositing on the substrate by magnetron sputtering or thermal evaporation a metal film; a metal film can use Cr, W, Ti, Ta, Mo, Al, Cu and other metals and alloys thereof, or a composite film composed of a plurality of metal films;
  • sequentially forming the gate insulating layer 7, the active layer 8, the data line 1, the source/drain metal layer, the passivation layer 5, and the via 4 includes the following steps:
  • PECVD Pullasma Enhanced Chemical Vapor Deposition
  • magnetron sputtering or thermal evaporation Depositing a source/drain metal layer depositing a semiconductor layer and a doped semiconductor layer sequentially on the gate insulating layer 7 by a method such as PECVD (Plasma Enhanced Chemical Vapor Deposition); and then using magnetron sputtering or thermal evaporation Depositing a source/drain metal layer;
  • a passivation layer 5 by using a PECVD method or other methods on the source electrode, the drain electrode, and the channel region;
  • a via 4 is formed on the passivation layer 5 by a patterning process.
  • the method for fabricating the array substrate of the present embodiment is merely an implementation method for fabricating the array substrate provided by the present invention. In actual operation, the specific steps may be changed by increasing or decreasing the number of patterning processes, selecting different materials, and the like.
  • the passivation layer and the non-bonding region in the bonding region 2 are reduced or eliminated.
  • the height difference of the passivation layer in 3 is such that the passivation layer in the bonding region 2 and the passivation layer in the non-bonding region 3 are planarized (ie, flush with each other), thereby solving the problem of the passivation layer falling off and reducing
  • the occurrence of poor wiring has improved the reliability of the product.
  • This embodiment also provides a display device including any of the above array substrates.
  • the display device is, for example, a liquid crystal display panel, an electronic paper, an OLED (Organic Light Emitting Diode) display panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like, and any product or component having a display function.
  • OLED Organic Light Emitting Diode
  • the passivation layer in the bonding region 2 of the array substrate and the passivation layer in the non-bonding region 2 are flat, thereby avoiding the occurrence of the passivation layer falling off, reducing the occurrence of wiring defects and improving The reliability of the product.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

公开一种阵列基板及其制造方法、显示装置。该阵列基板包括：衬底基板；以及设置在所述衬底基板上的多条数据线（1）。衬底基板包括与各条数据线（1）的端部相贴合的多个贴合区域（2）和位于相邻贴合区域之间的非贴合区域（3），所述非贴合区域（3）中的钝化层（5）与衬底基板之间设置有增高层（6）。通过在非贴合区域（3）中的钝化层（5）与衬底基板之间增加增高层（6），从而减少或者消除贴合区域中的钝化层与非贴合区域中的钝化层高度差异，以解决钝化层脱落问题，提高了产品的可靠性。

Description

阵列基板及其制造方法、 显示装置 技术领域
本公开涉及一种阵列基板及其制造方法、 显示装置。 背景技术
液晶显示装置主要包括液晶显示面板以及驱动该液晶显示面板的驱动装 置。 液晶显示面板主要包括相对设置的第一基板和第二基板； 例如， 第一基 板和第二基板分别为阵列基板和彩膜基板。 阵列基板包括交叉设置的多条数 据线以及多条扫描线以限定出多个像素区域。 每个像素区域设置有薄膜晶体 管。 驱动装置包括将扫描信号输出至扫描线的栅极驱动电路以及将数据信号 输出至数据线的源极驱动电路。
如图 1中所示， 数据线 1的端部贴合至衬底基板的贴合区域 2， 即与源 极驱动电路或者其他控制电路连接的区域， 相邻贴合区域 2之间的区域为非 贴合区域 3， 衬底基板在贴合区域 2以及非贴合区域 3中均覆盖有钝化层 5， 从而起到防止数据线 1被氧化以及受到物理损伤。 在钝化层 5上开设有过孔 4，源极驱动电路或者其他控制电路通过过孔 4与数据线 1连接。如图 3所示， 在贴合区域 2中， 钝化层 5与栅绝缘层 7之间还设置有数据线 1以及有源层 8，这样贴合区域 2中钝化层的高度与非贴合区域 3中钝化层的高度相差 ΔΗ1。 发明内容
第一方面， 提供一种阵列基板， 包括： 衬底基板； 以及设置在所述衬底 基板上的多条数据线； 其中衬底基板包括与各条数据线的端部相贴合的多个 贴合区域和位于相邻贴合区域之间的非贴合区域， 所述非贴合区域中的钝化 层与衬底基板之间设置有增高层。
在一个示例中， 上述阵列基板还包括设置在衬底基板上的栅极金属层； 所述增高层与所述栅极金属层同层设置且材质相同。
在一个示例中， 所述数据线的端部与衬底基板之间设置有有源层； 所述 增高层的厚度等于所述数据线与所述有源层的厚度之和。 在一个示例中， 所述增高层的长度等于或大于所述贴合区域的长度。 在一个示例中， 所述增高层的厚度设置为使所述非贴合区域和所述贴合 区域中的钝化层齐平。
第二方面， 提供一种阵列基板制造方法， 包括： 提供衬底基板， 其中所 述衬底基板上设置有多条数据线， 所述衬底基板包括与各条数据线的端部相 贴合的多个贴合区域和位于相邻贴合区域之间的非贴合区域； 以及在衬底基 板的非贴合区域中形成增高层。
在一个示例中， 上述制造方法还包括： 在衬底基板上形成栅极； 在形成 有栅极的衬底基板上依次形成栅绝缘层、 有源层、 数据线、 源漏金属层、 钝 化层以及过孔。
在一个示例中， 所述栅极和所述增高层同时形成在衬底基板上。
在一个示例中， 所述在衬底基板上同时形成栅极以及增高层包括： 在衬 底基板上沉积金属薄膜； 通过构图工艺形成所述栅极以及增高层图案。
在一个示例中， 所述通过构图工艺形成所述栅极以及增高层图案包括： 在所述金属薄膜上涂覆一层光刻胶； 通过掩模板曝光、 显影， 形成对应所述 增高层以及栅极的光刻胶保留区域以及对应上述区域之外区域的光刻胶去除 区域； 通过刻蚀工艺去除光刻胶去除区域中的金属薄膜； 以及剥离剩余的光 刻胶。
在一个示例中， 所述增高层与所述栅极的材料相同。
在一个示例中， 所述增高层的厚度等于所述数据线与所述有源层的厚度 之和。
第三方面， 提供一种显示装置， 包括以上任意一项所述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1是已知阵列基板的贴合区域以及非贴合区域的俯视图；
图 2是图 1中阵列基板发生钝化层脱落现象的结构示意图；
图 3是图 1在 A-A方向的剖面示意图； 图 4是本发明实施例中阵列基板的贴合区域以及非贴合区域的俯视图； 图 5是图 4在 A-A方向的剖面示意图。
附图标记： 1 : 数据线； 2: 贴合区域； 3: 非贴合区域； 4: 过孔； 5: 钝 化层； 6: 增高层； 7: 栅绝缘层； 8: 有源层。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
由于 ΔΗ1的存在， 图 1所示阵列基板的钝化层时常发生如图 2中所示的 钝化层脱落现象， 使得暴露出的数据线 1很容易被氧化或者受到物理损伤或 者被污染物腐蚀， 从而引起接线不良。 为此， 本公开提供一种能够改善钝化 层脱落现象的阵列基板； 进一步的， 本公开还提供了一种该阵列基板的制造 方法以及应用该阵列基板的显示装置。
如图 4以及图 5所示， 本发明实施例所提供的阵列基板， 包括： 衬底基板（未示出）； 以及
设置在衬底基板上的多条数据线 1 ;
其中衬底基板包括与各条各数据线 1的端部相贴合的多个贴合区域 2和 相邻贴合区域 2之间的非贴合区域 3; 贴合区域 2以及非贴合区域 3中的最 外层为钝化层 5;非贴合区域 3中的钝化层 5与衬底基板之间设置有增高层 6。
在上述阵列基板中， 通过在非贴合区域 3中的钝化层 5与衬底基板之间 增加增高层 6， 从而减少或者消除贴合区域 2中的钝化层与非贴合区域 3中 的钝化层的高度差异， 使贴合区域 2中的钝化层和非贴合区域 3中的钝化层 平坦化（即相互齐平），从而解决了钝化层脱落问题， 降低了接线不良现象的 发生， 提高了产品的可靠性。
由于数据线 1的端部与衬底基板之间设置有有源层 8， 本实施例中， 增 高层 6的厚度例如大致等于数据线 1与有源层 8的厚度之和， 此时， 贴合区 域 2中的钝化层和非贴合区域 3中的钝化层几乎是平坦的。 在一个示例中， 增高层 6的长度等于或大于贴合区域 2的长度， 例如可 以比贴合区域 2的长度稍长， 从而在较大的面积上减少或者消除贴合区域 2 中的钝化层与非贴合区域 3中的钝化层的高度差异， 尽可能避免钝化层的脱 落。
本实施例中还提供了一种上述阵列基板制备方法， 相应的， 与现有技术 中阵列基板制备方法的主要不同之处在于， 本实施例中的阵列基板制备方法 还包括形成上述任意一种增高层 6的步骤。
例如， 上述制备方法包括：
提供衬底基板， 其中所述衬底基板上设置有多条数据线， 所述衬底基板 包括与各条数据线的端部相贴合的多个贴合区域和位于相邻贴合区域之间的 非贴合区域； 以及
在衬底基板的非贴合区域中形成增高层。
上述增高层 6可以单独形成， 例如， 在非贴合区域 3的钝化层与衬底基 板之间单独形成一层树脂层作为增高层 6。 或者， 上述增高层 6与其他层同 时形成例如， 增高层 6与栅极同层设置且材质相同， 这样可以在形成栅极的 同时形成增高层 6， 从而降低工艺难度， 节省生产成本。 下面以在形成栅极 的同时形成增高层 6为例加以详细说明。
本实施例中所提供的阵列基板制备方法， 包括以下步骤：
在衬底基板上同时形成栅极（未示出） 以及增高层 6; 以及
依次形成栅绝缘层 7、 有源层 8、 数据线 1、 源漏金属层（未示出）、 钝 化层 5以及过孔 4。
例如， 在衬底基板上同时形成栅极以及增高层 6包括以下步骤：
101 )清洁衬底基板， 其中衬底基板可以是玻璃基板或者石英基板等等； 102 )在衬底基板上沉积金属薄膜； 例如釆用磁控溅射或热蒸发的方法在 衬底基板上沉积一层金属薄膜； 金属薄膜可以使用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属及其合金， 也可以为由多层金属薄膜组成的复合薄膜；
103 )在金属薄膜上涂布一层光刻胶；
104 )釆用掩模板进行曝光、显影， 以形成对应增高层 6以及栅极的光刻 105 )通过刻蚀工艺去除光刻胶去除区域的金属薄膜； 106 )剥离剩余的光刻胶， 留下的金属薄膜为包括栅极 (及扫描线 )和增 高层 6的图案。
例如， 依次形成栅绝缘层 7、 有源层 8、 数据线 1、 源漏金属层、 钝化层 5以及过孔 4包括以下步骤：
201 )在栅极以及增高层 6上形成覆盖整个衬底基板的栅绝缘层 7;
202 )釆用 PECVD ( Plasma Enhanced Chemical Vapor Deposition, 等离子 体增强化学气相沉积法）等方法在栅绝缘层 7上依次沉积半导体层以及掺杂 半导体层； 然后釆用磁控溅射或热蒸发等方法沉积源漏金属层；
203 )在源漏金属层上涂覆一层光刻胶；
204 )通过双色调掩模板曝光、显影， 形成对应源电极以及漏电极区域的 光刻胶完全保留区域、 对应沟道区域的光刻胶半保留区域以及对应上述区域 之外区域的光刻胶完全去除区域；
205 )通过第一次刻蚀工艺去除光刻胶完全去除区域的源漏金属层、掺杂 半导体层以及半导体层， 形成有源层 8图形；
206 )通过灰化工艺去除光刻胶半保留区域的光刻胶，暴露出该区域的源 漏金属层；
207 )通过第二次刻蚀工艺去除光刻胶半保留区域的源漏金属层以及掺杂 半导体层， 并去除部分厚度的半导体层， 形成源电极、 漏电极以及沟道区域；
208 )剥离剩余的光刻胶；
209 )在源电极、 漏电极及沟道区域上釆用 PECVD 方法或者其他方式 沉积形成钝化层 5;
2010 )通过构图工艺在钝化层 5上形成过孔 4。
上述本实施例的阵列基板制造方法仅仅是制造本发明所提供的阵列基板 的一种实现方法， 实际操作中， 还可以通过增加或减少构图工艺次数、 选择 不同的材料等方式改变上述具体步骤。
在上述阵列基板制造方法中， 通过在非贴合区域 3中的钝化层 5与衬底 基板之间增加增高层 6， 从而减少或者消除贴合区域 2中的钝化层与非贴合 区域 3中的钝化层的高度差异， 使贴合区域 2中的钝化层和非贴合区域 3中 的钝化层平坦化（即相互齐平），从而解决了钝化层脱落问题， 降低了接线不 良现象的发生， 提高了产品的可靠性。 本实施例还提供了一种包括上述任意一种阵列基板的显示装置。 该显示 装置例如是： 液晶显示面板、 电子纸、 OLED (有机发光二极管）显示面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等任何具有显示功能的 产品或部件。
由于该显示装置中， 阵列基板的贴合区域 2中的钝化层和非贴合区域 2 中的钝化层为平坦的， 因此避免出现钝化层脱落， 降低了接线不良现象的发 生， 提高了产品的可靠性。
本申请基于并且要求于 2013 年 9 月 29 日递交的中国专利申请第 201310455200.1号的优先权， 在此全文引用上述中国专利申请公开的内容。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板， 包括：
衬底基板； 以及
设置在所述衬底基板上的多条数据线；
其中衬底基板包括与各条数据线的端部相贴合的多个贴合区域和位于相 邻贴合区域之间的非贴合区域， 所述非贴合区域中的钝化层与衬底基板之间 设置有增高层。
2、根据权利要求 1所述的阵列基板，还包括设置在衬底基板上的栅极金 属层； 所述增高层与所述栅极金属层同层设置且材质相同。
3、根据权利要求 1或 2所述的阵列基板，其中所述数据线的端部与衬底 基板之间设置有有源层； 所述增高层的厚度等于所述数据线与所述有源层的 厚度之和。
4、根据权利要求 1-3任意一项所述的阵列基板， 其中所述增高层的长度 等于或大于所述贴合区域的长度。
5、根据权利要求 1-4任意一项所述的阵列基板， 其中所述增高层的厚度 设置为使所述非贴合区域和所述贴合区域中的钝化层齐平。
6、 一种阵列基板制造方法， 包括：
提供衬底基板， 其中所述衬底基板上设置有多条数据线， 所述衬底基板 包括与各条数据线的端部相贴合的多个贴合区域和位于相邻贴合区域之间的 非贴合区域； 以及
在衬底基板的非贴合区域中形成增高层。
7、 根据权利要求 6所述的阵列基板制造方法， 还包括：
在衬底基板上形成栅极；
在形成有栅极的衬底基板上依次形成栅绝缘层、 有源层、 数据线、 源漏 金属层、 钝化层以及过孔。
8、根据权利要求 7所述的阵列基板制造方法，其中所述栅极和所述增高 层同时形成在衬底基板上。
9、根据权利要求 8所述的阵列基板制造方法，其中所述在衬底基板上同 时形成栅极以及增高层包括： 在衬底基板上沉积金属薄膜；
通过构图工艺形成所述栅极以及增高层图案。
10、 根据权利要求 9所述的阵列基板制造方法， 其中所述通过构图工艺 形成所述栅极以及增高层图案包括：
在所述金属薄膜上涂覆一层光刻胶；
通过掩模板曝光、 显影， 形成对应所述增高层以及栅极的光刻胶保留区 域以及对应上述区域之外区域的光刻胶去除区域；
通过刻蚀工艺去除光刻胶去除区域中的金属薄膜； 以及
剥离剩余的光刻胶。
11、根据权利要求 6-10任意一项所述的阵列基板制造方法， 其中所述增 高层与所述栅极的材料相同。
12、根据权利要求 6-11任意一项所述的阵列基板制造方法， 其中所述增 高层的厚度等于所述数据线与所述有源层的厚度之和。
13、 一种显示装置， 包括权利要求 1-5任意一项所述的阵列基板。
PCT/CN2014/083562 2013-09-29 2014-08-01 阵列基板及其制造方法、显示装置 WO2015043315A1 (zh)

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CN105549286B (zh) * 2016-03-02 2019-05-24 京东方科技集团股份有限公司 显示面板、显示装置及显示面板的制造方法
CN105932030B (zh) * 2016-06-08 2019-07-26 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置
CN107238962A (zh) * 2017-07-27 2017-10-10 京东方科技集团股份有限公司 一种显示基板的制作方法、显示基板及显示装置
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122989A1 (en) * 2001-12-28 2003-07-03 Hyun-Tak Park Array substrate for a liquid crystal display device and fabricating method thereof
US20040125313A1 (en) * 2002-12-30 2004-07-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
CN101101914A (zh) * 2006-06-26 2008-01-09 Lg.菲利浦Lcd株式会社 阵列基板及其制造方法以及包括其的液晶显示器件
CN101697053A (zh) * 2009-09-23 2010-04-21 深超光电（深圳）有限公司 有源组件阵列基板
CN103500746A (zh) * 2013-09-29 2014-01-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3902693C2 (de) * 1988-01-30 1995-11-30 Toshiba Kawasaki Kk Mehrebenenverdrahtung für eine integrierte Halbleiterschaltungsanordnung und Verfahren zur Herstellung von Mehrebenenverdrahtungen für integrierte Halbleiterschaltungsanordnungen
KR101329288B1 (ko) * 2007-11-13 2013-11-14 삼성디스플레이 주식회사 게이트 구동용 박막 트랜지스터 및 이를 포함하는 액정표시 장치
CN103489918A (zh) * 2012-06-08 2014-01-01 京东方科技集团股份有限公司 一种薄膜晶体管和阵列基板及其制造方法
CN103293727B (zh) * 2012-06-29 2016-02-17 上海中航光电子有限公司 液晶显示装置的阵列基板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122989A1 (en) * 2001-12-28 2003-07-03 Hyun-Tak Park Array substrate for a liquid crystal display device and fabricating method thereof
US20040125313A1 (en) * 2002-12-30 2004-07-01 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and method of fabricating the same
CN101101914A (zh) * 2006-06-26 2008-01-09 Lg.菲利浦Lcd株式会社 阵列基板及其制造方法以及包括其的液晶显示器件
CN101697053A (zh) * 2009-09-23 2010-04-21 深超光电（深圳）有限公司 有源组件阵列基板
CN103500746A (zh) * 2013-09-29 2014-01-08 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

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