WO2015037331A1 - Dispositif d'affichage et son procédé de commande - Google Patents

Dispositif d'affichage et son procédé de commande Download PDF

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Publication number
WO2015037331A1
WO2015037331A1 PCT/JP2014/069285 JP2014069285W WO2015037331A1 WO 2015037331 A1 WO2015037331 A1 WO 2015037331A1 JP 2014069285 W JP2014069285 W JP 2014069285W WO 2015037331 A1 WO2015037331 A1 WO 2015037331A1
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Prior art keywords
period
circuit
measurement
voltage
drive
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PCT/JP2014/069285
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English (en)
Japanese (ja)
Inventor
将紀 小原
野口　登
宣孝 岸
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シャープ株式会社
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Priority to US14/895,503 priority Critical patent/US9734754B2/en
Publication of WO2015037331A1 publication Critical patent/WO2015037331A1/fr
Priority to US15/648,581 priority patent/US9886894B2/en

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
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    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
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    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to a display device, and more particularly, to a display device including a current-driven light emitting element such as an organic EL element and a driving method thereof.
  • organic EL (Electro Luminescence) display devices have attracted attention as display devices that are thin, lightweight, and capable of high-speed response.
  • the organic EL display device includes a plurality of pixel circuits arranged two-dimensionally.
  • the pixel circuit of the organic EL display device includes an organic EL element and a driving transistor.
  • the drive transistor is provided in series with the organic EL element, and controls the amount of current flowing through the organic EL element (hereinafter referred to as drive current).
  • the organic EL element emits light with a luminance corresponding to the amount of drive current.
  • the characteristics (threshold voltage and mobility) of the drive transistor vary.
  • variations in the characteristics of the drive transistors variations in the amount of drive current occur, resulting in uneven brightness on the display screen.
  • Patent Document 1 discloses an organic EL display in which a drive current is read out via a power supply line, a correction gain and a correction offset are updated based on the measured amount of drive current, and a video signal is corrected using these.
  • An apparatus is described.
  • the drive current is read out via a data line, the threshold voltage of the drive transistor is updated based on the comparison result between the measured drive current amount and the target amount, and the video signal is corrected using this.
  • An organic EL display device is described.
  • Pause driving is a driving method in which when the same image is continuously displayed, the frame period is classified into a driving period and a pausing period, the driving circuit is operated during the driving period, and the operation of the driving circuit is stopped during the pausing period.
  • the pause drive can be applied when the off-leak characteristics of the transistors in the pixel circuit are good (the off-leak current is small).
  • Patent Document 3 A display device that performs pause driving is described in Patent Document 3, for example.
  • a voltage corresponding to a video signal (hereinafter referred to as a data voltage) is written to pixel circuits in all rows within one frame period, and output from the pixel circuits for one row.
  • a display device that measures the measured drive current is referred to as a pixel circuit to be measured.
  • FIG. 18 is a timing chart of the display device according to the comparative example.
  • FIG. 18 shows changes in the voltages of the scanning lines SL1 to SLm when the pixel circuit in the i-th row is the measurement target.
  • the voltages of the scanning lines SL1 to SLm are controlled to the high level in order of one line period (each time Ts1).
  • the voltage of the scanning line SLi is controlled to the high level only for the time Ts2 (> Ts1) in order to perform the writing of the data voltage and the measurement of the driving current.
  • the time Ts2 is, for example, about several times the time Ts1.
  • the selection period of the scanning line SLi corresponding to the pixel circuit to be measured is longer than the selection period of the other scanning lines.
  • scanning lines whose selection period is longer than other scanning lines are switched every frame period.
  • a scanning line driving circuit of a display device is generally configured by connecting flip-flops in multiple stages, supplying a clock signal to the clock terminal of each stage flip-flop, and supplying a start pulse to the input terminal of the first stage flip-flop.
  • the scanning line driving circuit of the display device according to the comparative example needs to control the scanning line voltage as shown in FIG. For this reason, in the display device according to the comparative example, the configuration of the scanning line driving circuit is more complicated than in a general display device.
  • the drive current is a minute current of the order of ⁇ A or less, it is necessary to lengthen the measurement time in order to accurately measure the drive current.
  • the data voltage is written to the pixel circuits in all rows within one frame period, so that it is not possible to secure a sufficient time for measuring the drive current.
  • the display device according to the comparative example has a problem in that variations in characteristics of the drive transistor cannot be sufficiently compensated, and luminance unevenness in the display screen cannot be sufficiently suppressed.
  • the display device according to the comparative example also has a problem that power consumption at the peak time is large because data voltage writing and driving current measurement are performed in the same frame period.
  • an object of the present invention is to provide a low power consumption display device that has a scanning line driving circuit with a simple configuration and can effectively suppress uneven luminance, and a driving method thereof.
  • a first aspect of the present invention is a display device including a current-driven light emitting element, A plurality of pixel circuits arranged corresponding to the intersections of the plurality of scanning lines and the plurality of data lines; A driving circuit for writing a voltage to the pixel circuit by driving the scanning line and the data line; A measurement circuit for measuring the drive current output from the pixel circuit to the data line; A correction circuit for correcting the video signal based on the drive current measured by the measurement circuit;
  • the pixel circuit includes: A light emitting element; A driving transistor that is provided in series with the light emitting element and outputs a driving current in an amount corresponding to a voltage between a control terminal and the conduction terminal on the light emitting element side; An input / output transistor provided between a conduction terminal on the light emitting element side of the driving transistor and the data line, and having a control terminal connected to the scanning line;
  • the drive circuit classifies the frame period into a drive period and a pause period, and in the drive period, a selection voltage is sequential
  • the drive circuit applies a voltage corresponding to the corrected video signal to the data line during a scanning line selection period corresponding to a pixel circuit that is not a measurement target within the drive period, and the measurement target pixel circuit within the drive period A measuring voltage is applied to the data line in a scanning line selection period corresponding to the above.
  • the drive circuit classifies the four frame periods in order into a first drive period, a first idle period, a second drive period, and a second idle period, and corresponds to the pixel circuit to be measured in the first drive period
  • the first measurement voltage is applied to the data line
  • the second measurement voltage is applied to the data line.
  • the measurement circuit measures the drive current output from the pixel circuit to be measured as the first drive current in the first pause period, and performs the second drive on the drive current output from the pixel circuit to be measured in the second pause period.
  • the correction circuit corrects a part related to a pixel circuit to be measured in the video signal based on the first and second drive currents.
  • the driving circuit applies a voltage corresponding to the corrected video signal to the data line during the selection period of each scanning line within the driving period, sets a writing period and a measuring period during the pause period, and measures during the writing period. Voltage is applied to the data line, The measurement circuit measures a drive current output from a pixel circuit to be measured in a measurement period.
  • the drive circuit sequentially sets a first write period, a first measurement period, a second write period, and a second pause period within a pause period, and a first measurement voltage is applied to the data line during the first write period. And applying a second measurement voltage to the data line in the second writing period;
  • the measurement circuit measures the drive current output from the pixel circuit to be measured as the first drive current in the first measurement period, and performs the second drive on the drive current output from the pixel circuit to be measured in the second measurement period.
  • the correction circuit corrects a part related to a pixel circuit to be measured in the video signal based on the first and second drive currents.
  • a sixth aspect of the present invention is the fifth aspect of the present invention,
  • the driving circuit sets a third writing period after the second measurement period within the pause period, and applies a voltage corresponding to the corrected video signal to the data line in the third writing period.
  • the driving circuit applies the selection voltage to one scanning line corresponding to a pixel circuit to be measured in one pause period.
  • the driving circuit applies the selection voltage in order to a plurality of scanning lines corresponding to a pixel circuit to be measured in one pause period.
  • the driving circuit applies a voltage corresponding to the corrected video signal to the data line during a selection period of each scanning line within the driving period, and applies the voltage to the scanning line during a continuous pause period including a plurality of continuous pause periods.
  • a writing period and a measurement period are set within a selection period of each scanning line, and a measurement voltage is applied to the data line in each writing period, The measurement circuit measures the drive current output from the pixel circuit to be measured in each measurement period.
  • the driving circuit applies a selection voltage to all the scanning lines in order in one continuous rest period.
  • An eleventh aspect of the present invention is the tenth aspect of the present invention,
  • the drive circuit applies a first measurement voltage to the data line in each write period within a first continuous pause period, and applies a second measurement voltage to the data line in each write period within a second continuous pause period.
  • the measurement circuit measures the drive current output from the pixel circuit to be measured as the first drive current in each measurement period within the first continuous pause period, and the measurement target in each measurement period within the second continuous pause period.
  • the correction circuit corrects a part related to a circuit to be measured in the video signal based on the first and second drive currents.
  • a storage unit for storing the first and second correction data used for correcting the video signal for each pixel circuit The correction circuit updates first correction data related to the pixel circuit to be measured based on the first drive current, updates second correction data related to the pixel circuit to be measured based on the second drive current, and And based on 2nd correction data, the part regarding the pixel circuit of a measurement object is correct
  • the driving circuit includes a first scanning line driving circuit that drives the scanning line during a driving period and a second scanning line driving circuit that drives the scanning line during a pause period.
  • the drive circuit and the measurement circuit share a drive / measurement circuit corresponding to the data line
  • the driving / measuring circuit includes an operational amplifier having an inverting input terminal connected to the data line, a switching element provided between an inverting input terminal and an output terminal of the operational amplifier, and the operational amplifier in parallel with the switching element.
  • a passive element provided between the inverting input terminal and the output terminal of The passive element is any one of a capacitive element and a resistive element.
  • a fifteenth aspect of the present invention is arranged corresponding to the intersections of a plurality of scanning lines and a plurality of data lines, each of which is provided in series with the current-driven light emitting element, the control terminal, A driving transistor that outputs a driving current in an amount corresponding to a voltage between the light emitting element side and a conduction terminal; and the light emitting element side conduction terminal of the driving transistor and the data line, and the scanning
  • a driving method of a display device including a plurality of pixel circuits having an input / output transistor having a control terminal connected to a line, A driving step of writing a voltage to the pixel circuit by driving the scanning line and the data line; A measurement step of measuring a drive current output from the pixel circuit to the data line; A correction step for correcting the video signal based on the measured drive current,
  • the frame period is classified into a driving period and a pause period.
  • a selection voltage is sequentially applied to the scanning lines, and a voltage to be written in the pixel circuit is sequentially applied to the data line. Applying the selection voltage to one or more scanning lines corresponding to the pixel circuit to be measured; In the measuring step, the driving current output from the pixel circuit to be measured is measured in the idle period.
  • the frame period is classified into a drive period and a pause period, and the drive current output from the pixel circuit to be measured to the data line is measured in the pause period.
  • a scanning line driver circuit that applies a selection voltage to a plurality of scanning lines in order during the driving period and applies a selection voltage to one or more scanning lines during the rest period has a simple configuration.
  • by measuring the drive current during the rest period it is possible to ensure sufficient time for measurement of the drive current, effectively compensate for variations in the characteristics of the drive transistor, and effectively suppress luminance unevenness in the display screen can do.
  • voltage writing and driving current measurement in different frame periods power consumption at the peak time can be reduced. Therefore, a display device with low power consumption that has a scan line driver circuit with a simple configuration and can effectively suppress luminance unevenness, or a driving method thereof can be provided.
  • the measurement voltage is written to the pixel circuit to be measured in the driving period. Therefore, it is possible to measure the drive current output from the pixel circuit in which the measurement voltage is written in the subsequent rest period.
  • writing of the measurement voltage and measurement of the drive current are performed twice for the pixel circuit to be measured within the four frame period, and the video signal is converted into two measurement results. Based on correction. Therefore, it is possible to compensate for variations in the two types of characteristics (for example, threshold voltage and mobility) of the drive transistor, and to effectively suppress luminance unevenness in the display screen.
  • the measurement voltage is written into the pixel circuit to be measured in the writing period within the idle period. Therefore, in the subsequent measurement period, the drive current output from the pixel circuit in which the measurement voltage is written can be measured.
  • the measurement voltage is written to the measurement target pixel circuit and the drive current is measured twice in one frame period, and the video signal is converted into two measurement results. Based on correction. Therefore, it is possible to compensate for variations in the two types of characteristics of the drive transistor and to effectively suppress uneven brightness in the display screen.
  • the voltage corresponding to the video signal corrected based on the measurement results in the first and second measurement periods is written into the pixel circuit to be measured in the third writing period. Therefore, the result of compensating for the variation in the characteristics of the drive transistor can be immediately reflected in the display image.
  • the seventh aspect of the present invention it is possible to compensate for variations in the characteristics of the drive transistors for a plurality of pixel circuits connected to one scanning line in one pause period.
  • the eighth aspect of the present invention it is possible to compensate for variations in the characteristics of the drive transistors for a plurality of pixel circuits connected to a plurality of scanning lines in one idle period.
  • the measurement voltage is written to the pixel circuit to be measured in each writing period within the continuous pause period. Therefore, in the subsequent measurement period, the drive current output from the pixel circuit in which the measurement voltage is written can be measured.
  • variations in the characteristics of the drive transistors can be compensated for all the pixel circuits in one continuous pause period.
  • the writing of the measurement voltage and the measurement of the drive current are performed twice for all the pixel circuits within the two continuous pause periods, and the video signal is measured by two measurements. It is corrected based on the result. Therefore, it is possible to compensate for variations in the two types of characteristics of the drive transistor and to effectively suppress uneven brightness in the display screen.
  • two correction data are stored for each pixel circuit, two correction data are updated based on two measurement results, and a video signal is converted based on the two correction data.
  • the scanning line driving circuit can be easily configured by dividing into a circuit operating in the driving period and a circuit operating in the idle period.
  • the drive / measurement circuit applies the voltage applied to the non-inverting input terminal of the operational amplifier to the data line when the switch element is in the on state, and the data when the switch element is in the off state.
  • a voltage corresponding to the drive current output to the line is output from the output terminal of the operational amplifier. Therefore, it is possible to easily configure a drive circuit that writes a voltage to the pixel circuit and a measurement circuit that measures the drive current output from the pixel circuit to the data line using the drive / measurement circuit.
  • FIG. 2 is a circuit diagram showing a part of a pixel circuit and a data line drive / current measurement circuit of the display device shown in FIG. 1. It is a figure which shows the operation
  • movement in the drive period and idle period of the display apparatus shown in FIG. 2 is a timing chart of a driving period of the display device shown in FIG. It is a timing chart of the idle period of the display apparatus shown in FIG. It is a figure which shows the voltage write-in operation
  • FIG. 2 is a diagram showing gradation-current characteristics of the display device shown in FIG.
  • FIG. 2 is a circuit diagram of first and second scanning line driving circuits of the display device shown in FIG. 1.
  • 3 is a timing chart of a first scanning line driving circuit of the display device shown in FIG. 1.
  • 3 is a timing chart of a second scanning line driving circuit of the display device shown in FIG.
  • FIG. 2 is a circuit diagram of a power supply voltage selection circuit of the display device shown in FIG. 1. It is a timing chart of the idle period of the display apparatus which concerns on the 2nd Embodiment of this invention.
  • FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention.
  • a display device 10 shown in FIG. 1 includes a display unit 11, a display control circuit 12, a first scanning line driving circuit 13, a second scanning line driving circuit 14, a data line driving / current measuring circuit 15, a power supply voltage selecting circuit 16,
  • a The organic EL display device includes a / D converter 17, a correction arithmetic circuit 18, and a correction data storage unit 19.
  • m and n are integers of 2 or more
  • i is an integer of 1 to m
  • j is an integer of 1 to n.
  • the display unit 11 includes m scanning lines SL1 to SLm, n data lines DL1 to DLn, m power lines PL1 to PLm, and (m ⁇ n) pixel circuits 20.
  • Scan lines SL1 to SLm and power supply lines PL1 to PLm are arranged in parallel to each other.
  • the data lines DL1 to DLn are arranged in parallel to each other so as to be orthogonal to the scanning lines SL1 to SLm.
  • the scanning lines SL1 to SLm and the data lines DL1 to DLn intersect at (m ⁇ n) locations.
  • the (m ⁇ n) pixel circuits 20 are arranged corresponding to the intersections of the scanning lines SL1 to SLm and the data lines DL1 to DLn.
  • the extending direction (horizontal direction in FIG. 1) of the scanning lines SL1 to SLm is referred to as the row direction
  • the extending direction (vertical direction in FIG. 1) of the data lines DL1 to DLn is referred to as the column direction.
  • the pixel circuit 20 is referred to as PX (i, j).
  • the first scanning line driving circuit 13 is arranged along one side (right side in FIG. 1) of the display unit 11.
  • the second scanning line driving circuit 14 and the power supply voltage selection circuit 16 are arranged along the opposite sides (left side in FIG. 1) of the display unit 11.
  • the data line drive / current measurement circuit 15 is arranged along the remaining one side (lower side in FIG. 1) of the display unit 11.
  • the display control circuit 12 outputs a control signal to control the operation of the display device 10. More specifically, the display control circuit 12 outputs a control signal C1 to the first scanning line driving circuit 13, and outputs a control signal C2 to the second scanning line driving circuit 14, thereby data line driving / current. A control signal C3 is output to the measurement circuit 15. Further, the display control circuit 12 outputs the video signal D1 (video signal before correction) to the correction arithmetic circuit 18.
  • the first scanning line driving circuit 13 and the second scanning line driving circuit 14 drive the scanning lines SL1 to SLm.
  • the data line drive / current measurement circuit 15 selectively performs an operation of driving the data lines DL1 to DLn and an operation of measuring the drive current output from the pixel circuit 20 to the data lines DL1 to DLn.
  • the first scanning line driving circuit 13, the second scanning line driving circuit 14, and the data line driving / current measuring circuit 15 drive the scanning lines SL1 to SLm and the data lines DL1 to DLn to thereby apply a voltage to the pixel circuit 20. Functions as a drive circuit for writing.
  • the data line drive / current measurement circuit 15 also functions as a measurement circuit that measures the drive current output from the pixel circuit 20 to the data lines DL1 to DLn.
  • the power supply voltage selection circuit 16 selectively applies the first low level power supply voltage ELVSS for display and the second low level power supply voltage ELVSS_moni for current measurement to the power supply lines PL1 to PLm.
  • Each pixel circuit 20 is supplied with a high level power supply voltage ELVDD and a reference voltage Vref from a power supply circuit (not shown).
  • the correction data storage unit 19 stores two types of correction data used for correcting the video signal D1. More specifically, the correction data storage unit 19 includes a threshold voltage correction data storage unit 47 and a mobility correction data storage unit 48.
  • the threshold voltage correction data storage unit 47 stores threshold voltage correction data Vt (i, j) for each pixel circuit PX (i, j).
  • the mobility correction data storage unit 48 stores mobility correction data B (i, j) for each pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 outputs a voltage corresponding to the drive current output from the pixel circuit 20 to the data lines DL1 to DLn.
  • the A / D converter 17 converts the voltage output from the data line drive / current measurement circuit 15 into a digital value. This digital value represents the amount of drive current output from the pixel circuit 20.
  • the correction calculation circuit 18 updates the correction data stored in the correction data storage unit 19 based on the digital value output from the A / D converter 17.
  • the correction calculation circuit 18 corrects the video signal D1 with reference to the correction data stored in the correction data storage unit 19, and outputs the corrected video signal D2.
  • the data line drive / current measurement circuit 15 drives the data lines DL1 to DLn based on the corrected video signal D2.
  • FIG. 2 is a circuit diagram showing a part of the pixel circuit 20 and the data line drive / current measurement circuit 15.
  • FIG. 2 shows a pixel circuit PX (i, j) in the i-th row and j-th column and a portion corresponding to the data line DLj in the data line driving / current measuring circuit 15.
  • the pixel circuit 20 includes N-channel TFTs (Thin Film Transistors) 21 to 23, a capacitor 24, and an organic EL element 25.
  • TFTs 21 to 23 TFTs having good off-leak characteristics are used.
  • TFTs 21 to 23 for example, TFTs having a semiconductor layer formed of indium-gallium-zinc oxide (IGZO) are used.
  • IGZO indium-gallium-zinc oxide
  • the high level power supply voltage ELVDD is applied to the drain terminal of the TFT 21.
  • the source terminal of the TFT 21 is connected to the anode terminal of the organic EL element 25, and the cathode terminal of the organic EL element 25 is connected to the power supply line PLi.
  • One conduction terminal of the TFT 22 is connected to the data line DLj, and the other conduction terminal of the TFT 22 is connected to the source terminal of the TFT 21.
  • a reference voltage Vref is applied to the drain terminal of the TFT 23, and the source terminal of the TFT 23 is connected to the gate terminal of the TFT 21.
  • the gate terminal of the TFT 22 and the gate terminal of the TFT 23 are connected to the scanning line SLi.
  • the capacitor 24 is provided between the gate terminal and the source terminal of the TFT 21.
  • the organic EL element 25 is a current-driven light emitting element.
  • the TFT 21 is provided in series with the organic EL element 25 and functions as a drive transistor that outputs a drive current in an amount corresponding to the gate-source voltage.
  • the TFT 22 is provided between the source terminal of the TFT 21 and the data line DLj, and functions as an input / output transistor having a gate terminal connected to the scanning line SLi.
  • the TFT 23 is provided between the wiring having the reference voltage Vref and the gate terminal of the TFT 21 and functions as a reference voltage application transistor having a gate terminal connected to the scanning line SLi.
  • the capacitor 24 functions as a holding capacitor that holds the gate-source voltage of the TFT 21.
  • the data line drive / current measurement circuit 15 includes a D / A converter 31, an operational amplifier 32, a capacitor 33, and a switch 34 corresponding to the data line DLj.
  • a data voltage value Vm (i, j, P) included in the video signal D2 is applied to the input terminal of the D / A converter 31.
  • the D / A converter 31 converts the data voltage value Vm (i, j, P) into an analog data voltage (represented as Vm (i, j, P) as with the data voltage value).
  • the output terminal of the D / A converter 31 is connected to the non-inverting input terminal of the operational amplifier 32.
  • the inverting input terminal of the operational amplifier 32 is connected to the data line DLj.
  • the switch 34 is provided between the inverting input terminal and the output terminal of the operational amplifier 32.
  • the capacitor 33 is provided between the inverting input terminal and the output terminal of the operational amplifier 32 in parallel with the switch 34.
  • An input / output control signal DWT included in the control signal C3 is applied to the control terminal of the switch 34.
  • the output terminal of the operational amplifier 32 is connected to the input terminal of the A / D converter 17.
  • the switch 34 When the input / output control signal DWT is at a high level, the switch 34 is turned on, and the inverting input terminal and the output terminal of the operational amplifier 32 are short-circuited. At this time, the operational amplifier 32 functions as a buffer amplifier, and the data voltage Vm (i, j, P) given to the non-inverting input terminal of the operational amplifier 32 is applied to the data line DLj.
  • the switch 34 When the input / output control signal DWT is at a low level, the switch 34 is turned off, and the inverting input terminal and the output terminal of the operational amplifier 32 are connected via the capacitor 33.
  • the operational amplifier 32 and the capacitor 33 function as an integration circuit, and the output voltage of the operational amplifier 32 is a voltage corresponding to the drive current output from the pixel circuit 20 to the data line DLj.
  • the A / D converter 17 converts the output voltage of the operational amplifier 32 into a digital value.
  • the drive current measured by the data line drive / current measurement circuit 15 is referred to as Im (i, j, P)
  • the digital value output from the A / D converter 17 is referred to as the drive current value.
  • it is expressed as Im (i, j, P).
  • the display device 10 performs rest driving that classifies the frame period into a driving period and a rest period.
  • the display device 10 writes the display data voltage to the pixel circuit 20 during the driving period, and does not write the display data voltage to the pixel circuit 20 during the idle period. Further, the display device 10 measures the driving current output from the pixel circuits 20 for one row to the data lines DL1 to DLn during the idle period, and the correction data stored in the correction data storage unit 19 based on the driving current value. Update.
  • the first gradation P1 and the second gradation P2 are determined in advance within the display gradation range.
  • the data line drive / current measurement circuit 15 generates a first measurement voltage Vm (i, j, P1) for writing the first gradation P1 to the pixel circuit PX (i, j), and the first measurement voltage.
  • the drive current output from the pixel circuit PX (i, j) in which Vm (i, j, P1) is written is measured as the first drive current Im (i, j, P1).
  • the correction calculation circuit 18 uses the threshold voltage correction data Vt ( i, j) is updated.
  • the data line drive / current measurement circuit 15 generates a second measurement voltage Vm (i, j, P2) for writing the second gradation P2 in the pixel circuit PX (i, j), and performs the second measurement.
  • the drive current output from the pixel circuit PX (i, j) to which the working voltage Vm (i, j, P2) is written is measured as the second drive current Im (i, j, P2).
  • the correction calculation circuit 18 uses the mobility correction data B (stored in the mobility correction data storage unit 48). i, j) is updated.
  • the display device 10 performs pause driving in which the driving period and the pause period are alternately switched every frame period.
  • FIG. 3 is a diagram illustrating operations of the display device 10 during a driving period and a rest period.
  • the drive circuit of the display device 10 includes four consecutive frame periods F1 to F4 in a first drive period F1, a first pause period F2, a second drive period F3, and a second pause period.
  • the frame period is classified as F4, and the next frame period after the second pause period F4 is classified as the third drive period F5.
  • the display device 10 writes the first measurement voltage Vm (i, j, P1) to the pixel circuit PX (i, j) to be measured and displays the other pixel circuits for display.
  • the display device 10 measures the first drive current Im (i, j, P1) output from the pixel circuit PX (i, j) to be measured.
  • the display device 10 writes the second measurement voltage Vm (i, j, P2) to the pixel circuit PX (i, j) to be measured and displays the other pixel circuits for display. Write data voltage.
  • the display device 10 measures the second drive current Im (i, j, P2) output from the pixel circuit PX (i, j) to be measured.
  • the display device 10 writes the first measurement voltage to the next pixel circuit to be corrected, and displays the other measurement circuits (including the pixel circuit PX (i, j)). Write data voltage.
  • the data voltage written to the pixel circuit PX (i, j) in the third driving period F5 is the first driving current value Im (i, j, P1) and the second driving current value Im (i, j, P2). Based on the corrected video signal D2 obtained by updating the two types of correction data stored in the correction data storage unit 19 and referring to the updated correction data.
  • FIG. 4 is a timing chart of the driving period of the display device 10.
  • the second scanning line driving circuit 14 stops operating.
  • the first scanning line driving circuit 13 sequentially selects the scanning lines SL1 to SLm one line period at a time, and applies a selection voltage (here, a high level voltage) to the selected scanning line.
  • the data line drive / current measurement circuit 15 applies n data voltages based on the corrected video signal D2 to the data lines DL1 to DLn, respectively. However, when the pixel circuit in the i-th row is the measurement target, the data line drive / current measurement circuit 15 applies the first measurement voltage Vm (i, i) to the data lines DL1 to DLn in the selection period of the scanning line SLi.
  • the power supply voltage selection circuit 16 applies the first low level power supply voltage ELVSS to the power supply lines PL1 to PLm.
  • the pixel circuits 20 for one row are sequentially selected for each line period, and the data voltage or the measurement voltage is written to the pixel circuits 20 in the selected row. Thereby, the data voltage or the measurement voltage can be written to all the pixel circuits 20 within one driving period.
  • FIG. 5 is a timing chart of the pause period of the display device 10.
  • the first scanning line driving circuit 13 stops operating.
  • the second scanning line driving circuit 14 applies a selection voltage to the scanning line SLi over one frame period.
  • the power supply voltage selection circuit 16 applies the second low level power supply voltage ELVSS_moni to the power supply line PLi and applies the first low level power supply voltage ELVSS to the other power supply lines.
  • the data line drive / current measurement circuit 15 measures the drive current output from the pixel circuit 20 to be measured to the data lines DL1 to DLn. As a result, n drive currents output from the n pixel circuits 20 within one pause period can be measured.
  • the data line drive / current measurement circuit 15 measures the first drive current Im (i, j, P1) in the first idle period F2, and the second drive current Im (i, j, P2) in the second idle period F4. Measure.
  • the pixel circuit to be measured is switched every two pause periods. As a result, the two types of correction data stored in the correction data storage unit 19 for all the pixel circuits 20 can be updated within the 2m pause period.
  • FIG. 6 is a diagram illustrating a voltage writing operation of the display device 10.
  • the voltage writing operation for the pixel circuit PX (i, j) will be described.
  • the voltage writing is performed within the driving period.
  • the driving period the first low-level power supply voltage ELVSS is applied to the power supply line PLi.
  • the selection period of the pixel circuit 20 in the i-th row the voltage of the scanning line SLi is at a high level, and the voltages of other scanning lines are at a low level (see FIG. 4).
  • a data voltage Vm (i, j, P) for writing the gradation P to the pixel circuit PX (i, j) is applied to the data line DLj.
  • the first measurement voltage Vm (i, j, P1) or the second measurement voltage Vm (i, j, P2) is applied to the data line DLj. Is done.
  • the TFTs 22 and 23 are turned on. Therefore, the voltage of the data line DLj is applied to the source terminal of the TFT 21 via the TFT 22, and the reference voltage Vref is applied to the gate terminal of the TFT 21 via the TFT 23.
  • a drive current Id flows between the drain and source of the TFT 21, and the organic EL element 25 emits light with a luminance corresponding to the drive current Id.
  • the amount of the drive current Id and the luminance of the organic EL element 25 depend on the gate-source voltage Vgs of the TFT 21, the high level power supply voltage ELVDD, and the first low level power supply voltage ELVSS.
  • the TFTs 22 and 23 are turned off. Thereafter, the gate-source voltage Vgs of the TFT 21 is maintained at the previous level by the action of the capacitor 24. Therefore, the organic EL element 25 continues to emit light with a luminance corresponding to the gate-source voltage Vgs of the TFT 21.
  • FIG. 7 is a diagram illustrating a current measurement operation of the display device 10.
  • the current measurement operation for the pixel circuit PX (i, j) will be described. Current measurements are made during the rest period.
  • the voltage of the scanning line SLi is at a high level and the voltages of the other scanning lines are at a low level during the idle period (see FIG. 5).
  • the second low level power supply voltage ELVSS_moni is applied to the power supply line PLi
  • the first low level power supply voltage ELVSS is applied to the other power supply lines.
  • the second low-level power supply voltage ELVSS_moni is determined so as to satisfy the following expression (1).
  • the TFTs 22 and 23 are turned on. At this time, a drive current Id flows between the drain and source of the TFT 21.
  • the amount of the drive current Id depends on the gate-source voltage Vgs of the TFT 21, the high-level power supply voltage ELVDD, and the second low-level power supply voltage ELVSS_moni. However, since Formula (1) is established, the drive current Id does not flow to the organic EL element 25 but flows to the data line drive / current measurement circuit 15 via the TFT 22 and the data line DLj.
  • the data line drive / current measurement circuit 15 measures the drive current Id output from the pixel circuit PX (i, j), and uses the result as the first drive current Im (i, j, P1) or the second drive current Im. Output as (i, j, P2).
  • the TFTs 22 and 23 are turned off.
  • the state of the pixel circuit PX (i, j) does not change until the voltage of the scanning line SLi next changes to the high level.
  • FIG. 8 is a block diagram showing details of the correction arithmetic circuit 18.
  • the correction arithmetic circuit 18 includes a first LUT 41, a multiplier 42, an adder 43, a subtracter 44, a second LUT 45, and a CPU 46.
  • reference symbol P represents a gradation included in the video signal D1.
  • the correction arithmetic circuit 18 refers to the two types of correction data stored in the correction data storage unit 19 to correct the video signal D1 and the two drive current values output from the A / D converter 17. Based on this, an operation of updating two types of correction data stored in the correction data storage unit 19 is performed.
  • the correction calculation circuit 18 functions as a correction circuit that corrects the video signal based on the drive current measured by the measurement circuit (data line drive / current measurement circuit 15).
  • the CPU 46 may be constituted by an arithmetic circuit.
  • the first LUT 41 stores an overdrive voltage Vc (P) corresponding to each gradation P for display.
  • the first LUT 41 converts the gradation P included in the video signal D1 into an overdrive voltage Vc (P).
  • the multiplier 42 multiplies the overdrive voltage Vc (P) and the mobility correction data B (i, j) read from the mobility correction data storage unit 48.
  • the adder 43 adds the output of the multiplier 42 and the threshold voltage correction data Vt (i, j) read from the threshold voltage correction data storage unit 47.
  • the subtracter 44 subtracts the output of the adder 43 from the value of the reference voltage Vref. Thereby, the correction calculation shown in the following equation (2) is performed on the gradation P included in the video signal D1.
  • Vm (i, j, P) Vref ⁇ Vc (P) ⁇ B (i, j) ⁇ Vt (i, j) (2)
  • the correction calculation circuit 18 outputs a corrected video signal D2 including the obtained data voltage value Vm (i, j, P).
  • the data line drive / current measurement circuit 15 drives the data lines DL1 to DLn based on the corrected video signal D2.
  • the second LUT 45 stores a first target current value I (P1) corresponding to the first gradation P1 and a second target current value I (P2) corresponding to the second gradation P2.
  • the second LUT 45 outputs the first target current value I (P1) in the first pause period F2, and outputs the second target current value I (P2) in the second pause period F4.
  • the CPU 46 receives the first drive current value Im (i, j, P1) from the A / D converter 17 in the first idle period F2, and the second drive current value from the A / D converter 17 in the second idle period F4. Im (i, j, P2) is received.
  • the CPU 46 compares the first drive current value Im (i, j, P1) with the first target current value I (P1) and compares the result. Accordingly, the threshold voltage correction data Vt (i, j) stored in the threshold voltage correction data storage unit 47 is updated.
  • the CPU 46 adds ⁇ V to the threshold voltage correction data Vt (i, j) when the following equation (3) holds, ⁇ V is subtracted from threshold voltage correction data Vt (i, j) when equation (4) is satisfied, and threshold voltage correction data Vt (i, j) is not updated when equation (5) is satisfied. .
  • the first drive current value Im (i, j, P1) approaches the first target current value I (P1) stepwise, and finally converges to the first target current value I (P1).
  • ⁇ V_dz (5)
  • the CPU 46 When the CPU 46 receives the second drive current value Im (i, j, P2), the CPU 46 compares the second drive current value Im (i, j, P2) with the second target current value I (P2).
  • the mobility correction data B (i, j) stored in the mobility correction data storage unit 48 is updated according to the comparison result. More specifically, when the update amount is ⁇ B and the dead zone width is B_dz, the CPU 46 adds ⁇ B to the mobility correction data B (i, j) when the following equation (6) is satisfied, If equation (7) holds, ⁇ B is subtracted from mobility correction data B (i, j). If equation (8) holds, mobility correction data B (i, j) is not updated. .
  • the second drive current value Im (i, j, P2) approaches the second target current value I (P2) stepwise and finally converges to the second target current value I (P2).
  • ⁇ B_dz (8)
  • the initial value of the threshold voltage correction data Vt (i, j) is a predetermined voltage value, and the initial value of the mobility correction data B (i, j) is 1.
  • the threshold voltage of the TFT 21 is Vt, and the gain of the TFT 21 is ⁇ .
  • the amount of the drive current Id flowing between the drain and source of the TFT 21 is expressed by the following equation (9) using the gate-source voltage Vgs of the TFT 21.
  • Id ⁇ / 2 ⁇ (Vgs-Vt) 2 (9)
  • a reference voltage Vref is applied to the gate terminal of the TFT 21, and a data voltage Vm (i, j, P) is applied to the source terminal of the TFT 21.
  • Formula (9) can be transformed into the following Formula (10).
  • the threshold voltage correction data Vt (i, j) or the mobility correction data B (i, j) may be increased.
  • the threshold voltage correction data Vt (i, j) or the mobility correction data B (i, j) may be reduced.
  • FIG. 9 is a diagram showing the gradation-current characteristics of the display device 10.
  • the CPU 46 updates the threshold voltage correction data Vt (i, j) and the mobility correction data B (i, j) by the above method. For this reason, the first drive current value Im (i, j, P1) and the second drive current value Im (i, j, P2) finally match the respective target values.
  • the drive current when the first gradation P1 is written to the pixel circuit PX (i, j) and the drive current when the second gradation P2 is written to the pixel circuit PX (i, j) are: It matches each target amount.
  • two black circles correspond to two white circles, respectively.
  • the drive current when an arbitrary gradation P is written in the pixel circuit PX (i, j) substantially matches the target amount corresponding to the gradation P. Therefore, according to the display device 10, by correcting the threshold voltage and mobility of the TFT 21 for each pixel circuit 20, it is possible to perform high-quality display while suppressing luminance unevenness in the display screen.
  • FIG. 10 is a circuit diagram of the first scanning line driving circuit 13 and the second scanning line driving circuit 14.
  • the first scanning line driving circuit 13 includes m flip-flops 51 connected in multiple stages.
  • the flip-flop 51 has a reset terminal R, a clock terminal CK, an input terminal D, and an output terminal Q.
  • a reset signal RST is supplied to the reset terminals R of the m flip-flops 51, and a clock signal CKa is supplied to the clock terminals CK of the m flip-flops 51.
  • a control signal SDa is supplied to the input terminal D of the first-stage flip-flop 51.
  • the input terminal D of the second and subsequent flip-flops 51 is connected to the output terminal Q of the preceding flip-flop 51.
  • the output terminals Q of the m flip-flops 51 are connected to the scanning lines SL1 to SLm, respectively.
  • the second scanning line driving circuit 14 includes m flip-flops 52 and m N-channel transistors 53 connected in multiple stages.
  • a reset signal RST is supplied to the reset terminals R of the m flip-flops 52, and a clock signal CKb is supplied to the clock terminals CK of the m flip-flops 52.
  • a control signal SDb is supplied to the input terminal D of the first-stage flip-flop 52.
  • the input terminal D of the second and subsequent flip-flops 52 is connected to the output terminal Q of the preceding flip-flop 52.
  • the m transistors 53 are provided between the output terminals Q of the m flip-flops 52 and the scanning lines SL1 to SLm, respectively.
  • a control signal CX included in the control signal C2 is supplied to the control terminals of the m transistors 53.
  • FIG. 11 is a timing chart of the first scanning line driving circuit 13.
  • the clock signal CKa is a clock signal with a period of one line period.
  • the control signal SDa becomes high level for one line period at the beginning of the frame period.
  • the output signal SLa1 of the first-stage flip-flop 51 is at the high level.
  • the output signal SLa2 of the second-stage flip-flop 51 becomes high level.
  • the output signals SLa3, SLa4,... Of the flip-flops 51 in the third and subsequent stages sequentially become high level for each line period.
  • the output signals SLa1 to SLam are applied to the scanning lines SL1 to SLm, respectively.
  • FIG. 12 is a timing chart of the second scanning line driving circuit 14.
  • the control signal CX is at a low level during the driving period and is at a high level during the pause period.
  • the clock signal CKb is a clock signal having a period of 4 frame periods, and becomes high level for a predetermined time at the beginning of the driving period.
  • the control signal SDb becomes high level for four frame periods before the pixel circuit 20 in the first row is set as a measurement target. In the next four frame periods after the four frame period in which the control signal SDb is at the high level, the output signal FF1_Q of the first-stage flip-flop 52 is at the high level.
  • the output signal FF2_Q of the second-stage flip-flop 52 becomes high level.
  • the output signals FF3_Q, FF4_Q,... Of the third and subsequent flip-flops 52 sequentially become high level every four frame periods.
  • the m transistors 53 When the control signal CX is at a high level, the m transistors 53 are turned on, and the output signals FF1_Q to FFm_Q of the m flip-flops 52 become the output signals SLb1 to SLbm of the second scanning line driving circuit 14.
  • the control signal CX When the control signal CX is at a low level, the m transistors 53 are turned off, and the output signals SLb1 to SLbm of the second scanning line driving circuit 14 are at a low level.
  • the output signal SLb1 becomes high level when the output signal of the first-stage flip-flop 52 and the control signal CX are high level.
  • the output signal SLb2 becomes high level after 4 frame periods of the high level period of the output signal SLb1.
  • the output signal SLbi becomes a high level after four frame periods of the high level period of the output signal SLbi-1.
  • FIG. 13 is a circuit diagram of the power supply voltage selection circuit 16.
  • the power supply voltage selection circuit 16 includes a P-channel transistor 54 and an N-channel transistor 55 corresponding to the power supply line PLi.
  • the first low level power supply voltage ELVSS is applied to the source terminal of the transistor 54
  • the second low level power supply voltage ELVSS_moni is applied to the source terminal of the transistor 55.
  • the drain terminals of the transistors 54 and 55 are connected to the power supply line PLi.
  • the output signal SLbi of the second scanning line driving circuit 14 is supplied to the gate terminals of the transistors 54 and 55.
  • the output signal SLbi is at a high level during the rest period and when the pixel circuit 20 in the i-th row is the measurement target, and at a low level otherwise.
  • the output signal SLbi is at a high level, so that the transistor 54 is turned off and the transistor 55 is turned on.
  • the second low-level power supply voltage ELVSS_moni is applied to the power supply line PLi via the transistor 55.
  • the output signal SLbi is at a low level, so that the transistor 54 is turned on and the transistor 55 is turned off.
  • the first low-level power supply voltage ELVSS is applied to the power supply line PLi via the transistor 54.
  • the display device according to the comparative example (the display device that drives the scanning lines at the timing shown in FIG. 18) sufficiently suppresses uneven luminance in the display screen, which makes the configuration of the scanning line driving circuit complicated. There is a problem that power consumption at peak time is not possible.
  • the display device 10 classifies the frame period into a driving period and a rest period, and measures a driving current in the rest period.
  • the scanning line driving circuit of the display device 10 sequentially applies a selection voltage to the scanning lines SL1 to SLm in the driving period, and applies a selection voltage to one scanning line SLi corresponding to the pixel circuit to be measured in the pause period ( (See FIGS. 4 and 5).
  • Such a scanning line driving circuit can be easily configured using the first scanning line driving circuit 13 and the second scanning line driving circuit 14 (see FIG. 10). Therefore, according to the display device 10, the configuration of the scanning line driving circuit can be simplified as compared with the display device according to the comparative example.
  • the display device 10 since the drive current is measured in the idle period, a sufficient time can be secured for the drive current measurement. In the longest case, the drive current may be measured over one frame period. The longer the drive current measurement time, the more accurately the drive current can be measured, so that the characteristics (threshold voltage and mobility) of the TFT 21 can be compensated more effectively. Therefore, according to the display device 10, it is possible to effectively compensate for variations in the characteristics of the TFTs 21 compared to the display device according to the comparative example, and to effectively suppress luminance unevenness in the display screen.
  • the display device 10 voltage writing and driving current measurement are performed in different frame periods. Therefore, according to the display device 10, the power consumption at the peak time can be reduced as compared with the display device according to the comparative example.
  • the display device 10 includes (m ⁇ n) pixel circuits 20 and a drive circuit (a first scan line drive circuit 13 and a second scan line) that writes a voltage to the pixel circuit 20.
  • Drive circuit 14 and data line drive / current measurement circuit 15 ), a measurement circuit (data line drive / current measurement circuit 15) for measuring the drive current output from the pixel circuit 20, and a drive measured by the measurement circuit.
  • a correction circuit (correction calculation circuit 18) for correcting the video signal based on the current.
  • the drive circuit classifies the frame period into a drive period and a pause period, and in the drive period, a selection voltage is sequentially applied to the scanning lines SL1 to SLm, and a voltage written to the pixel circuit 20 (data voltage, first measurement voltage, or , The second measurement voltage) is sequentially applied to the data lines DL1 to DLn, and the selection voltage is applied to one scanning line SLi corresponding to the pixel circuit 20 to be measured in the rest period.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured in the idle period. Therefore, according to the display device 10, as described above, the configuration of the scanning line driving circuit can be simplified, luminance unevenness in the display screen can be effectively suppressed, and peak power consumption can be reduced.
  • the driving circuit applies a voltage corresponding to the corrected video signal D2 to the data lines DL1 to DLn in the scanning line selection period corresponding to the pixel circuit 20 that is not the measurement target in the driving period, In the selection period of the scanning line SLi corresponding to the pixel circuit 20 to be measured, the first or second measurement voltage is applied to the data lines DL1 to DLn. In this way, by writing the measurement voltage to the pixel circuit to be measured in the drive period, the drive current output from the pixel circuit to which the measurement voltage is written can be measured in the subsequent pause period.
  • the drive circuit classifies the four frame periods in order into a first drive period, a first idle period, a second drive period, and a second idle period, and the pixel circuit 20 to be measured within the first drive period.
  • the first measurement voltage is applied to the data line DLj during the selection period of the scanning line SLi corresponding to, and the second measurement voltage is selected during the selection period of the scanning line SLi corresponding to the pixel circuit 20 to be measured within the second drive period. Is applied to the data line DLj.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured as the first drive current in the first pause period, and the second drive current output from the pixel circuit 20 to be measured in the second pause period. Measured as drive current.
  • the correction circuit corrects a part related to the pixel circuit 20 to be measured in the video signal D1 based on the first and second drive currents. In this manner, writing of the measurement voltage and measurement of the drive current are performed twice for the pixel circuit to be measured within the four frame period, and the video signal is corrected based on the two measurement results, thereby correcting the drive transistor. It is possible to compensate for variations in two types of characteristics (threshold voltage and mobility), and to effectively suppress luminance unevenness in the display screen.
  • the driving circuit applies a selection voltage to one scanning line SLi corresponding to the pixel circuit 20 to be measured in one pause period. Accordingly, it is possible to compensate for variations in the characteristics of the driving transistors for a plurality of pixel circuits connected to one scanning line in one pause period.
  • the display device 10 also includes a storage unit (correction data storage unit 19) that stores first and second correction data (threshold voltage correction data and mobility correction data) used for correcting the video signal for each pixel circuit 20.
  • the correction circuit updates the first correction data related to the pixel circuit 20 to be measured based on the first drive current, updates the second correction data related to the pixel circuit 20 to be measured based on the second drive current, and 2.
  • the portion of the video signal D1 related to the pixel circuit 20 to be measured is corrected.
  • two correction data are stored for each pixel circuit, two correction data are updated based on the two measurement results, and the video signal is corrected based on the two correction data. It is possible to compensate for variations in two types of characteristics and effectively suppress luminance unevenness in the display screen.
  • the drive circuit includes a first scan line drive circuit 13 that drives the scan lines SL1 to SLm in the drive period, and a second scan line drive circuit 14 that drives the scan lines SL1 to SLm in the idle period.
  • the drive circuit and the measurement circuit share a drive / measurement circuit (an operational amplifier 32, a capacitor 33, and a switch 34) provided corresponding to the data line DLj.
  • a drive / measurement circuit an operational amplifier 32, a capacitor 33, and a switch 34
  • the display device according to the second embodiment of the present invention has the same configuration as the display device 10 according to the first embodiment (see FIG. 1).
  • the display device according to the first embodiment measures the first drive current in the first idle period F2, and measures the second drive current in the second idle period F4.
  • the display device according to the present embodiment measures the first drive current and the second drive current within one idle period.
  • the display device writes the display data voltage to all the pixel circuits 20 during the driving period. More specifically, in the driving period, the second scanning line driving circuit 14 stops operating.
  • the first scanning line driving circuit 13 sequentially selects the scanning lines SL1 to SLm one line period at a time and applies a selection voltage to the selected scanning line (see FIG. 4).
  • the data line drive / current measurement circuit 15 applies n data voltages based on the corrected video signal D2 to the data lines DL1 to DLn, respectively.
  • FIG. 14 is a timing chart of the suspension period of the display device according to the present embodiment.
  • the driving circuit of the display device according to the present embodiment sequentially includes a first writing period T1, a first measuring period T2, a second writing period T3, and a second measuring period T4 within one idle period. And a third writing period T5 is set.
  • the second scanning line driving circuit 14 applies a selection voltage to the scanning line SLi in the periods T1 to T5. Note that in the pixel circuit 20 in the i-th row, the current Ioled flowing through the organic EL element 25 becomes zero during the periods T1 to T5.
  • the input / output control signal DWT is at a high level, and the data line drive / current measurement circuit 15 functions as a data line drive circuit.
  • the input / output control signal DWT is at a low level, and the data line drive / current measurement circuit 15 functions as a current measurement circuit.
  • the data line drive / current measurement circuit 15 applies the first measurement voltage Vm (i, j, P1) to the data line DLj.
  • the first measurement voltage Vm (i, j, P1) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 measures the first drive current Im (i, j, P1) output from the pixel circuit PX (i, j) to the data line DLj.
  • the CPU 46 updates the threshold voltage correction data Vt (i, j) stored in the threshold voltage correction data storage unit 47 based on the first drive current value Im (i, j, P1) at this time.
  • the data line drive / current measurement circuit 15 applies the second measurement voltage Vm (i, j, P2) to the data line DLj.
  • the second measurement voltage Vm (i, j, P2) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 measures the second drive current Im (i, j, P2) output from the pixel circuit PX (i, j) to the data line DLj.
  • the CPU 46 updates the mobility correction data B (i, j) stored in the mobility correction data storage unit 48 based on the second drive current value Im (i, j, P2) at this time.
  • the data line drive / current measurement circuit 15 applies the data voltage Vm (i, j, P) to the data line DLj.
  • the data voltage Vm (i, j, P) is written into the pixel circuit PX (i, j).
  • the data voltage Vm (i, j, P) in the third writing period T5 is corrected based on the first drive current value Im (i, j, P1) and the second drive current value Im (i, j, P2). This is a voltage based on a corrected video signal D2 obtained by updating two types of correction data stored in the data storage unit 19 and referring to the updated correction data.
  • the display device classifies the frame period into a drive period and an idle period, and measures the drive current in the idle period. Therefore, according to the display device according to the present embodiment, as in the first embodiment, the configuration of the scanning line driving circuit is simplified, the luminance unevenness in the display screen is effectively suppressed, and the power consumption at the peak time Can be reduced.
  • the driving circuit applies a voltage corresponding to the corrected video signal D2 to the data lines DL1 to DLn in the selection period of each scanning line in the driving period, and in the idle period.
  • a writing period and a measurement period are set, and the first or second measurement voltage is applied to the data lines DL1 to DLn in the writing period.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured in the measurement period. In this way, by writing the measurement voltage to the pixel circuit to be measured in the writing period within the pause period, the drive current output from the pixel circuit to which the measurement voltage is written can be measured in the subsequent measurement period. .
  • the driving circuit sets a first writing period, a first measurement period, a second writing period, and a second rest period in order within the pause period, and the first measurement voltage is set to the data line DLj in the first write period.
  • the second measurement voltage is applied to the data line DLj in the second writing period.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured as the first drive current in the first measurement period, and the second drive current output from the pixel circuit 20 to be measured in the second measurement period. Measured as drive current.
  • the correction circuit corrects a part related to the pixel circuit 20 to be measured in the video signal D1 based on the first and second drive currents.
  • the measurement voltage is written to the pixel circuit to be measured and the drive current is measured twice in one frame period, and the video signal is corrected based on the two measurement results. It is possible to compensate for variations in two types of characteristics (threshold voltage and mobility), and to effectively suppress luminance unevenness in the display screen.
  • the driving circuit sets a third writing period after the second measurement period within the pause period, and applies a voltage corresponding to the corrected video signal D2 to the data lines DL1 to DLn in the third writing period.
  • the voltage corresponding to the video signal corrected based on the measurement results in the first and second measurement periods is written in the pixel circuit to be measured in the third writing period, thereby compensating the variation in the characteristics of the driving transistor. Can be immediately reflected in the display image.
  • the display device according to the third embodiment of the present invention has the same configuration as the display device 10 according to the first embodiment (see FIG. 1).
  • the display device according to the first embodiment alternately switches between the driving period and the rest period.
  • the display device according to the present embodiment treats a plurality of continuous pause periods as continuous pause periods, and alternately switches between a drive period and a continuous pause period.
  • FIG. 15 is a diagram illustrating an operation in a driving period and a continuous rest period of the display device according to the embodiment.
  • the drive circuit of the display device according to the present embodiment includes a plurality of frame periods in order of a first drive period F1, a first continuous pause period FS2, a second drive period F3, and a second continuous pause period FS4.
  • the first and second continuous pause periods FS2 and FS4 are each composed of N pause periods (N is an integer of 2 or more).
  • the display device according to the present embodiment performs the same operation on all the pixel circuits 20 in the periods F1, FS2, F3, FS4, and F5.
  • the display device In the first driving period F1, the display device according to the present embodiment writes a display data voltage in the pixel circuit PX (i, j). In the first continuous rest period FS2, the display device according to the present embodiment writes the first measurement voltage Vm (i, j, P1) to the pixel circuit PX (i, j), and the pixel circuit PX (i, j). The first drive current Im (i, j, P1) output from is measured. In the second drive period F3, the display device according to the present embodiment writes a display data voltage in the pixel circuit PX (i, j).
  • the display device In the second continuous rest period FS4, the display device according to the present embodiment writes the second measurement voltage Vm (i, j, P2) to the pixel circuit PX (i, j), and the pixel circuit PX (i, j). The second drive current Im (i, j, P2) output from is measured.
  • the display device In the third drive period F5, the display device according to the present embodiment writes a display data voltage in the pixel circuit PX (i, j).
  • the display device writes the display data voltage to all the pixel circuits 20 during the driving period, as in the second embodiment.
  • FIG. 16 is a timing chart of the continuous pause period of the display device according to the present embodiment.
  • the drive circuit of the display device according to the present embodiment sets m selection periods within one continuous pause period, and sets a writing period Tw and a measurement period Tm within each selection period. To do.
  • the second scanning line driving circuit 14 applies a selection voltage to the scanning line SLi in the i-th selection period within the continuous pause period.
  • the input / output control signal DWT becomes high level, and the data line drive / current
  • the measurement circuit 15 functions as a data line driving circuit.
  • the input / output control signal DWT is at a low level, and the data line drive / current measurement circuit 15 functions as a current measurement circuit.
  • the data line driving / current measuring circuit 15 applies the display data voltage Vm (i, j, P) to the data line DLj.
  • the data voltage Vm (i, j, P) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 applies the first measurement voltage Vm (i, j, P1) to the data line DLj. To do.
  • the first measurement voltage Vm (i, j, P1) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 measures the first drive current Im (i, j, P1) output from the pixel circuit PX (i, j) to the data line DLj.
  • the CPU 46 updates the threshold voltage correction data Vt (i, j) stored in the threshold voltage correction data storage unit 47 based on the first drive current value Im (i, j, P1) at this time.
  • the data line driving / current measuring circuit 15 applies the display data voltage Vm (i, j, P) to the data line DLj.
  • the data voltage Vm (i, j, P) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 applies the second measurement voltage Vm (i, j, P2) to the data line DLj. To do.
  • the second measurement voltage Vm (i, j, P2) is written into the pixel circuit PX (i, j).
  • the data line drive / current measurement circuit 15 measures the second drive current Im (i, j, P2) output from the pixel circuit PX (i, j) to the data line DLj.
  • the CPU 46 updates the mobility correction data B (i, j) stored in the mobility correction data storage unit 48 based on the second drive current value Im (i, j, P2) at this time.
  • the data line drive / current measurement circuit 15 applies the display data voltage Vm (i, j, P) to the data line DLj.
  • the data voltage Vm (i, j, P) is written into the pixel circuit PX (i, j).
  • the data voltage Vm (i, j, P) in the third driving period F5 is corrected based on the first driving current value Im (i, j, P1) and the second driving current value Im (i, j, P2). This is a voltage based on a corrected video signal D2 obtained by updating two types of correction data stored in the data storage unit 19 and referring to the updated correction data.
  • the display device classifies the frame period into a drive period and an idle period, and measures the drive current in the idle period. Therefore, according to the display device according to the present embodiment, similarly to the first and second embodiments, the configuration of the scanning line driving circuit is simplified, the luminance unevenness in the display screen is effectively suppressed, and the peak time is reached. Power consumption can be reduced.
  • the driving circuit applies a voltage corresponding to the corrected video signal D2 to the data lines DL1 to DLn in the selection period of each scanning line in the driving period, and in the continuous pause period.
  • a selection voltage is sequentially applied to the scanning lines SL1 to SLm, a writing period and a measurement period are set within the selection period of each scanning line, and the first or second measurement voltage is applied to the data line DLj in each writing period.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured in each measurement period. In this manner, by writing the measurement voltage to the pixel circuit to be measured in each writing period within the continuous pause period, the drive current output from the pixel circuit having written the measurement voltage is measured in the subsequent measurement period. Can do.
  • the driving circuit applies a selection voltage to all the scanning lines SL1 to SLm in order during one continuous pause period. Accordingly, it is possible to compensate for variations in the characteristics of the drive transistors for all the pixel circuits in one continuous pause period.
  • the driving circuit applies the first measurement voltage to the data line DLj in each writing period within the first continuous pause period, and applies the second measurement voltage to the data line DLj in each write period within the second continuous pause period. Apply to.
  • the measurement circuit measures the drive current output from the pixel circuit 20 to be measured as the first drive current in each measurement period within the first continuous pause period, and the measurement target in each measurement period within the second continuous pause period.
  • the drive current output from the pixel circuit 20 is measured as the second drive current.
  • the correction circuit corrects a part related to the circuit to be measured in the video signal D1 based on the first and second drive currents.
  • the measurement voltage is written and the drive current is measured twice for all the pixel circuits within two continuous pause periods, and the video signal is corrected based on the two measurement results, thereby driving the pixel circuit. It is possible to compensate for variations in the two types of characteristics (threshold voltage and mobility) of the transistor and to effectively suppress luminance unevenness in the display screen.
  • the pixel circuit 20 shown in FIG. 2 includes N-channel TFTs 21 to 23, the pixel circuit 20 may include P-channel TFTs.
  • the polarity of the voltage applied to the pixel circuit 20 and the polarity of the voltage in the pixel circuit 20 are reversed.
  • 2 includes the capacitor 33 between the inverting input terminal and the output terminal of the operational amplifier 32 in parallel with the switch 34
  • the data line drive / current measurement circuit 15 includes:
  • a resistor 35 may be included instead of the capacitor 33 (see FIG. 17).
  • the switch 34 is off, the operational amplifier 32 and the resistor 35 function as an integration circuit.
  • either a capacitive element or a resistive element may be provided as a passive element between the inverting input terminal and the output terminal of the operational amplifier.
  • the driving circuit may sequentially apply the selection voltage to a plurality of scanning lines corresponding to the pixel circuit to be measured in one pause period. Accordingly, it is possible to compensate for variations in the characteristics of the driving transistors for a plurality of pixel circuits connected to a plurality of scanning lines in one pause period.
  • the driving circuit may sequentially apply the selection voltage to a part of the scanning lines SL1 to SLm in one continuous pause period.
  • the classification of the frame periods shown in FIGS. 3 and 15 is an example of a classification method
  • the setting of the writing period and the measurement period within the pause period shown in FIG. 14 is an example of a setting method.
  • the drive circuit of the display device according to the first embodiment may classify the frame period into a drive period and a pause period in a manner other than that shown in FIG.
  • the drive circuit of the display device according to the second embodiment may set the writing period and the measurement period within the pause period in a mode other than that shown in FIG.
  • the drive circuit of the display device according to the third embodiment may classify the frame period into a drive period and a continuous pause period in a manner other than that shown in FIG.
  • the display device and the driving method thereof according to the present invention have a scan line driving circuit with a simple configuration, can effectively suppress luminance unevenness, and have low power consumption, such as an organic EL element.
  • the present invention can be used for a display device including a current-driven light emitting element.

Abstract

L'invention concerne un circuit d'attaque qui divise une période de trame en une période d'attaque et en une période de repos. Le circuit d'attaque applique une tension de sélection à une pluralité de lignes de balayage de manière séquentielle tout en appliquant une tension conformément à un signal vidéo (tension de mesure pour un objet à mesurer) à une pluralité de lignes de données de manière séquentielle durant la période d'attaque. Le circuit d'attaque applique la tension de sélection à une ligne de balayage unique correspondant à un circuit de pixel à mesurer, tandis qu'un circuit de mesure mesure un courant d'attaque délivré à la pluralité de lignes de données à partir du circuit de pixel à mesurer durant la période de repos. Le circuit d'attaque peut établir une période d'écriture et une période de mesure durant la période de repos et peut appliquer la tension de mesure à la pluralité de lignes de données durant la période d'écriture. Le circuit de mesure peut mesurer le courant d'attaque délivré à la pluralité de lignes de données à partir du circuit de pixel à mesurer durant la période de mesure. Ainsi, il est possible de fournir un dispositif d'affichage à faible consommation d'énergie qui a un circuit d'attaque de ligne de balayage à configuration simple et est apte à supprimer de manière efficace la variation de luminance.
PCT/JP2014/069285 2013-09-10 2014-07-22 Dispositif d'affichage et son procédé de commande WO2015037331A1 (fr)

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WO2015199051A1 (fr) * 2014-06-23 2015-12-30 シャープ株式会社 Dispositif d'affichage et son procédé d'attaque
JPWO2015199051A1 (ja) * 2014-06-23 2017-04-20 シャープ株式会社 表示装置およびその駆動方法
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WO2016158481A1 (fr) * 2015-03-27 2016-10-06 シャープ株式会社 Dispositif d'affichage et procédé de fonctionnement de ce dernier
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CN108231016A (zh) * 2017-12-21 2018-06-29 南京中电熊猫平板显示科技有限公司 一种显示面板像素亮度补偿控制方法及装置
CN108648671A (zh) * 2018-04-28 2018-10-12 武汉华星光电半导体显示技术有限公司 检测信号选择电路及选择方法、阵列基板、显示面板
CN108648671B (zh) * 2018-04-28 2020-03-31 武汉华星光电半导体显示技术有限公司 检测信号选择电路及选择方法、阵列基板、显示面板
WO2019205304A1 (fr) * 2018-04-28 2019-10-31 武汉华星光电半导体显示技术有限公司 Circuit de sélection de signal de détection, substrat de réseau et panneau d'affichage
WO2020066024A1 (fr) * 2018-09-28 2020-04-02 シャープ株式会社 Dispositif d'affichage et son procédé d'attaque
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CN111862893B (zh) * 2019-04-29 2022-02-22 奇景光电股份有限公司 源极驱动器

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