WO2015034118A1 - Procédé de pelage de surface de substrat de silicium - Google Patents

Procédé de pelage de surface de substrat de silicium Download PDF

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Publication number
WO2015034118A1
WO2015034118A1 PCT/KR2013/008116 KR2013008116W WO2015034118A1 WO 2015034118 A1 WO2015034118 A1 WO 2015034118A1 KR 2013008116 W KR2013008116 W KR 2013008116W WO 2015034118 A1 WO2015034118 A1 WO 2015034118A1
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WO
WIPO (PCT)
Prior art keywords
silicon substrate
electrolytic deposition
crystalline silicon
layer
stress
Prior art date
Application number
PCT/KR2013/008116
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English (en)
Korean (ko)
Inventor
유봉영
이정훈
권영임
윤상화
엄한돈
Original Assignee
Yoo Bong Young
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yoo Bong Young filed Critical Yoo Bong Young
Priority to PCT/KR2013/008116 priority Critical patent/WO2015034118A1/fr
Publication of WO2015034118A1 publication Critical patent/WO2015034118A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers

Definitions

  • the present invention relates to a method of peeling a surface of a silicon substrate, and more particularly, to a method of manufacturing a crystalline silicon thin film by peeling a surface of a crystalline silicon substrate at room temperature.
  • Monocrystalline silicon semiconductor materials are used in the form of wafers in which single crystal ingots are manufactured and thinly cut, but due to the thickness limitations due to the cutting, material costs are inevitably higher than in the case of forming an amorphous thin film.
  • a method of peeling a silicon substrate is a technique known as SmartCut technology, which is a method of peeling off by performing ion implantation on the surface of a silicon substrate.
  • SmartCut technology is a method of peeling off by performing ion implantation on the surface of a silicon substrate.
  • the present invention aims to solve the problems of the prior art described above, and provides a method for peeling crystalline silicon substrates which can be carried out at low cost while maintaining the quality of the silicon thin film.
  • the method of surface peeling a crystalline silicon substrate according to the present invention for achieving the above object comprises the steps of preparing a crystalline silicon substrate; constructing a plating bath for electrodeposition; Forming a stress layer on the crystalline silicon substrate by an electrolytic deposition process; and peeling a surface of the crystalline silicon substrate by the electrolytic deposition force remaining in the stress layer.
  • Electrodeposition involves placing electrode plates in a solution and reducing the direct voltage.
  • electroplating of a metal coating on the material in the negative electrode is one of the electrolytic deposition.
  • the electrolytic deposition layer formed by the electrolytic deposition has an electrolytic deposition stress formed therein, and in order to improve the quality of the electrolytic deposition layer, it is common to solve the electrolytic deposition force by a method such as heat treatment.
  • the inventors have developed a method of peeling the surface of the crystalline silicon substrate at low temperature using these electrolytic deposition forces.
  • the method further includes forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the silicon substrate and the stress layer.
  • the electrolytic deposition stress remaining in the stress layer can be controlled by adding an additive to the bath or adjusting the current density of the electrolytic deposition process.
  • the remaining electrolytic deposition strength varies depending on the type of, but by adding impurity to the deposition layer, the remaining electrolytic deposition stress can be further changed, and the impurity can be added to the deposition layer by adding an additive to the plating bath.
  • Additives added to the plating bath to control the amount varies depending on the material of the deposition layer, which is obvious to those of ordinary skill in the art to which the present invention belongs, and a detailed description thereof will be omitted.
  • the material applicable to the stress layer is a metal such as Ni, Co, Fe or the like. These alloys can be used, and their oxides and alloys are also possible.
  • the Ni metal thin film can be electrolytically deposited into the stress layer, and in the process, P can be added as an additive to the stress layer to control the electrolytic deposition force. It is preferable to use a plating bath composed of ⁇ 0 2 and H 3 B0 3 and H 3 P0 3 for electrolytic deposition of P-doped Ni thin films.
  • a method of surface peeling a crystalline silicon substrate includes the steps of preparing a crystalline silicon substrate; forming a buffer layer on the crystalline silicon substrate; constructing a plating bath for electrolytic deposition; Forming a stress layer on the surface of the buffer layer using an electrolytic deposition process; and peeling the surface of the crystalline silicon substrate by the electrolytic deposition stress remaining in the stress layer, and remaining in the buffer layer. It is characterized by the fact that the resistivity is smaller than the electrolytic deposition stress remaining in the stress layer.
  • the inventors of the present invention are the result of excessive electrolytic deposition stress of the stress layer.
  • the present invention can control the thickness of the crystalline silicon stripped by controlling the thickness of the buffer layer to control the depth of the electrolytic deposition force remaining on the stress layer on the crystalline silicon substrate.
  • the electrolytic deposition force remaining in the stress layer can be controlled by adding an additive to the bath or adjusting the current density of the electrolytic deposition process.
  • the remaining electrolytic deposition strength varies depending on the type, but by adding the pure impurities to the deposition layer, the remaining electrolytic deposition forces can be further changed, and impurities can be added to the deposition layer by adding an additive to the plating bath.
  • Additives added to the plating bath to control the amount varies depending on the material of the deposition layer, which is obvious to those of ordinary skill in the art to which the present invention belongs, and a detailed description thereof will be omitted.
  • the material applicable to the stress layer may be a metal such as Ni, Co, Fe, or an alloy thereof, and also an oxide thereof and an alloy thereof.
  • the electrolytic deposition of Ni metal thin film all-stress layer may be performed.
  • electrolytic deposition stress can be controlled by adding P as an additive to the stress layer. It is preferable to use a plating bath composed of NiCl 2 and B0 3 and H 3 P0 3 for electrolytic deposition of P-added Ni thin films.
  • the step of forming the buffer layer may be performed by an electrolytic deposition process.
  • the electrolytic deposition forces remaining in the buffer layer must be less than the electrolytic deposition forces remaining in the stress layer.
  • the method further includes forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the crystalline silicon substrate and the buffer layer.
  • the present invention configured as described above has the effect of producing a crystalline silicon thin film at low cost by peeling the crystalline silicon substrate by using electrolytic deposition which can be applied to a large area at low cost.
  • the electrolytic deposition process applied in the present invention is carried out at low temperatures, there is an effect that can prevent the disadvantages of silicon quality deterioration at high temperatures.
  • the present invention can control the remaining electrolytic deposition stress by adjusting the electrolytic deposition conditions such as plating bath composition and current density, and especially when the buffer layer is introduced, the electrolytic deposition stress on the crystalline silicon substrate is controlled by controlling the thickness of the buffer layer.
  • the depth can be adjusted so that the crystalline silicon thin film can be manufactured by peeling the crystalline silicon substrate under various conditions.
  • 1 is a graph showing the change of the electrolytic deposition stress according to the concentration of H 3 P0 3 .
  • FIG. 2 is a graph showing changes in electrolytic deposition force according to current density.
  • FIG. 3 is a schematic diagram showing a surface peeling method of a silicon substrate according to an embodiment of the present invention.
  • FIG. 4 is a photograph showing the results of peeling by electrolytic deposition according to an embodiment of the present invention for a 4 inch circular silicon wafer.
  • FIG. 5 is a photograph showing the results of peeling by electrolytic deposition according to an embodiment of the present invention for a 3.5 cm x 3.5 n silicon substrate.
  • FIG. 6 is a photograph showing the results of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate on which a gold seed layer was formed.
  • FIG. 7 is a schematic diagram showing a surface peeling method of a crystalline silicon substrate including a buffer layer according to another embodiment of the present invention.
  • FIG. 8 illustrates an embodiment including a buffer layer for a 3.5 cm x 3.5 cm silicon substrate.
  • the photo shows the results of peeling off the silicon substrate.
  • FIG. 9 is a photograph showing the dissolution of Ni and Ni-P in the silicon thin film peeled from FIG. 8.
  • This section describes in detail how to peel the surface of the crystalline silicon substrate.
  • Electrodeposition involves placing electrode plates in solution and reducing the direct voltage.
  • the material deposited by electrolysis is attached to the surface of the electrode, and electroplating for coating metal on the material located on the cathode is one of electrolytic deposition.
  • the electrolytic deposition layer formed by the electrolytic deposition has an electrolytic deposition stress therein, and in order to improve the quality of the electrolytic deposition layer, it is common to solve the electrolytic deposition force by heat treatment or the like. Since the surface of the crystalline silicon substrate is peeled using the electrolytic deposition force, the change of the electrolytic deposition force according to the electrolytic deposition conditions is confirmed.
  • FIG. 1 is a graph showing the change in electrolytic deposition force according to the concentration of H 3 P0 3 .
  • Electrolytic deposition on an area of 7.74ctn 2 was carried out using a sphere strip as an electrode to measure the residual stress of the electrolyte deposition layer.
  • FIG. 2 is a graph showing a change in electrolytic deposition force according to current density.
  • the electrolytic deposition force increases to a current density of 20 mA / cm 2 and then decreases.
  • the electrolytic deposition stress remaining in the electrolytically deposited Ni-P thin film can be controlled by controlling the amount of P added and the current density in the process of electrolytic deposition of Ni. By controlling the density, the electrolytic deposition force remaining in the electrolytic deposition layer can be controlled, which can be used to peel off the surface of the crystalline silicon substrate.
  • FIG 3 illustrates a method of surface peeling a crystalline silicon substrate according to an embodiment of the present invention.
  • Deposition on the surface of the substrate 100 Specifically, Ti having excellent adhesion with silicon is deposited on the surface of the silicon wafer using a PVD method to a thickness of 10 nm, and adhesion with a Ni-P stress layer on the Ti layer. Excellent M or Au was deposited to a thickness of 50 nm.
  • a stress is applied to the surface of the crystalline silicon substrate on the seed layer 200.
  • Electrolytic deposition of Ni-P thin film as the stress layer 300 Specifically, using a Watts bath or Watts nickel bath, which is the most commonly used for nickel plating, 30 at a current density of 50 mA / cm 2 . Striking for 21 minutes using a plating bath in which 0.6M NiCl 2 and 0.5M 3 ⁇ 4B0 3 are added to 0.01M H 3 P0 3 , using a current density of 20 mA / cm 2 as an optimal condition It was.
  • the surface of the silicon substrate 100 is peeled off by the electrolytic deposition force remaining on the deposited stress layer 300 to form the crystalline silicon thin film 120.
  • FIG. 4 is a photograph showing the results of electrolytic deposition according to an embodiment of the present invention for a 4 inch circular silicon wafer. As shown in the photograph, excessive electrolysis of the Ni-P electrolytic deposition layer is shown. Due to the deposition forces, it can be seen that the surface of the silicon wafer is irregularly peeled off.
  • FIG. 5 is a photograph showing the results of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate in accordance with an embodiment of the present invention. In this case, too, the excessive electrolytic deposition of the Ni-P electrolytic deposition layer is performed. Due to the force, the surface of the silicon can be found to be finely broken.
  • the electrolytic deposition stress can be controlled by adjusting the plating bath and the current density conditions, and the silicon substrate can be peeled off by depositing an electrolytic deposition layer on the silicon substrate with the appropriate electrolytic deposition force. Is considered.
  • a seed layer having a thickness of 100 nm was formed on a 3.5 cm x 3.5 cm silicon substrate with gold (Au), and the surface was peeled off under the same conditions as in the previous example.
  • FIG. 6 is a photograph showing the result of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate on which a gold seed layer was formed.
  • the surface of the silicon is broken finely By simply changing the seed layer, it can be seen that it is difficult to control the force on the silicon substrate due to the electrolytic deposition stress remaining in the stress layer.
  • FIG. 7 is a schematic diagram showing a surface peeling method of a crystalline silicon substrate including a buffer layer according to another embodiment of the present invention.
  • the seed layer 200 for increasing the adhesion between the Ni-P electrolytic deposition layer and the silicon has a silicon thickness of several tens of nanometers.
  • Ni having excellent adhesion to silicon on the surface of the silicon wafer is deposited to a thickness of 10 nm using the PVD method, and Ni having excellent adhesion to the Ni buffer layer on the Ti layer.
  • Au was deposited to a thickness of 50 nm.
  • the Ni thin film is electrolytically deposited on the seed layer 200 with the buffer layer 250. Specifically, electrolytic deposition was carried out for 1 hour 30 minutes at a current density of 20 mA / cm 2 using a watt bath to form a Ni thin film buffer layer 250 having a thickness of about 40;
  • Ni-P thin film is electrolytically deposited as the stress layer 300. Specifically, 20 mA / is applied using a plating bath in which 0.6M NiCl 2 and (.5M H 3 B0 3 are added with 0.01M 3 ⁇ 4:? 0 3 .
  • the stress layer 300 was formed.
  • the electrolytic deposition stress of the stress layer 300 is satisfied to apply stress to the surface of the silicon substrate 100 as a whole. , Prevent destruction of the peeled silicon thin film 120.
  • FIG. 8 is a photograph showing the result of peeling a silicon substrate according to an embodiment including a buffer layer for a 3.5 cm x 3.5 cm silicon substrate. As shown in the photograph, the silicon thin film is peeled off on the left side. From this, it can be seen that without changing the conditions for electrolytic deposition of the stress layer, a small buffer layer of electrolytic deposition force can be formed between the stress layer and the silicon substrate to prevent breakage of the peeled silicon thin film.
  • FIG. 9 is a photograph showing the dissolution of Ni and Ni-P in the silicon thin film peeled from FIG. 8.
  • the silicon thin film to which the Ni thin film buffer layer and the Ni-P stress layer were bonded was placed in hydrochloric acid. After removing Ni-P and Ni-P, the complete silicon thin film was peeled off.
  • the surface of the crystalline silicon substrate was prepared using the electrolytic deposition force.
  • the present invention which peels off, uses an electrolytic deposition process that is inexpensive and capable of mass processing to produce a silicon thin film by peeling the surface of the crystalline silicon substrate.
  • the manufacturing cost can be greatly reduced.
  • the electrolytic deposition process does not need to apply a high temperature, the silicon thin film peeled by the present invention has no problem of quality deterioration that can occur at high temperature.
  • the crystalline silicon thin film peeled by the embodiment of the present invention has a thickness thinner than that which can be cut on a silicon wafer in a general manner, and exhibits excellent characteristics compared to the amorphous silicon thin film, and thus can be applied to various devices.
  • the solar cell is fabricated using the crystalline silicon thin film produced by the present invention.
  • the material cost is greatly reduced compared to the general single crystalline silicon solar cell, and the efficiency is very high compared to the general amorphous silicon solar cell.

Abstract

La présente invention concerne un procédé de pelage d'une surface de substrat de silicium cristallin qui nécessite de faibles coûts de traitement et qui est mis en œuvre à basse température de sorte que la qualité du film mince de silicium puisse être maintenue. Le procédé comprend les étapes consistant à : préparer un substrat de silicium cristallin ; préparer un bain de placage pour un dépôt électrolytique ; former une couche de contrainte sur le substrat en silicium cristallin par dépôt électrolytique à l'aide du bain de placage ; et peler la surface du substrat de silicium cristallin par contrainte de dépôt électrolytique demeurant sur la couche de contrainte. Le procédé de pelage d'une surface de substrat de silicium cristallin selon un autre mode de réalisation de la présente invention comprend les étapes consistant à : préparer un substrat de silicium cristallin ; former une couche tampon sur le substrat de silicium cristallin ; préparer un bain de placage pour un dépôt électrolytique ; former une couche de contrainte sur la surface de la couche tampon par dépôt électrolytique à l'aide du bain de placage ; et peler la surface du substrat de silicium cristallin par contrainte de dépôt électrolytique demeurant sur la couche de contrainte, la contrainte demeurant sur la couche tampon étant inférieure à la contrainte demeurant sur la couche de contrainte. La présente invention peut permettre la fabrication d'un film mince de silicium cristallin à faible coût par pelage du substrat de silicium cristallin par dépôt électrolytique, et peut éviter l'inconvénient consistant en la dégradation de la qualité du film de silicium cristallin à une température élevée.
PCT/KR2013/008116 2013-09-09 2013-09-09 Procédé de pelage de surface de substrat de silicium WO2015034118A1 (fr)

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PCT/KR2013/008116 WO2015034118A1 (fr) 2013-09-09 2013-09-09 Procédé de pelage de surface de substrat de silicium

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PCT/KR2013/008116 WO2015034118A1 (fr) 2013-09-09 2013-09-09 Procédé de pelage de surface de substrat de silicium

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040255846A1 (en) * 2003-06-06 2004-12-23 Bruce Faure Method for fabricating a carrier substrate
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
JP2007279248A (ja) * 2006-04-04 2007-10-25 Seiko Epson Corp 撥液膜の形成方法
JP2011222898A (ja) * 2010-04-14 2011-11-04 Fuji Electric Co Ltd 半導体装置の製造方法
KR20120055997A (ko) * 2010-11-24 2012-06-01 포항공과대학교 산학협력단 레이저를 이용한 플렉서블 전자소자의 제조방법, 플렉서블 전자소자 및 플렉서블 기판

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
US20040255846A1 (en) * 2003-06-06 2004-12-23 Bruce Faure Method for fabricating a carrier substrate
JP2007279248A (ja) * 2006-04-04 2007-10-25 Seiko Epson Corp 撥液膜の形成方法
JP2011222898A (ja) * 2010-04-14 2011-11-04 Fuji Electric Co Ltd 半導体装置の製造方法
KR20120055997A (ko) * 2010-11-24 2012-06-01 포항공과대학교 산학협력단 레이저를 이용한 플렉서블 전자소자의 제조방법, 플렉서블 전자소자 및 플렉서블 기판

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