WO2015034118A1

WO2015034118A1 - Method of peeling silicon substrate surface

Info

Publication number: WO2015034118A1
Application number: PCT/KR2013/008116
Authority: WO
Inventors: 유봉영; 이정훈; 권영임; 윤상화; 엄한돈
Original assignee: Yoo Bong Young
Priority date: 2013-09-09
Filing date: 2013-09-09
Publication date: 2015-03-12

Abstract

The present invention relates to a method of peeling a crystalline silicon substrate surface that requires low processing costs and is performed at a low temperature so that the quality of a silicon thin film may be maintained. The method comprises the steps of: preparing a crystalline silicon substrate; preparing a plating bath for electrodeposition; forming a stress layer on the crystalline silicon substrate by electrodeposition using the plating bath; and peeling off the surface of the crystalline silicon substrate by electrodeposition stress remaining on the stress layer. The method of peeling off a crystalline silicon substrate surface according to another embodiment of the present invention comprises the steps of: preparing a crystalline silicon substrate; forming a buffer layer on the crystalline silicon substrate; preparing a plating bath for electrodeposition; forming a stress layer on the surface of the buffer layer by electrodeposition using the plating bath; and peeling off the surface of the crystalline silicon substrate by electrodeposition stress remaining on the stress layer, wherein the stress remaining on the buffer layer is smaller than the stress remaining on the stress layer. The present invention may enable a crystalline silicon thin film to be manufactured at low cost by peeling off the crystalline silicon substrate by electrodeposition, and may prevent the drawback of the quality of the thin crystalline silicon film degrading at a high temperature.

Description

Specification

Name of the Invention: Surface Peeling Method of Silicon Substrate

[1] The present invention relates to a method of peeling a surface of a silicon substrate, and more particularly, to a method of manufacturing a crystalline silicon thin film by peeling a surface of a crystalline silicon substrate at room temperature.

Background

[2] Semiconductor materials, typically represented by silicon, are essential for electronics

In recent years, its use continues to increase because it plays an important role in solar power generation.

[3] Semiconductor devices to which these semiconductor materials are applied have excellent performance.

It started with the use of a single-crystal material, but the cost of semiconductor materials, especially silicon, is getting more than the cost of the material.

[4] Representatively, in the photovoltaic generation, crystalline silicon solar cells made of single crystal crystalline silicon material have been continuously developed and used from the beginning based on the excellent performance, but the material cost of single crystal silicon substrate is increasing. Due to this, researches on amorphous thin-film silicon solar cells or poly-crystal-type silicon solar cells in which an amorphous thin film is crystallized are being actively conducted.

[5] Monocrystalline silicon semiconductor materials are used in the form of wafers in which single crystal ingots are manufactured and thinly cut, but due to the thickness limitations due to the cutting, material costs are inevitably higher than in the case of forming an amorphous thin film.

[6] Therefore, efforts have been made to lower the material cost by thinly peeling and using crystalline silicon materials.

[7] A method of peeling a silicon substrate is a technique known as SmartCut technology, which is a method of peeling off by performing ion implantation on the surface of a silicon substrate. As a result, the process cost is high, and the process is performed at a high temperature, and thus, the brittleness of the silicon is weakened, so that the stress of peeling is high, and the impurities in the silicon are more likely to be diffused.

[8] SlimCut technology has been developed as a technique for peeling silicon substrates at a lower cost than SmartCut method (US Patent Publication No. 2010/0310775), which has a coefficient of thermal expansion on the surface of a silicon substrate. It is a method of peeling a silicon substrate by depositing a metal having a large difference, heating it to a high temperature, cooling it, and then applying a stress on the silicon substrate by a difference of the coefficient of thermal expansion. Lower than Although it is possible to peel off using stress, the problem of deterioration of the quality of the silicon thin film was not solved due to the high possibility of impurity diffusion in the silicon during the step of raising the high temperature before the angle.

Detailed description of the invention

Technical task

[9] The present invention aims to solve the problems of the prior art described above, and provides a method for peeling crystalline silicon substrates which can be carried out at low cost while maintaining the quality of the silicon thin film.

Task solution

[10] The method of surface peeling a crystalline silicon substrate according to the present invention for achieving the above object comprises the steps of preparing a crystalline silicon substrate; constructing a plating bath for electrodeposition; Forming a stress layer on the crystalline silicon substrate by an electrolytic deposition process; and peeling a surface of the crystalline silicon substrate by the electrolytic deposition force remaining in the stress layer.

[11] Electrodeposition involves placing electrode plates in a solution and reducing the direct voltage.

By the ^will, for attaching the precipitated material on the surface of the electrode by electrolysis, electroplating of a metal coating on the material in the negative electrode is one of the electrolytic deposition.

[12] The electrolytic deposition layer formed by the electrolytic deposition has an electrolytic deposition stress formed therein, and in order to improve the quality of the electrolytic deposition layer, it is common to solve the electrolytic deposition force by a method such as heat treatment. The inventors have developed a method of peeling the surface of the crystalline silicon substrate at low temperature using these electrolytic deposition forces.

[13] At this time, before forming a stress layer on the crystalline silicon substrate,

Preferably, the method further includes forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the silicon substrate and the stress layer.

[14] In the step of forming a plating bath for electrolytic deposition, the electrolytic deposition stress remaining in the stress layer can be controlled by adding an additive to the bath or adjusting the current density of the electrolytic deposition process. The remaining electrolytic deposition strength varies depending on the type of, but by adding impurity to the deposition layer, the remaining electrolytic deposition stress can be further changed, and the impurity can be added to the deposition layer by adding an additive to the plating bath. Additives added to the plating bath to control the amount varies depending on the material of the deposition layer, which is obvious to those of ordinary skill in the art to which the present invention belongs, and a detailed description thereof will be omitted.

[15] In the present invention, the material applicable to the stress layer is a metal such as Ni, Co, Fe or the like. These alloys can be used, and their oxides and alloys are also possible. In particular, the Ni metal thin film can be electrolytically deposited into the stress layer, and in the process, P can be added as an additive to the stress layer to control the electrolytic deposition force. It is preferable to use a plating bath composed of ^ 0 ₂ and H ₃ B0 ₃ and H ₃ P0 ₃ for electrolytic deposition of P-doped Ni thin films.

[16] A method of surface peeling a crystalline silicon substrate according to another aspect of the present invention includes the steps of preparing a crystalline silicon substrate; forming a buffer layer on the crystalline silicon substrate; constructing a plating bath for electrolytic deposition; Forming a stress layer on the surface of the buffer layer using an electrolytic deposition process; and peeling the surface of the crystalline silicon substrate by the electrolytic deposition stress remaining in the stress layer, and remaining in the buffer layer. It is characterized by the fact that the resistivity is smaller than the electrolytic deposition stress remaining in the stress layer.

[17] The inventors of the present invention are the result of excessive electrolytic deposition stress of the stress layer.

In order to prevent the breakdown of the crystalline silicon thin film and to solve the problem of difficult separation due to the weakening of the electrolytic deposition stress, a method of forming a buffer layer to buffer the excessive electrolytic deposition stress of the stress layer has been disclosed.

In particular, the present invention can control the thickness of the crystalline silicon stripped by controlling the thickness of the buffer layer to control the depth of the electrolytic deposition force remaining on the stress layer on the crystalline silicon substrate.

[19] In the step of forming a plating bath for electrolytic deposition, the electrolytic deposition force remaining in the stress layer can be controlled by adding an additive to the bath or adjusting the current density of the electrolytic deposition process. The remaining electrolytic deposition strength varies depending on the type, but by adding the pure impurities to the deposition layer, the remaining electrolytic deposition forces can be further changed, and impurities can be added to the deposition layer by adding an additive to the plating bath. Additives added to the plating bath to control the amount varies depending on the material of the deposition layer, which is obvious to those of ordinary skill in the art to which the present invention belongs, and a detailed description thereof will be omitted.

[20] In the present invention, the material applicable to the stress layer may be a metal such as Ni, Co, Fe, or an alloy thereof, and also an oxide thereof and an alloy thereof. Particularly, the electrolytic deposition of Ni metal thin film all-stress layer may be performed. In this process, electrolytic deposition stress can be controlled by adding P as an additive to the stress layer. It is preferable to use a plating bath composed of NiCl ₂ and B0 ₃ and H ₃ P0 ₃ for electrolytic deposition of P-added Ni thin films.

[21] On the other hand, the step of forming the buffer layer may be performed by an electrolytic deposition process.

The electrolytic deposition forces remaining in the buffer layer must be less than the electrolytic deposition forces remaining in the stress layer.

[22] and prior to forming the buffer layer by electrolytic deposition on the crystalline silicon substrate, Preferably, the method further includes forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the crystalline silicon substrate and the buffer layer. Effects of the Invention

The present invention configured as described above has the effect of producing a crystalline silicon thin film at low cost by peeling the crystalline silicon substrate by using electrolytic deposition which can be applied to a large area at low cost.

Furthermore, since the electrolytic deposition process applied in the present invention is carried out at low temperatures, there is an effect that can prevent the disadvantages of silicon quality deterioration at high temperatures.

[25] In addition, the present invention can control the remaining electrolytic deposition stress by adjusting the electrolytic deposition conditions such as plating bath composition and current density, and especially when the buffer layer is introduced, the electrolytic deposition stress on the crystalline silicon substrate is controlled by controlling the thickness of the buffer layer. The depth can be adjusted so that the crystalline silicon thin film can be manufactured by peeling the crystalline silicon substrate under various conditions.

Brief description of the drawings

1 is a graph showing the change of the electrolytic deposition stress according to the concentration of H ₃ P0 ₃ .

FIG. 2 is a graph showing changes in electrolytic deposition force according to current density.

3 is a schematic diagram showing a surface peeling method of a silicon substrate according to an embodiment of the present invention.

4 is a photograph showing the results of peeling by electrolytic deposition according to an embodiment of the present invention for a 4 inch circular silicon wafer.

5 is a photograph showing the results of peeling by electrolytic deposition according to an embodiment of the present invention for a 3.5 cm x 3.5 n silicon substrate.

FIG. 6 is a photograph showing the results of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate on which a gold seed layer was formed.

FIG. 7 is a schematic diagram showing a surface peeling method of a crystalline silicon substrate including a buffer layer according to another embodiment of the present invention.

8 illustrates an embodiment including a buffer layer for a 3.5 cm x 3.5 cm silicon substrate.

The photo shows the results of peeling off the silicon substrate.

FIG. 9 is a photograph showing the dissolution of Ni and Ni-P in the silicon thin film peeled from FIG. 8.

Mode for Carrying Out the Invention

[35] First, we will look at how to control the electrolytic deposition force.

This section describes in detail how to peel the surface of the crystalline silicon substrate.

[36] Electrodeposition involves placing electrode plates in solution and reducing the direct voltage.

By attaching, the material deposited by electrolysis is attached to the surface of the electrode, and electroplating for coating metal on the material located on the cathode is one of electrolytic deposition. The electrolytic deposition layer formed by the electrolytic deposition has an electrolytic deposition stress therein, and in order to improve the quality of the electrolytic deposition layer, it is common to solve the electrolytic deposition force by heat treatment or the like. Since the surface of the crystalline silicon substrate is peeled using the electrolytic deposition force, the change of the electrolytic deposition force according to the electrolytic deposition conditions is confirmed.

[38] First, the change of electrolytic deposition force according to the composition of the plating bath was confirmed. At this time, Ni was selected as the material for electrolytic deposition, and the plating bath was prepared with 0.6M NiCl ₂ and 0.5M H ₃ B0 ₃ . P was selected as the material to be added to the electrolytic deposition layer, and H ₃ P0 ₃ was added to the plating bath. To measure the residual strength of the electrolytic deposition layer, a copper strip was used to measure 7.74 cm ² . A current density electrolytic deposition of 9.689 mA / cm ² was deposited on the area.

FIG. 1 is a graph showing the change in electrolytic deposition force according to the concentration of H ₃ P0 ₃ .

[40] As shown, the addition of H ₃ P0 ₃ to the plating bath increases the electrolytic deposition force to the electrolytic deposition layer up to 0.01 M, but then decreases gradually.

[41] Next, the electrolytic deposition force according to the current density in the electrolytic deposition process was investigated.

At this time, a plating bath with 0.01M!> 0 ₃ added to 0.6M NiCl ₂ and 0.5M H ₃ B0 ₃ , which was found to have the highest electrolytic deposition strength, was used. Was 1.49. Electrolytic deposition on an area of 7.74ctn ² was carried out using a sphere strip as an electrode to measure the residual stress of the electrolyte deposition layer.

FIG. 2 is a graph showing a change in electrolytic deposition force according to current density.

As shown, the electrolytic deposition force increases to a current density of 20 mA / cm ² and then decreases.

From the above results, it can be confirmed that the electrolytic deposition stress remaining in the electrolytically deposited Ni-P thin film can be controlled by controlling the amount of P added and the current density in the process of electrolytic deposition of Ni. By controlling the density, the electrolytic deposition force remaining in the electrolytic deposition layer can be controlled, which can be used to peel off the surface of the crystalline silicon substrate.

[45]

[46] The conditions for the highest electrolytic deposition force under the above electrolytic deposition conditions of Ni-P are as follows.

The surface peeling of a 4 inch circular single crystal silicon wafer was attempted.

3 illustrates a method of surface peeling a crystalline silicon substrate according to an embodiment of the present invention.

It is a schematic diagram shown.

[48] In the silicon surface peeling method of the present embodiment, first, the Ni-P electrolytic deposition layer and the silicon

Silicon layer with tens of nanometers thickness for seed layer 200 for improved adhesion

Deposition on the surface of the substrate 100. Specifically, Ti having excellent adhesion with silicon is deposited on the surface of the silicon wafer using a PVD method to a thickness of 10 nm, and adhesion with a Ni-P stress layer on the Ti layer. Excellent M or Au was deposited to a thickness of 50 nm.

[49] Next, a stress is applied to the surface of the crystalline silicon substrate on the seed layer 200. Electrolytic deposition of Ni-P thin film as the stress layer 300. Specifically, using a Watts bath or Watts nickel bath, which is the most commonly used for nickel plating, 30 at a current density of 50 mA / cm ² . Striking for 21 minutes using a plating bath in which 0.6M NiCl ₂ and 0.5M ¾B0 ₃ are added to 0.01M H ₃ P0 ₃ , using a current density of 20 mA / cm ² as an optimal condition It was.

The surface of the silicon substrate 100 is peeled off by the electrolytic deposition force remaining on the deposited stress layer 300 to form the crystalline silicon thin film 120.

FIG. 4 is a photograph showing the results of electrolytic deposition according to an embodiment of the present invention for a 4 inch circular silicon wafer. As shown in the photograph, excessive electrolysis of the Ni-P electrolytic deposition layer is shown. Due to the deposition forces, it can be seen that the surface of the silicon wafer is irregularly peeled off.

[52] the same as described above for a 3.5cm by 3.5cm silicon substrate.

Conditional stripping was attempted.

FIG. 5 is a photograph showing the results of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate in accordance with an embodiment of the present invention. In this case, too, the excessive electrolytic deposition of the Ni-P electrolytic deposition layer is performed. Due to the force, the surface of the silicon can be found to be finely broken.

[54] From the above results, it was confirmed that the surface of the silicon substrate could be peeled off using the electrolytic deposition force. However, due to the excessive electrolytic deposition force, the complete silicon thin film was not obtained. This is because you have chosen the largest case, and you will be able to adjust it to peel off the silicon thin film.

[55]

[56] As described above, the electrolytic deposition stress can be controlled by adjusting the plating bath and the current density conditions, and the silicon substrate can be peeled off by depositing an electrolytic deposition layer on the silicon substrate with the appropriate electrolytic deposition force. Is considered.

[57] However, the adjustment of the electrolytic deposition conditions to find an appropriate electrolytic deposition force has to be determined through a number of experiments, and may be difficult to peel off due to the decrease of electrolytic deposition forces. We have developed different ways to control the stresses.

[58] First, it was checked whether the seed layer could be prevented from being destroyed by changing the seed layer to improve adhesion.

To this end, a seed layer having a thickness of 100 nm was formed on a 3.5 cm x 3.5 cm silicon substrate with gold (Au), and the surface was peeled off under the same conditions as in the previous example.

FIG. 6 is a photograph showing the result of electrolytic deposition on a 3.5 cm x 3.5 cm silicon substrate on which a gold seed layer was formed. In this case, too, due to excessive electrolytic deposition force of the Ni-P electrolytic deposition layer. ， The surface of the silicon is broken finely By simply changing the seed layer, it can be seen that it is difficult to control the force on the silicon substrate due to the electrolytic deposition stress remaining in the stress layer.

[61] Next, the inventors of the present invention found that between the stress layer and the silicon substrate.

How to add a buffer layer to buffer the electrolytic deposition force of the stress layer

Developed.

In the silicon surface peeling method of the present embodiment, first, the seed layer 200 for increasing the adhesion between the Ni-P electrolytic deposition layer and the silicon has a silicon thickness of several tens of nanometers.

Deposition on the surface of the substrate 100. Specifically, Ni having excellent adhesion to silicon on the surface of the silicon wafer is deposited to a thickness of 10 nm using the PVD method, and Ni having excellent adhesion to the Ni buffer layer on the Ti layer. Alternatively, Au was deposited to a thickness of 50 nm.

Next, the Ni thin film is electrolytically deposited on the seed layer 200 with the buffer layer 250. Specifically, electrolytic deposition was carried out for 1 hour 30 minutes at a current density of 20 mA / cm ² using a watt bath to form a Ni thin film buffer layer 250 having a thickness of about 40;

[65] Finally, the silicon substrate 100 is stressed over the buffer layer 250.

The Ni-P thin film is electrolytically deposited as the stress layer 300. Specifically, 20 mA / is applied using a plating bath in which 0.6M NiCl ₂ and (.5M H ₃ B0 ₃ are added with 0.01M ¾:? 0 ₃ . NP thin film of about 50 thickness by electrolytic deposition for 1 hour 30 minutes with a current density of cm ²

The stress layer 300 was formed.

Since the Ni thin film formed of the buffer layer 250 has a small electrolytic deposition force, as shown in FIG. 1, the electrolytic deposition stress of the stress layer 300 is satisfied to apply stress to the surface of the silicon substrate 100 as a whole. ， Prevent destruction of the peeled silicon thin film 120.

FIG. 8 is a photograph showing the result of peeling a silicon substrate according to an embodiment including a buffer layer for a 3.5 cm x 3.5 cm silicon substrate. As shown in the photograph, the silicon thin film is peeled off on the left side. From this, it can be seen that without changing the conditions for electrolytic deposition of the stress layer, a small buffer layer of electrolytic deposition force can be formed between the stress layer and the silicon substrate to prevent breakage of the peeled silicon thin film.

FIG. 9 is a photograph showing the dissolution of Ni and Ni-P in the silicon thin film peeled from FIG. 8. In the process of peeling, the silicon thin film to which the Ni thin film buffer layer and the Ni-P stress layer were bonded was placed in hydrochloric acid. After removing Ni-P and Ni-P, the complete silicon thin film was peeled off.

[69] As described above, the surface of the crystalline silicon substrate was prepared using the electrolytic deposition force.

The present invention, which peels off, uses an electrolytic deposition process that is inexpensive and capable of mass processing to produce a silicon thin film by peeling the surface of the crystalline silicon substrate. The manufacturing cost can be greatly reduced. In addition, since the electrolytic deposition process does not need to apply a high temperature, the silicon thin film peeled by the present invention has no problem of quality deterioration that can occur at high temperature.

[70]

The crystalline silicon thin film peeled by the embodiment of the present invention has a thickness thinner than that which can be cut on a silicon wafer in a general manner, and exhibits excellent characteristics compared to the amorphous silicon thin film, and thus can be applied to various devices.

[72] In particular, the solar cell is fabricated using the crystalline silicon thin film produced by the present invention.

In the case of manufacturing, the material cost is greatly reduced compared to the general single crystalline silicon solar cell, and the efficiency is very high compared to the general amorphous silicon solar cell.

[73]

The present invention has been described with reference to preferred embodiments, which are illustrative only for describing the technical idea of the present invention, and various changes can be made without departing from the technical idea of the present invention. Those of ordinary skill in the art will understand that the scope of protection of the present invention should be interpreted not by specific embodiments but by the matters described in the claims, and all technical ideas within the scope of the present invention are equivalent. It should be interpreted as being included in the scope of rights of the right.

Claims

Claim

Preparing a crystalline silicon substrate;

Constructing a plating bath for electrodeposition; Forming a stress layer on the silicon substrate by an electrolytic deposition process using the plating bath; and

Peeling the surface of the crystalline silicon substrate by the electrolytic deposition force remaining in the stress layer.

In claim 1,

Prior to forming a stress layer on the crystalline silicon substrate, further comprising forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the crystalline silicon substrate and the stress layer. Of surface peeling method.

In claim 1,

In the step of forming the plating bath, the method of peeling the surface of the silicon substrate, characterized in that by adding an additive to the plating bath to adjust the electrolytic deposition force remaining in the stress layer.

In claim 1,

In the step of forming the stress layer, the surface peeling method of the silicon substrate, characterized in that by adjusting the current density of the electrolytic deposition process to control the electrolytic deposition force remaining in the stress layer.

In claim 1,

A surface peeling method of a silicon substrate, characterized in that the stress layer is one of Ni, Co, and Fe or an alloy thereof.

In claim 1,

And said stress layer is a Ni metal thin film, wherein P is added to said Ni metal thin film.

In claim 1,

Upper Plating Bath A method of peeling a surface of a silicon substrate comprising 1 ₂ and H ₃ B0 ₃ and ¾P0 ₃ .

Preparing a crystalline silicon substrate;

Forming a buffer layer on the crystalline silicon substrate;

Configuring a plating bath for electrolytic deposition;

Forming a stress layer on the surface of the buffer layer by an electrolytic deposition process using the plating bath; and Peeling the surface of the crystalline silicon substrate by the electrolytic deposition forces remaining in the stress layer, wherein the surface of the silicon substrate is characterized in that the force remaining in the buffer layer is smaller than the electrolytic deposition force remaining in the stress layer. Peeling method.

In claim 8,

Adjust the thickness of the buffer layer to determine the depth of the electrolytic deposition force remaining on the stress layer on the crystalline silicon substrate.

Adjusting the thickness of the exfoliated crystalline silicon by adjusting the surface of the silicon substrate.

In claim 8,

And in the step of constructing the plating bath, adding an additive to the plating bath to adjust the electrolytic deposition force remaining in the stress layer.

In claim 8,

In the step of forming the stress layer, the surface peeling method of the silicon substrate, characterized in that for adjusting the current deposition of the electrolytic deposition process to control the electrolytic deposition force remaining in the stress layer.

In claim 8,

The method according to claim 8,

And the plating bath comprises NiCl ₂ and H ₃ B0 ₃ and H ₃ P0 ₃ .

The method according to claim 8,

And the step of forming the buffer layer is performed by an electrolytic deposition process.

The method according to claim 10,

Prior to forming the buffer layer on the crystalline silicon substrate, further comprising the step of forming a seed layer on the surface of the crystalline silicon substrate to improve the adhesion between the crystalline silicon substrate and the buffer layer of the silicon substrate Surface Peeling Method.