WO2015029638A1 - 電力用半導体装置及びその製造方法、並びに、そのための半田 - Google Patents

電力用半導体装置及びその製造方法、並びに、そのための半田 Download PDF

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Publication number
WO2015029638A1
WO2015029638A1 PCT/JP2014/069108 JP2014069108W WO2015029638A1 WO 2015029638 A1 WO2015029638 A1 WO 2015029638A1 JP 2014069108 W JP2014069108 W JP 2014069108W WO 2015029638 A1 WO2015029638 A1 WO 2015029638A1
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Prior art keywords
solder
mass
bonding
semiconductor element
semiconductor device
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Ceased
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PCT/JP2014/069108
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English (en)
French (fr)
Japanese (ja)
Inventor
靖 池田
高彰 宮崎
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering or brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400°C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices
    • B23K2101/42—Printed circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic materials other than metals or composite materials
    • B23K2103/52—Ceramics
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00—Materials to be soldered, welded or cut
    • B23K2103/50—Inorganic materials other than metals or composite materials
    • B23K2103/56—Inorganic materials other than metals or composite materials being semiconducting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/346—Solder materials or compositions specially adapted therefor
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    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
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    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
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    • H10W72/07336—Soldering or alloying
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    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07341—Controlling the bonding environment, e.g. atmosphere composition or temperature
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5525—Materials of bond wires comprising metals or metalloids, e.g. silver comprising copper [Cu]
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/874—On different surfaces
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof for power hot reliability is required, in particular, IGBT (I nsulated G ate B ipolar T ransistor) configuration and the manufacturing method thereof of a power semiconductor module having a power semiconductor element such as a Furthermore, the present invention relates to solder for that purpose.
  • IGBT I nsulated G ate B ipolar T ransistor
  • Power semiconductor modules such as IGBT modules are used in inverters that control high-power motors, such as those for electric railways, power generation, and electric / hybrid vehicles (EV / HEV).
  • solder containing lead has been used for various joints of power semiconductor modules.
  • the lead component has an adverse effect on the human body, and such lead-containing solder has been closed up as a major social problem, and is represented by the EU's ROHS (Restriction of Hazardous Substances Directive) directive.
  • ROHS Restriction of Hazardous Substances Directive
  • next-generation power semiconductor devices such as SiC and GaN, which can operate at a higher temperature than Si
  • next-generation power semiconductor devices such as SiC and GaN, which can operate at a higher temperature than Si
  • the power semiconductor modules may be used in a high temperature environment exceeding 175 ° C., which has not been conventionally used.
  • the melting point of Sn-based solder is 200 to 250 ° C., which is an extremely severe environment. Therefore, there has been a problem of improving the reliability of Sn-based solder at a temperature of 175 ° C. or higher.
  • Patent Document 1 discloses a conventional technique for improving the reliability of Sn-based solder at a joint portion (ceramic substrate joint portion) between a ceramic substrate and a base substrate.
  • Sn-0.1 to 4.5Ag-0.1 to 5.0Cu-3 to 7In (mass%) is cited as a solder that can obtain the reliability higher than that of the conventional Sn-Ag-Cu-based lead-free solder. Since this solder is more easily creep-deformed than Sn—Ag—Cu solder, it is difficult to cause fatigue failure even in large area bonding such as a ceramic substrate bonding portion. However, with this solder, it is difficult to obtain reliability because the interface reaction between the solder and the member proceeds remarkably at a high temperature of 175 ° C. or higher.
  • Patent Document 2 As a prior art for ensuring the reliability of the bonding interface in a high temperature environment, there is, for example, Patent Document 2.
  • Patent Document 2 a joining interface having Ni metallization is joined with Sn-3 to 10Cu (mass%) solder, whereby a stable joining interface can be obtained even at 200 ° C.
  • this conventional technique cannot sufficiently suppress thermal fatigue failure in, for example, a large area bonding such as a ceramic substrate bonding portion.
  • JP 2009-70863 A Japanese Patent No. 4569423
  • Patent Document 1 the suppression of the interfacial reaction between the solder and the member in a high temperature environment of 175 ° C. or higher
  • Patent Document 2 the suppression of the thermal fatigue failure in the bonding of a large area such as a ceramic substrate. No consideration was given to.
  • the present invention has been made in view of the above-described prior art, and its purpose is to prevent the above-described problems in the prior art, that is, the suppression of the interface reaction at the joint in a high temperature environment of 175 ° C. and the suppression of thermal fatigue breakdown. It is to provide a semiconductor device and a semiconductor device manufacturing method capable of achieving both, and solder for the semiconductor device.
  • a semiconductor device including a ceramic substrate on which a power semiconductor element is mounted and a base, or a power semiconductor element and a lead frame, wherein the ceramic substrate and the base are bonded with a bonding material, or The power semiconductor element and the lead frame are joined by a joining material, and the joining material is Sn, Ag of 0 to 3.5 (mass%) and 3 to 10 (mass%) with respect to the Sn. Cu and 1-4 (mass%) Bi.
  • the method for manufacturing a semiconductor device includes a step of bonding a ceramic substrate on which a power semiconductor element is mounted with a solder, or a step of bonding a power semiconductor element to a lead frame with a solder, wherein the bonding material is Sn, It contains 0 to 3.5 (mass%) Ag, 3 to 10 (mass%) Cu and 1 to 4% (mass%) Bi with respect to Sn.
  • Solder for manufacturing a semiconductor device manufactured by bonding a ceramic substrate on which a power semiconductor element is mounted to a base or bonding a power semiconductor element to a lead frame is Sn, and 0 to Contains 3.5 (mass%) Ag, 3-10 (mass%) Cu, and 1-4 (mass%) Bi.
  • a semiconductor device and a method for manufacturing the semiconductor device capable of achieving both suppression of interface reaction at a joint portion in a high temperature environment of 175 ° C. and suppression of thermal fatigue breakdown, and solder for the semiconductor device. It is possible to achieve an extremely excellent effect in terms of being provided.
  • FIG. 5 is a view showing a cross section of a joint portion of Sn-3Ag-0.5Cu-5In solder after 250 cycles in a temperature cycle test at ⁇ 55 ° C. to 200 ° C. Section of the joint with Sn-3Ag-7Cu-3Bi solder ( Figure 7 (A)) and section of the joint with Sn-3Ag-7Cu-5In solder ( Figure 7 (B)) when held at 200 ° C for 500h
  • FIG. It is sectional drawing which shows the structure of the power semiconductor module which concerns on other embodiment of this invention. It is a figure which shows the relationship between holding time and Ni plating loss
  • FIG. 1 attached herewith is a cross-sectional view showing the overall configuration of a power semiconductor module according to an embodiment of the present invention.
  • a bonding material for example, high-lead solder, Zn-Al, sintered Ag, Cu, or the like
  • the semiconductor element 1 for example, IGBT
  • the semiconductor element 2 for example, a diode
  • Sn-based intermetallic compound 4 is joined by the Sn-based intermetallic compound
  • a wire 8 such as Al or Cu was connected, and then the ceramic substrate 5 to which the semiconductor element 1 and the semiconductor element 2 were bonded was bonded onto the base 7 with solder (bonding material) 30 described in detail below. Further, a Cu terminal 3 is ultrasonically bonded to a Cu wiring (that is, a Cu-uncoated substrate) on the ceramic substrate 5 bonded onto the base 7 to produce a power semiconductor module.
  • the semiconductor element 1 and the semiconductor element 2 are also called power semiconductor elements.
  • the solder 30 has a composition of Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) (hereinafter, "Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder”) Also called).
  • Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder is Sn and 0 to 3.5 (mass%) Ag and 3 to 10 (mass%) with respect to Sn. This is a solder containing Cu and 1 to 4 (mass%) Bi.
  • FIGS. The results of testing the solder 30 in a temperature cycle of ⁇ 55 ° C. to 200 ° C. are shown in FIGS.
  • the horizontal axis represents the Bi concentration dissolved in the Sn matrix of the solder 30, and the vertical axis represents the Cu content in the solder 30. All of Bi contained in the solder 30 is dissolved in the Sn matrix.
  • “ ⁇ ” indicates a composition with good reliability in the temperature cycle test
  • “ ⁇ ” indicates a composition with no reliability due to interfacial reaction breakdown
  • ⁇ Indicates a composition whose reliability was not obtained mainly due to thermal fatigue failure.
  • “ ⁇ ” indicates a composition in which interfacial reaction failure and thermal fatigue failure cause destruction to the same extent.
  • the content ratio of each component will be described.
  • the Bi content in the Sn matrix will be described. If the Bi content in the Sn matrix is less than 1%, thermal fatigue failure cannot be suppressed. When Bi is added to the Sn matrix, thermal fatigue failure can be suppressed by the effect of solid solution strengthening of the Sn matrix and the effect of easy creep deformation at high temperatures.
  • Fig. 4 shows a Sn-3Ag-0.5Cu (mass%) solder with a thickness of 100 ⁇ m and a Sn-3Ag-0.5Cu-3Bi (mass%) solder included in the composition range of solder 30 at a load of 2MPa at 200 ° C. It is a photograph when it is made to creep-deform over. It can be seen that the Sn-3Ag-0.5Cu-3Bi (mass%) solder shown in FIG. 4 (B) creeps more greatly than the Sn-3Ag-0.5Cu (mass%) solder shown in FIG. 4 (A). . This large creep deformation is obtained when the Bi content is 1 to 4 mass%. When the Bi content in the Sn matrix is higher than 4%, even if the Cu content is increased, Bi tends to segregate at the bonding interface, and the interface reaction suppressing effect in a high temperature environment is significantly reduced.
  • the Cu content When the Cu content is less than 3%, the interfacial reaction suppression effect in a high temperature environment is significantly reduced. On the other hand, if the Cu content is higher than 10%, the solidus temperature of the solder becomes high and joining becomes extremely difficult. That is, a Cu content of 10% is the joining limit.
  • FIG. 5 shows the results of a temperature cycle test of ⁇ 55 ° C. to 200 ° C. for a sample in which a 10 mm square Invar plate is joined to a 15 mm square Cu plate with various solders having a thickness of 100 ⁇ m.
  • Each sample number (n) is five.
  • the bonding ratio is a ratio between the bonding area after the temperature cycle test and the bonding before the temperature cycle test (0 cycle).
  • Sn-3Ag-0.5Cu (mass%) solder curve A in the lowermost part of the graph
  • a joint ratio of 10% or less due to thermal fatigue failure and joint interface failure
  • reference numeral 5 denotes a ceramic substrate
  • reference numeral 11 denotes an Invar plate
  • reference numeral 21 denotes an intermetallic compound.
  • the upper and lower electrodes of the semiconductor element 31 are connected to the solder 30 described above.
  • the lead frame (upper lead and lower lead) 9 is joined. It is preferable to seal the periphery of each joint between the semiconductor element 31 and the lead frame 9 with a hard resin.
  • the semiconductor element 31 is also called a power semiconductor element.
  • the thermal expansion coefficient of the resin is desirably 10 ppm / K or more.
  • the thermal expansion coefficient of the resin is less than 10 ppm / k, the effect of suppressing the progress of cracks due to the thermal shock of the joint portion is reduced.
  • the ceramic substrate 5 to which the semiconductor element is bonded is connected to Sn-0 to 3.5Ag-5 to which Si is added to the solder 30. Bonded to the base 7 by 10Cu-1 to 4Bi-0.001 to 0.1Si (mass%) solder (hereinafter referred to as solder 30A). Further, the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30A.
  • solder by adding 0.001 to 0.1 Si (mass%) to the solder 30, fine precipitates such as Cu—Si compounds are dispersed and precipitated in the Sn matrix.
  • solder can be strengthened and thermal fatigue resistance can be improved.
  • Si content is less than 0.001%, the solder cannot be sufficiently strengthened.
  • Si content is higher than 0.1%, the Si oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
  • solder 30B solder 30B
  • the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30B.
  • solder 30A of the first modification by adding 0.001 to 0.1 Ti (mass%) to the solder 30, as in the solder 30A of the first modification, precipitates such as fine Cu-Si compounds in the Sn matrix. Are dispersed and precipitated. Thereby, solder can be strengthened and thermal fatigue resistance can be improved. If the Ti content is less than 0.001%, the solder cannot be strengthened sufficiently. On the other hand, if the Ti content is higher than 0.1%, the Ti oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
  • the solder composition is a so-called Sn-0 to 3.5Ag-5 to 10Cu-1 to 4Bi (mass%) solder with a Cu composition of 5 to 10 (mass%).
  • FIG. 9 shows the relationship of the Ni plating disappearance thickness when the Ni plated member is joined with Sn-based solder and held at 200 ° C.
  • FIG. 9 From this, it can be seen that the effect appears when the Cu content is 3 mass% or more, but in particular, when the Cu content is 5 mass% or more, the reaction suppressing effect becomes extremely large.
  • ceramics having a Ni-plated wiring as the ceramic substrate 5 are provided.
  • the substrate or the lead frame 9 is a lead frame having a Ni-plated wiring.
  • the Cu—Sn compound is selected on the Ni-based plating. Since this precipitates and functions as a diffusion barrier that suppresses interfacial reactions at high temperatures, high high temperature reliability can be obtained.
  • the thickness of the Ni-based plating is desirably 0.2 ⁇ m or more. If the thickness of the Ni plating is less than 0.2 ⁇ m, the effect of applying the Ni plating may be lost.
  • the thickness of the joint portion by the solder 30 or the solder 30A or the solder 30B is 50 to 500 ⁇ m.
  • the thickness of the joint is less than 50 ⁇ m, the stress buffering ability may be reduced and the joint reliability may not be obtained, and the Cu—Sn system that is selectively formed on the Ni-based plating at the time of joining. This is because the thickness of the compound is reduced and it becomes difficult to obtain the effect of the diffusion barrier.
  • the thickness of the joint is greater than 500 ⁇ m, the proportion of the Cu—Sn compound contained in the solder in the form of floating islands increases in the joint, not in the solder joint interface, leading to a decrease in joint reliability. There is a fear.
  • SiC or GaN As the semiconductor element 1, the semiconductor element 2, and the semiconductor element 31, respectively.
  • the loss of the power semiconductor module can be reduced.
  • the cooling equipment for the inverter is simplified, and the entire device can be made smaller and lighter.
  • the joint portion (ceramic substrate joint portion) under the ceramic substrate is heated to about 200 ° C.
  • desired reliability can be obtained by the solder 30 or the solder 30A or the solder 30B described above.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate with Zn-Al.
  • the melting point of Zn—Al is about 380 ° C., and therefore, if the ceramic substrate 5 on which the semiconductor elements 1 and 2 are mounted is bonded to the base 7 at a temperature lower than 380 ° C., the semiconductor elements 1 and 2 It is because it can join, without remelting each junction part (semiconductor element junction part) of a ceramic substrate.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • the bonding temperature is higher in order to obtain a good bonding without voids or unwetting.
  • Zn—Al for the semiconductor element junction, a junction margin can be secured.
  • connection reliability can be improved.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with sintered Ag.
  • the melting point of sintered Ag is about 900 ° C.
  • the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 at a temperature lower than 900 ° C.
  • the semiconductor element junction is remelted. It is because it can join without making it.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • the joint temperature is higher.
  • a bonding margin can be secured by using sintered Ag for the semiconductor element bonding portion.
  • connection reliability can be improved.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with a Cu—Sn intermetallic compound.
  • the melting point is 400 ° C. or higher when bonded with a Cu—Sn based intermetallic compound, so if the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded at a temperature lower than 400 ° C., the semiconductor element It is because it can join, without remelting a junction part.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • it is advantageous that the joint temperature is higher.
  • a junction margin can be secured.
  • connection reliability can be improved.
  • the ceramic substrate 5 after bonding the semiconductor element 1 and the semiconductor element 2 to the ceramic substrate 5, it is preferable to bond the ceramic substrate 5 to the base 7 using the solder 30, the solder 30A, or the solder 30B in a reducing atmosphere with hydrogen or formic acid. . Further, it is preferable to join the semiconductor element 31 to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid.
  • the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 in a reducing atmosphere with hydrogen or formic acid, or the semiconductor element 31 is bonded to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid.
  • the solder 30 or the solder 30A or the solder 30B is satisfactorily wetted by the member, and a joining with less voids and non-wetting is obtained. It is easy to ensure high temperature reliability by obtaining joints with less voids and non-wetting.
  • the ceramic substrate 5 to the base 7 or the semiconductor element 31 to the lead frame 9 using the solder 30 or the solder 30A or the solder 30B at a maximum temperature of 250 to 350 ° C.
  • Examples 1 to 11 are shown in Table 1. That is, a temperature cycle test of ⁇ 55 ° C. to 200 ° C. for a power semiconductor module manufactured using the bonding material under substrate (solder for ceramic substrate bonding) and element bonding material (bonding material for semiconductor element bonding) shown in Table 1 The determination was made “x” when the crack in the ceramic substrate joint reached just below the chip, and the judgment was made “good” when the crack in the ceramic substrate joint did not reach just below the chip.
  • Comparative Examples 1 to 5 A power semiconductor module having the same shape was manufactured through the same steps as those in Examples 1 to 11 described above.
  • Table 2 shows the solder (bonding material under the substrate) used for bonding the ceramic substrates.
  • the crack in the ceramic substrate joint reached just below the chip in the temperature cycle test.
  • Comparative Examples 1 to 4 20% or more of the joints were broken due to interface fracture.
  • Sn-7Cu of Comparative Example 5 had good reliability in the high temperature holding test. In other words, none of these Comparative Examples 1 to 5 could obtain good reliability in both the temperature cycle test and the high temperature holding test.
  • solder 30 is applied to the power semiconductor module whose structure is shown in FIG. 8 will be described below.
  • a power semiconductor module was manufactured by joining a semiconductor element 31 with solder 30 on a Cu lead frame 9 plated with Ni.
  • Table 3 shows solders (joining materials) used for joining the semiconductor elements of Examples 12 to 22.
  • a temperature cycle test of -55 ° C to 200 ° C was conducted up to 1000 cycles, and when the crack reached 20% of the semiconductor element junction, the judgment was “x”, and the semiconductor element junction 20 When the crack did not reach to%, the judgment was “ ⁇ ”.
  • a high temperature holding test at 200 ° C. for 1000 hours is performed, and the determination is “X” when 20% or more of the semiconductor element junction is broken, and the determination is made when 20% or more of the semiconductor element junction is not broken. “ ⁇ ”.
  • Table 3 in any of the examples, good bonding reliability was obtained in the temperature cycle test and the high temperature holding test.
  • SYMBOLS 1 ... Semiconductor element (IGBT), 2 ... Semiconductor element (diode), 3 ... Cu terminal, 4 ... Bonding material, 5 ... Ceramic substrate, 7 ... Base, 8 ... Wire, 9 ... Lead frame, 11 ... Invar plate, 21 ... Intermetallic compound, 30 ... Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder, 31 ... Semiconductor element

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  • Die Bonding (AREA)
PCT/JP2014/069108 2013-08-30 2014-07-17 電力用半導体装置及びその製造方法、並びに、そのための半田 Ceased WO2015029638A1 (ja)

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JP2002252351A (ja) * 2001-02-26 2002-09-06 Sanyo Electric Co Ltd 半導体装置
JP2009060746A (ja) * 2007-09-03 2009-03-19 Sumitomo Electric Ind Ltd コネクタユニット
JP2013033891A (ja) * 2011-08-03 2013-02-14 Hitachi Ltd 半導体装置及びその製造方法

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US20040241039A1 (en) * 2000-10-27 2004-12-02 H-Technologies Group High temperature lead-free solder compositions
JP5523680B2 (ja) * 2008-05-29 2014-06-18 株式会社東芝 接合体、半導体装置および接合体の製造方法
DE102010044709B4 (de) * 2010-09-08 2015-07-02 Vincotech Holdings S.à.r.l. Leistungshalbleitermodul mit Metallsinterverbindungen sowie Herstellungsverfahren
JP5675525B2 (ja) * 2011-07-28 2015-02-25 日産自動車株式会社 半導体装置の製造方法及び半導体装置

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Publication number Priority date Publication date Assignee Title
JP2002252351A (ja) * 2001-02-26 2002-09-06 Sanyo Electric Co Ltd 半導体装置
JP2009060746A (ja) * 2007-09-03 2009-03-19 Sumitomo Electric Ind Ltd コネクタユニット
JP2013033891A (ja) * 2011-08-03 2013-02-14 Hitachi Ltd 半導体装置及びその製造方法

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