WO2015029638A1 - Semiconductor device for power generation, method for manufacturing same, and solder therefor - Google Patents

Semiconductor device for power generation, method for manufacturing same, and solder therefor Download PDF

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Publication number
WO2015029638A1
WO2015029638A1 PCT/JP2014/069108 JP2014069108W WO2015029638A1 WO 2015029638 A1 WO2015029638 A1 WO 2015029638A1 JP 2014069108 W JP2014069108 W JP 2014069108W WO 2015029638 A1 WO2015029638 A1 WO 2015029638A1
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Prior art keywords
solder
mass
bonding
semiconductor element
semiconductor device
Prior art date
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PCT/JP2014/069108
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French (fr)
Japanese (ja)
Inventor
靖 池田
高彰 宮崎
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株式会社日立製作所
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Publication of WO2015029638A1 publication Critical patent/WO2015029638A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0244—Powders, particles or spheres; Preforms made therefrom
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
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    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof for power hot reliability is required, in particular, IGBT (I nsulated G ate B ipolar T ransistor) configuration and the manufacturing method thereof of a power semiconductor module having a power semiconductor element such as a Furthermore, the present invention relates to solder for that purpose.
  • IGBT I nsulated G ate B ipolar T ransistor
  • Power semiconductor modules such as IGBT modules are used in inverters that control high-power motors, such as those for electric railways, power generation, and electric / hybrid vehicles (EV / HEV).
  • solder containing lead has been used for various joints of power semiconductor modules.
  • the lead component has an adverse effect on the human body, and such lead-containing solder has been closed up as a major social problem, and is represented by the EU's ROHS (Restriction of Hazardous Substances Directive) directive.
  • ROHS Restriction of Hazardous Substances Directive
  • next-generation power semiconductor devices such as SiC and GaN, which can operate at a higher temperature than Si
  • next-generation power semiconductor devices such as SiC and GaN, which can operate at a higher temperature than Si
  • the power semiconductor modules may be used in a high temperature environment exceeding 175 ° C., which has not been conventionally used.
  • the melting point of Sn-based solder is 200 to 250 ° C., which is an extremely severe environment. Therefore, there has been a problem of improving the reliability of Sn-based solder at a temperature of 175 ° C. or higher.
  • Patent Document 1 discloses a conventional technique for improving the reliability of Sn-based solder at a joint portion (ceramic substrate joint portion) between a ceramic substrate and a base substrate.
  • Sn-0.1 to 4.5Ag-0.1 to 5.0Cu-3 to 7In (mass%) is cited as a solder that can obtain the reliability higher than that of the conventional Sn-Ag-Cu-based lead-free solder. Since this solder is more easily creep-deformed than Sn—Ag—Cu solder, it is difficult to cause fatigue failure even in large area bonding such as a ceramic substrate bonding portion. However, with this solder, it is difficult to obtain reliability because the interface reaction between the solder and the member proceeds remarkably at a high temperature of 175 ° C. or higher.
  • Patent Document 2 As a prior art for ensuring the reliability of the bonding interface in a high temperature environment, there is, for example, Patent Document 2.
  • Patent Document 2 a joining interface having Ni metallization is joined with Sn-3 to 10Cu (mass%) solder, whereby a stable joining interface can be obtained even at 200 ° C.
  • this conventional technique cannot sufficiently suppress thermal fatigue failure in, for example, a large area bonding such as a ceramic substrate bonding portion.
  • JP 2009-70863 A Japanese Patent No. 4569423
  • Patent Document 1 the suppression of the interfacial reaction between the solder and the member in a high temperature environment of 175 ° C. or higher
  • Patent Document 2 the suppression of the thermal fatigue failure in the bonding of a large area such as a ceramic substrate. No consideration was given to.
  • the present invention has been made in view of the above-described prior art, and its purpose is to prevent the above-described problems in the prior art, that is, the suppression of the interface reaction at the joint in a high temperature environment of 175 ° C. and the suppression of thermal fatigue breakdown. It is to provide a semiconductor device and a semiconductor device manufacturing method capable of achieving both, and solder for the semiconductor device.
  • a semiconductor device including a ceramic substrate on which a power semiconductor element is mounted and a base, or a power semiconductor element and a lead frame, wherein the ceramic substrate and the base are bonded with a bonding material, or The power semiconductor element and the lead frame are joined by a joining material, and the joining material is Sn, Ag of 0 to 3.5 (mass%) and 3 to 10 (mass%) with respect to the Sn. Cu and 1-4 (mass%) Bi.
  • the method for manufacturing a semiconductor device includes a step of bonding a ceramic substrate on which a power semiconductor element is mounted with a solder, or a step of bonding a power semiconductor element to a lead frame with a solder, wherein the bonding material is Sn, It contains 0 to 3.5 (mass%) Ag, 3 to 10 (mass%) Cu and 1 to 4% (mass%) Bi with respect to Sn.
  • Solder for manufacturing a semiconductor device manufactured by bonding a ceramic substrate on which a power semiconductor element is mounted to a base or bonding a power semiconductor element to a lead frame is Sn, and 0 to Contains 3.5 (mass%) Ag, 3-10 (mass%) Cu, and 1-4 (mass%) Bi.
  • a semiconductor device and a method for manufacturing the semiconductor device capable of achieving both suppression of interface reaction at a joint portion in a high temperature environment of 175 ° C. and suppression of thermal fatigue breakdown, and solder for the semiconductor device. It is possible to achieve an extremely excellent effect in terms of being provided.
  • FIG. 5 is a view showing a cross section of a joint portion of Sn-3Ag-0.5Cu-5In solder after 250 cycles in a temperature cycle test at ⁇ 55 ° C. to 200 ° C. Section of the joint with Sn-3Ag-7Cu-3Bi solder ( Figure 7 (A)) and section of the joint with Sn-3Ag-7Cu-5In solder ( Figure 7 (B)) when held at 200 ° C for 500h
  • FIG. It is sectional drawing which shows the structure of the power semiconductor module which concerns on other embodiment of this invention. It is a figure which shows the relationship between holding time and Ni plating loss
  • FIG. 1 attached herewith is a cross-sectional view showing the overall configuration of a power semiconductor module according to an embodiment of the present invention.
  • a bonding material for example, high-lead solder, Zn-Al, sintered Ag, Cu, or the like
  • the semiconductor element 1 for example, IGBT
  • the semiconductor element 2 for example, a diode
  • Sn-based intermetallic compound 4 is joined by the Sn-based intermetallic compound
  • a wire 8 such as Al or Cu was connected, and then the ceramic substrate 5 to which the semiconductor element 1 and the semiconductor element 2 were bonded was bonded onto the base 7 with solder (bonding material) 30 described in detail below. Further, a Cu terminal 3 is ultrasonically bonded to a Cu wiring (that is, a Cu-uncoated substrate) on the ceramic substrate 5 bonded onto the base 7 to produce a power semiconductor module.
  • the semiconductor element 1 and the semiconductor element 2 are also called power semiconductor elements.
  • the solder 30 has a composition of Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) (hereinafter, "Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder”) Also called).
  • Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder is Sn and 0 to 3.5 (mass%) Ag and 3 to 10 (mass%) with respect to Sn. This is a solder containing Cu and 1 to 4 (mass%) Bi.
  • FIGS. The results of testing the solder 30 in a temperature cycle of ⁇ 55 ° C. to 200 ° C. are shown in FIGS.
  • the horizontal axis represents the Bi concentration dissolved in the Sn matrix of the solder 30, and the vertical axis represents the Cu content in the solder 30. All of Bi contained in the solder 30 is dissolved in the Sn matrix.
  • “ ⁇ ” indicates a composition with good reliability in the temperature cycle test
  • “ ⁇ ” indicates a composition with no reliability due to interfacial reaction breakdown
  • ⁇ Indicates a composition whose reliability was not obtained mainly due to thermal fatigue failure.
  • “ ⁇ ” indicates a composition in which interfacial reaction failure and thermal fatigue failure cause destruction to the same extent.
  • the content ratio of each component will be described.
  • the Bi content in the Sn matrix will be described. If the Bi content in the Sn matrix is less than 1%, thermal fatigue failure cannot be suppressed. When Bi is added to the Sn matrix, thermal fatigue failure can be suppressed by the effect of solid solution strengthening of the Sn matrix and the effect of easy creep deformation at high temperatures.
  • Fig. 4 shows a Sn-3Ag-0.5Cu (mass%) solder with a thickness of 100 ⁇ m and a Sn-3Ag-0.5Cu-3Bi (mass%) solder included in the composition range of solder 30 at a load of 2MPa at 200 ° C. It is a photograph when it is made to creep-deform over. It can be seen that the Sn-3Ag-0.5Cu-3Bi (mass%) solder shown in FIG. 4 (B) creeps more greatly than the Sn-3Ag-0.5Cu (mass%) solder shown in FIG. 4 (A). . This large creep deformation is obtained when the Bi content is 1 to 4 mass%. When the Bi content in the Sn matrix is higher than 4%, even if the Cu content is increased, Bi tends to segregate at the bonding interface, and the interface reaction suppressing effect in a high temperature environment is significantly reduced.
  • the Cu content When the Cu content is less than 3%, the interfacial reaction suppression effect in a high temperature environment is significantly reduced. On the other hand, if the Cu content is higher than 10%, the solidus temperature of the solder becomes high and joining becomes extremely difficult. That is, a Cu content of 10% is the joining limit.
  • FIG. 5 shows the results of a temperature cycle test of ⁇ 55 ° C. to 200 ° C. for a sample in which a 10 mm square Invar plate is joined to a 15 mm square Cu plate with various solders having a thickness of 100 ⁇ m.
  • Each sample number (n) is five.
  • the bonding ratio is a ratio between the bonding area after the temperature cycle test and the bonding before the temperature cycle test (0 cycle).
  • Sn-3Ag-0.5Cu (mass%) solder curve A in the lowermost part of the graph
  • a joint ratio of 10% or less due to thermal fatigue failure and joint interface failure
  • reference numeral 5 denotes a ceramic substrate
  • reference numeral 11 denotes an Invar plate
  • reference numeral 21 denotes an intermetallic compound.
  • the upper and lower electrodes of the semiconductor element 31 are connected to the solder 30 described above.
  • the lead frame (upper lead and lower lead) 9 is joined. It is preferable to seal the periphery of each joint between the semiconductor element 31 and the lead frame 9 with a hard resin.
  • the semiconductor element 31 is also called a power semiconductor element.
  • the thermal expansion coefficient of the resin is desirably 10 ppm / K or more.
  • the thermal expansion coefficient of the resin is less than 10 ppm / k, the effect of suppressing the progress of cracks due to the thermal shock of the joint portion is reduced.
  • the ceramic substrate 5 to which the semiconductor element is bonded is connected to Sn-0 to 3.5Ag-5 to which Si is added to the solder 30. Bonded to the base 7 by 10Cu-1 to 4Bi-0.001 to 0.1Si (mass%) solder (hereinafter referred to as solder 30A). Further, the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30A.
  • solder by adding 0.001 to 0.1 Si (mass%) to the solder 30, fine precipitates such as Cu—Si compounds are dispersed and precipitated in the Sn matrix.
  • solder can be strengthened and thermal fatigue resistance can be improved.
  • Si content is less than 0.001%, the solder cannot be sufficiently strengthened.
  • Si content is higher than 0.1%, the Si oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
  • solder 30B solder 30B
  • the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30B.
  • solder 30A of the first modification by adding 0.001 to 0.1 Ti (mass%) to the solder 30, as in the solder 30A of the first modification, precipitates such as fine Cu-Si compounds in the Sn matrix. Are dispersed and precipitated. Thereby, solder can be strengthened and thermal fatigue resistance can be improved. If the Ti content is less than 0.001%, the solder cannot be strengthened sufficiently. On the other hand, if the Ti content is higher than 0.1%, the Ti oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
  • the solder composition is a so-called Sn-0 to 3.5Ag-5 to 10Cu-1 to 4Bi (mass%) solder with a Cu composition of 5 to 10 (mass%).
  • FIG. 9 shows the relationship of the Ni plating disappearance thickness when the Ni plated member is joined with Sn-based solder and held at 200 ° C.
  • FIG. 9 From this, it can be seen that the effect appears when the Cu content is 3 mass% or more, but in particular, when the Cu content is 5 mass% or more, the reaction suppressing effect becomes extremely large.
  • ceramics having a Ni-plated wiring as the ceramic substrate 5 are provided.
  • the substrate or the lead frame 9 is a lead frame having a Ni-plated wiring.
  • the Cu—Sn compound is selected on the Ni-based plating. Since this precipitates and functions as a diffusion barrier that suppresses interfacial reactions at high temperatures, high high temperature reliability can be obtained.
  • the thickness of the Ni-based plating is desirably 0.2 ⁇ m or more. If the thickness of the Ni plating is less than 0.2 ⁇ m, the effect of applying the Ni plating may be lost.
  • the thickness of the joint portion by the solder 30 or the solder 30A or the solder 30B is 50 to 500 ⁇ m.
  • the thickness of the joint is less than 50 ⁇ m, the stress buffering ability may be reduced and the joint reliability may not be obtained, and the Cu—Sn system that is selectively formed on the Ni-based plating at the time of joining. This is because the thickness of the compound is reduced and it becomes difficult to obtain the effect of the diffusion barrier.
  • the thickness of the joint is greater than 500 ⁇ m, the proportion of the Cu—Sn compound contained in the solder in the form of floating islands increases in the joint, not in the solder joint interface, leading to a decrease in joint reliability. There is a fear.
  • SiC or GaN As the semiconductor element 1, the semiconductor element 2, and the semiconductor element 31, respectively.
  • the loss of the power semiconductor module can be reduced.
  • the cooling equipment for the inverter is simplified, and the entire device can be made smaller and lighter.
  • the joint portion (ceramic substrate joint portion) under the ceramic substrate is heated to about 200 ° C.
  • desired reliability can be obtained by the solder 30 or the solder 30A or the solder 30B described above.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate with Zn-Al.
  • the melting point of Zn—Al is about 380 ° C., and therefore, if the ceramic substrate 5 on which the semiconductor elements 1 and 2 are mounted is bonded to the base 7 at a temperature lower than 380 ° C., the semiconductor elements 1 and 2 It is because it can join, without remelting each junction part (semiconductor element junction part) of a ceramic substrate.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • the bonding temperature is higher in order to obtain a good bonding without voids or unwetting.
  • Zn—Al for the semiconductor element junction, a junction margin can be secured.
  • connection reliability can be improved.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with sintered Ag.
  • the melting point of sintered Ag is about 900 ° C.
  • the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 at a temperature lower than 900 ° C.
  • the semiconductor element junction is remelted. It is because it can join without making it.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • the joint temperature is higher.
  • a bonding margin can be secured by using sintered Ag for the semiconductor element bonding portion.
  • connection reliability can be improved.
  • the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with a Cu—Sn intermetallic compound.
  • the melting point is 400 ° C. or higher when bonded with a Cu—Sn based intermetallic compound, so if the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded at a temperature lower than 400 ° C., the semiconductor element It is because it can join, without remelting a junction part.
  • the solder 30 or the solder 30A or the solder 30B melts at about 200 ° C.
  • it is advantageous that the joint temperature is higher.
  • a junction margin can be secured.
  • connection reliability can be improved.
  • the ceramic substrate 5 after bonding the semiconductor element 1 and the semiconductor element 2 to the ceramic substrate 5, it is preferable to bond the ceramic substrate 5 to the base 7 using the solder 30, the solder 30A, or the solder 30B in a reducing atmosphere with hydrogen or formic acid. . Further, it is preferable to join the semiconductor element 31 to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid.
  • the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 in a reducing atmosphere with hydrogen or formic acid, or the semiconductor element 31 is bonded to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid.
  • the solder 30 or the solder 30A or the solder 30B is satisfactorily wetted by the member, and a joining with less voids and non-wetting is obtained. It is easy to ensure high temperature reliability by obtaining joints with less voids and non-wetting.
  • the ceramic substrate 5 to the base 7 or the semiconductor element 31 to the lead frame 9 using the solder 30 or the solder 30A or the solder 30B at a maximum temperature of 250 to 350 ° C.
  • Examples 1 to 11 are shown in Table 1. That is, a temperature cycle test of ⁇ 55 ° C. to 200 ° C. for a power semiconductor module manufactured using the bonding material under substrate (solder for ceramic substrate bonding) and element bonding material (bonding material for semiconductor element bonding) shown in Table 1 The determination was made “x” when the crack in the ceramic substrate joint reached just below the chip, and the judgment was made “good” when the crack in the ceramic substrate joint did not reach just below the chip.
  • Comparative Examples 1 to 5 A power semiconductor module having the same shape was manufactured through the same steps as those in Examples 1 to 11 described above.
  • Table 2 shows the solder (bonding material under the substrate) used for bonding the ceramic substrates.
  • the crack in the ceramic substrate joint reached just below the chip in the temperature cycle test.
  • Comparative Examples 1 to 4 20% or more of the joints were broken due to interface fracture.
  • Sn-7Cu of Comparative Example 5 had good reliability in the high temperature holding test. In other words, none of these Comparative Examples 1 to 5 could obtain good reliability in both the temperature cycle test and the high temperature holding test.
  • solder 30 is applied to the power semiconductor module whose structure is shown in FIG. 8 will be described below.
  • a power semiconductor module was manufactured by joining a semiconductor element 31 with solder 30 on a Cu lead frame 9 plated with Ni.
  • Table 3 shows solders (joining materials) used for joining the semiconductor elements of Examples 12 to 22.
  • a temperature cycle test of -55 ° C to 200 ° C was conducted up to 1000 cycles, and when the crack reached 20% of the semiconductor element junction, the judgment was “x”, and the semiconductor element junction 20 When the crack did not reach to%, the judgment was “ ⁇ ”.
  • a high temperature holding test at 200 ° C. for 1000 hours is performed, and the determination is “X” when 20% or more of the semiconductor element junction is broken, and the determination is made when 20% or more of the semiconductor element junction is not broken. “ ⁇ ”.
  • Table 3 in any of the examples, good bonding reliability was obtained in the temperature cycle test and the high temperature holding test.
  • SYMBOLS 1 ... Semiconductor element (IGBT), 2 ... Semiconductor element (diode), 3 ... Cu terminal, 4 ... Bonding material, 5 ... Ceramic substrate, 7 ... Base, 8 ... Wire, 9 ... Lead frame, 11 ... Invar plate, 21 ... Intermetallic compound, 30 ... Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder, 31 ... Semiconductor element

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Abstract

　Provided is a semiconductor device by which it is possible to mitigate fatigue failure and mitigate interface reaction failure even in a high temperature environment of 175°C or higher, a method for manufacturing the same, and a solder therefor. A semiconductor device manufactured by bonding, onto a base (7), a ceramic substrate (5) on which power semiconductor elements (1, 2) are mounted, or by bonding a power semiconductor element (31) onto a lead frame (9), wherein the ceramic substrate (5) is bonded to the base (7), or the power semiconductor element (31) is bonded to the lead frame (9) using solder (30) comprising Sn, 0-3.5 mass% Ag, 3-10 mass% Cu, 1-4 mass% Bi.

Description

電力用半導体装置及びその製造方法、並びに、そのための半田Power semiconductor device, method of manufacturing the same, and solder for the same
　本発明は、高温信頼性が求められる電力用の半導体装置やその製造方法に関し、特に、IGBT（Insulated Gate Bipolar Transistor）等のパワー半導体素子を有するパワー半導体モジュールの構成及びその製造方法、更には、そのための半田に関する。 The present invention relates to a semiconductor device and a manufacturing method thereof for power hot reliability is required, in particular, IGBT (I nsulated G ate B ipolar T ransistor) configuration and the manufacturing method thereof of a power semiconductor module having a power semiconductor element such as a Furthermore, the present invention relates to solder for that purpose.
　電鉄用、発電用、電気自動車/ハイブリッド自動車（EV/HEV）用モータ等、大出力モータを制御するインバータには、IGBTモジュール等のパワー半導体モジュールが使用される。従来、パワー半導体モジュールの各種接合部には、鉛を含む半田が使用されてきた。しかしながら、鉛成分が人体に悪影響を及ぼすことが指摘されるようになり、かかる鉛入り半田は大きな社会問題としてクローズ・アップされるとともに、EUのROHS（Restriction of Hazardous Substances Directive)指令に代表されるように、鉛を含む有害物質の使用を法的に規制しようと言う動きが活発化している。このような背景から、パワー半導体モジュールについても鉛フリー化が求められている。現時点では、半導体素子とセラミックス基板との接合部（半導体接合部）については汎用的な鉛フリーの接合材料が無いため、高鉛半田が多く使用されている。一方、セラミックス基板下の接合については、Sn－3Ag－0.5Cu（mass％）などのSn系鉛フリー半田が使われるようになってきている。 Power semiconductor modules such as IGBT modules are used in inverters that control high-power motors, such as those for electric railways, power generation, and electric / hybrid vehicles (EV / HEV). Conventionally, solder containing lead has been used for various joints of power semiconductor modules. However, it has been pointed out that the lead component has an adverse effect on the human body, and such lead-containing solder has been closed up as a major social problem, and is represented by the EU's ROHS (Restriction of Hazardous Substances Directive) directive. As such, there is a growing movement to legally regulate the use of hazardous substances including lead. Against this background, power semiconductor modules are also required to be lead-free. At present, since there is no general-purpose lead-free bonding material for the bonding portion (semiconductor bonding portion) between the semiconductor element and the ceramic substrate, high lead solder is often used. On the other hand, Sn-based lead-free solder such as Sn-3Ag-0.5Cu (mass%) has been used for bonding under ceramic substrates.
　近年、Siに比べて高温で動作可能なSiCおよびGaNといった次世代パワー半導体素子が普及しつつある。これらの次世代パワー半導体素子を用いたパワー半導体モジュールでは、従来では使われなかったような、175℃を超える高温環境下でパワー半導体モジュールが使用される可能性がある。このような高温環境下でSn系半田をセラミックス基板下の接合に用いた場合、Sn系半田の融点が200～250℃であり、極めて苛酷な環境となる。そのため、Sn系半田の175℃以上の温度における信頼性向上が課題となっていた。 In recent years, next-generation power semiconductor devices such as SiC and GaN, which can operate at a higher temperature than Si, are becoming widespread. In power semiconductor modules using these next-generation power semiconductor elements, there is a possibility that the power semiconductor modules may be used in a high temperature environment exceeding 175 ° C., which has not been conventionally used. When Sn-based solder is used for bonding under a ceramic substrate in such a high temperature environment, the melting point of Sn-based solder is 200 to 250 ° C., which is an extremely severe environment. Therefore, there has been a problem of improving the reliability of Sn-based solder at a temperature of 175 ° C. or higher.
　セラミックス基板とベース基板との接合部（セラミックス基板接合部）におけるSn系半田の高信頼化についての従来技術としては、例えば特許文献１がある。特許文献１では、従来のSn－Ag－Cu系鉛フリー半田の以上の信頼性を得る半田として、Sn－0.1～4.5Ag－0.1～5.0Cu－3～7In(mass％)を挙げている。この半田は、Sn－Ag－Cu系半田に比べてクリープ変形が容易であるため、セラミックス基板接合部のような大面積の接合においても疲労破壊しにくい。しかしながら、この半田では175℃以上の高温下で半田と部材間の界面反応が顕著に進むため信頼性を得ることが困難であった。 For example, Patent Document 1 discloses a conventional technique for improving the reliability of Sn-based solder at a joint portion (ceramic substrate joint portion) between a ceramic substrate and a base substrate. In Patent Document 1, Sn-0.1 to 4.5Ag-0.1 to 5.0Cu-3 to 7In (mass%) is cited as a solder that can obtain the reliability higher than that of the conventional Sn-Ag-Cu-based lead-free solder. Since this solder is more easily creep-deformed than Sn—Ag—Cu solder, it is difficult to cause fatigue failure even in large area bonding such as a ceramic substrate bonding portion. However, with this solder, it is difficult to obtain reliability because the interface reaction between the solder and the member proceeds remarkably at a high temperature of 175 ° C. or higher.
　一方、高温環境下における接合界面の信頼性を確保する従来技術としては、例えば特許文献２がある。特許文献２では、Niメタライズを有する被接続材をSn－3～10Cu(mass％)半田で接合することで、200℃でも安定な接合界面を得ることができる。しかしながら、この従来技術では、例えば、セラミックス基板接合部のような大面積の接合において、熱疲労破壊を十分に抑制することができない。 On the other hand, as a prior art for ensuring the reliability of the bonding interface in a high temperature environment, there is, for example, Patent Document 2. In Patent Document 2, a joining interface having Ni metallization is joined with Sn-3 to 10Cu (mass%) solder, whereby a stable joining interface can be obtained even at 200 ° C. However, this conventional technique cannot sufficiently suppress thermal fatigue failure in, for example, a large area bonding such as a ceramic substrate bonding portion.
特開２００９－７０８６３号公報JP 2009-70863 A 特許第４５６９４２３号公報Japanese Patent No. 4569423
　上記の従来技術（特許文献１及び特許文献２）においては、以下の点についての配慮がなされていなかった。即ち、特許文献１の場合、175℃以上の高温環境下における半田と部材間における界面反応の抑制について、また、特許文献２の場合、セラミックス基板のような大面積の接合における熱疲労破壊の抑制についての配慮がなされていなかった。 In the above prior art (Patent Document 1 and Patent Document 2), the following points have not been considered. That is, in the case of Patent Document 1, the suppression of the interfacial reaction between the solder and the member in a high temperature environment of 175 ° C. or higher, and in the case of Patent Document 2, the suppression of the thermal fatigue failure in the bonding of a large area such as a ceramic substrate. No consideration was given to.
　本発明は、上述した従来技術に鑑みてなされたものであり、その目的は、上述した従来技術における課題、即ち、175℃の高温環境下における接合部の界面反応抑制と、熱疲労破壊抑制の両立を可能とする半導体装置及び半導体装置の製造方法、並びに、そのための半田を提供することである。 The present invention has been made in view of the above-described prior art, and its purpose is to prevent the above-described problems in the prior art, that is, the suppression of the interface reaction at the joint in a high temperature environment of 175 ° C. and the suppression of thermal fatigue breakdown. It is to provide a semiconductor device and a semiconductor device manufacturing method capable of achieving both, and solder for the semiconductor device.
　本発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
  パワー半導体素子を搭載したセラミックス基板上とベースとを備え、又は、パワー半導体素子とリードフレームとを備える半導体装置であって、前記セラミックス基板と前記ベースとは接合材料で接合して構成され、又は前記パワー半導体素子と前記リードフレームとは接合材料で接合して構成され、前記接合材料は、Snと、前記Snに対して、0～3.5(mass％)のAgと3～10(mass％)のCuと1～4 (mass％)のBiを含む。 The outline of typical ones of the present invention will be briefly described as follows.
A semiconductor device including a ceramic substrate on which a power semiconductor element is mounted and a base, or a power semiconductor element and a lead frame, wherein the ceramic substrate and the base are bonded with a bonding material, or The power semiconductor element and the lead frame are joined by a joining material, and the joining material is Sn, Ag of 0 to 3.5 (mass%) and 3 to 10 (mass%) with respect to the Sn. Cu and 1-4 (mass%) Bi.
　半導体装置の製造方法は、パワー半導体素子を搭載したセラミックス基板をベースに半田で接合する工程、又は、パワー半導体素子をリードフレームに半田で接合する工程を備え、前記接合材料は、Snと、前記Snに対して、0～3.5(mass％)のAgと3～10(mass％)のCuと1～4 (mass％)のBiを含む。 The method for manufacturing a semiconductor device includes a step of bonding a ceramic substrate on which a power semiconductor element is mounted with a solder, or a step of bonding a power semiconductor element to a lead frame with a solder, wherein the bonding material is Sn, It contains 0 to 3.5 (mass%) Ag, 3 to 10 (mass%) Cu and 1 to 4% (mass%) Bi with respect to Sn.
　パワー半導体素子を搭載したセラミックス基板をベースに接合し、又は、パワー半導体素子をリードフレームに接合して製造される半導体装置を製造するための半田は、Snと、前記Snに対して、0～3.5(mass％)のAg、3～10(mass％)のCu、1～4(mass％)のBiを含む。 Solder for manufacturing a semiconductor device manufactured by bonding a ceramic substrate on which a power semiconductor element is mounted to a base or bonding a power semiconductor element to a lead frame is Sn, and 0 to Contains 3.5 (mass%) Ag, 3-10 (mass%) Cu, and 1-4 (mass%) Bi.
　以上に述べた本発明によれば、175℃の高温環境下における接合部の界面反応抑制と、熱疲労破壊抑制の両立を可能とする半導体装置及び半導体装置の製造方法、並びに、そのための半田が提供されるという実用的にも極めて優れた効果を達成することができる。 According to the present invention described above, there are provided a semiconductor device and a method for manufacturing the semiconductor device capable of achieving both suppression of interface reaction at a joint portion in a high temperature environment of 175 ° C. and suppression of thermal fatigue breakdown, and solder for the semiconductor device. It is possible to achieve an extremely excellent effect in terms of being provided.
本発明の一実施の形態に係るパワー半導体モジュールの全体構成を示す断面図である。It is sectional drawing which shows the whole structure of the power semiconductor module which concerns on one embodiment of this invention. Ag含有率0mass％のときの、Sn母相中のBi含有率と、半田のCu含有率と、高温信頼性との関係を示す図である。It is a figure which shows the relationship between the Bi content rate in Sn mother phase, the Cu content rate of solder, and high temperature reliability when Ag content rate is 0 mass%. Ag含有率3.5mass％のときの、Sn母相中のBi含有率と、半田のCu含有率と、高温信頼性との関係を示す図である。It is a figure which shows the relationship between Bi content rate in Sn mother phase, Cu content rate of solder, and high temperature reliability when Ag content rate is 3.5 mass%. 200℃2MPaでクリープ変形させた場合の、Sn－3Ag－0.5Cu(mass％)半田（図４（Ａ））とSn－3Ag－0.5Cu－3Bi(mass％)半田（図４（Ｂ））の外観を示す図である。Sn-3Ag-0.5Cu (mass%) solder (Fig. 4 (A)) and Sn-3Ag-0.5Cu-3Bi (mass%) solder (Fig. 4 (B)) when creep deformed at 200 ℃ 2MPa It is a figure which shows the external appearance. －55℃⇔200℃の温度サイクル試験における各種半田の接合部のサイクル数と接合割合との関係を示す図である。It is a figure which shows the relationship between the cycle number of the junction part of various solders, and a joining ratio in the temperature cycle test of -55 degreeC-200 degreeC. －55℃⇔200℃の温度サイクル試験における250サイクル後の、Sn－3Ag－0.5Cu－5In半田の接合部の断面を示す図である。FIG. 5 is a view showing a cross section of a joint portion of Sn-3Ag-0.5Cu-5In solder after 250 cycles in a temperature cycle test at −55 ° C. to 200 ° C. 200℃で500h保持したときのSn－3Ag－7Cu－3Bi半田による接合部の断面（図７（Ａ））とSn－3Ag－7Cu－5In半田による接合部の断面（図７（Ｂ））を示す図である。Section of the joint with Sn-3Ag-7Cu-3Bi solder (Figure 7 (A)) and section of the joint with Sn-3Ag-7Cu-5In solder (Figure 7 (B)) when held at 200 ° C for 500h FIG. 本発明の他の実施の形態に係るパワー半導体モジュールの構成を示す断面図である。It is sectional drawing which shows the structure of the power semiconductor module which concerns on other embodiment of this invention. Sn系半田でNiめっき部材を接合したサンプルについて、200℃で保持したときの、保持時間とNiめっき消失厚さとの関係を示す図である。It is a figure which shows the relationship between holding time and Ni plating loss | disappearance thickness when it hold | maintains at 200 degreeC about the sample which joined the Ni plating member with Sn type solder.
　以下、本発明を半導体装置であるパワー半導体モジュールに適用した実施の形態について、添付の図面を参照しながら詳細に説明する。ただし、以下の説明において、同一構成要素には同一符号を付し繰り返しの説明を省略することがある。本発明は下記の実施の形態に限定されるものではなく、種々変更可能であることはいうまでもない。 Hereinafter, embodiments in which the present invention is applied to a power semiconductor module which is a semiconductor device will be described in detail with reference to the accompanying drawings. However, in the following description, the same components may be denoted by the same reference numerals and repeated description may be omitted. It goes without saying that the present invention is not limited to the following embodiments and can be variously modified.
　まず、添付の図１は、本発明の一実施の形態に係るパワー半導体モジュールの全体構成を示す断面図である。この図からも明らかなように、窒化アルミニウムの上下面にNiめっきを施したCu配線を有するセラミックス基板５上に、接合材料（例えば、高鉛半田、又は、Zn－Al、焼結Ag、Cu－Sn系金属間化合物）４により、半導体素子１(例えば、IGBT）及び半導体素子２（例えば、ダイオード)を接合し、半導体素子１及び半導体素子２を搭載したセラミックス基板５に対してワイヤボンディングを行いAlやCu等のワイヤ８を接続し、その後、半導体素子１及び半導体素子２が接合されたセラミックス基板５を、以下に詳細に示す半田（接合材料）３０により、ベース７上に接合した。更に、ベース７上に接合されたセラミックス基板５上のCu配線（即ち、Cuむくの基板）に、Cu端子３を超音波接合し、もって、パワー半導体モジュールとして作製したものである。半導体素子１及び半導体素子２はそれぞれパワー半導体素子ともいう。 First, FIG. 1 attached herewith is a cross-sectional view showing the overall configuration of a power semiconductor module according to an embodiment of the present invention. As is apparent from this figure, a bonding material (for example, high-lead solder, Zn-Al, sintered Ag, Cu, or the like) is formed on a ceramic substrate 5 having Cu wiring with Ni plating on the upper and lower surfaces of aluminum nitride. The semiconductor element 1 (for example, IGBT) and the semiconductor element 2 (for example, a diode) are joined by the Sn-based intermetallic compound) 4 and wire bonding is performed to the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted. Then, a wire 8 such as Al or Cu was connected, and then the ceramic substrate 5 to which the semiconductor element 1 and the semiconductor element 2 were bonded was bonded onto the base 7 with solder (bonding material) 30 described in detail below. Further, a Cu terminal 3 is ultrasonically bonded to a Cu wiring (that is, a Cu-uncoated substrate) on the ceramic substrate 5 bonded onto the base 7 to produce a power semiconductor module. The semiconductor element 1 and the semiconductor element 2 are also called power semiconductor elements.
　続いて、半導体素子１及び半導体素子２が接合されたセラミックス基板５をベース７に接合している半田３０について説明する。半田３０は、Sn－0～3.5Ag－3～10Cu－1～4Bi(mass％)の組成からなる（以下、「Sn－0～3.5Ag－3～10Cu－1～4Bi(mass％)半田」とも言う）。ここで、Sn－0～3.5Ag－3～10Cu－1～4Bi(mass％)半田とは、Snと、Snに対して、0～3.5(mass％)のAgと3～10(mass％)のCuと1～4(mass％)のBiと、を含む半田である。 Subsequently, the solder 30 that joins the ceramic substrate 5 to which the semiconductor element 1 and the semiconductor element 2 are joined to the base 7 will be described. The solder 30 has a composition of Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) (hereinafter, "Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder") Also called). Here, Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder is Sn and 0 to 3.5 (mass%) Ag and 3 to 10 (mass%) with respect to Sn. This is a solder containing Cu and 1 to 4 (mass%) Bi.
　半田３０を、－55℃⇔200℃の温度サイクルで試験した結果を、図２及び図３に示す。なお、これらの図における横軸は、半田３０のSn母相中に固溶するBi濃度を、その縦軸は、半田３０中のCu含有率を、それぞれ、示している。半田３０に含まれるBiは、全て、Sn母相中に固溶している。また、これらの図中の「○」は、温度サイクル試験において良好な信頼性が得られた組成を、「△」は界面反応破壊が主因で信頼性が得られなかった組成を、「×」は熱疲労破壊が主因で信頼性が得られなかった組成を示す。また、「□」は、界面反応破壊と熱疲労破壊が同程度に破壊の原因になった組成を示す。 The results of testing the solder 30 in a temperature cycle of −55 ° C. to 200 ° C. are shown in FIGS. In these drawings, the horizontal axis represents the Bi concentration dissolved in the Sn matrix of the solder 30, and the vertical axis represents the Cu content in the solder 30. All of Bi contained in the solder 30 is dissolved in the Sn matrix. In these figures, “◯” indicates a composition with good reliability in the temperature cycle test, “Δ” indicates a composition with no reliability due to interfacial reaction breakdown, and “×”. Indicates a composition whose reliability was not obtained mainly due to thermal fatigue failure. “□” indicates a composition in which interfacial reaction failure and thermal fatigue failure cause destruction to the same extent.
　図２及び図３から明らかなように、Ag含有率が0mass％（図２参照）と3.5mass％（図３参照）の結果が同等であり、このことから、結果は、Ag含有率により大きく左右されないと考えられる。但し、Agが3.5mass％より高くなると、コスト面でデメリットが大きくなると思われる。 As is clear from FIG. 2 and FIG. 3, the results of the Ag content rate of 0 mass% (see FIG. 2) and 3.5 mass% (see FIG. 3) are equivalent. It seems that it is not influenced. However, if Ag is higher than 3.5 mass%, it seems that the cost disadvantages increase.
　続いて、各成分の含有率について述べる。まず、Sn母相中のBi含有率について述べる。Sn母相中のBi含有率が1％未満の場合、熱疲労破壊を抑制できない。Sn母相中にBiを添加した場合、Sn母相が固溶強化される効果、高温化でのクリープ変形が容易になる効果により、熱疲労破壊を抑制することができる。 Subsequently, the content ratio of each component will be described. First, the Bi content in the Sn matrix will be described. If the Bi content in the Sn matrix is less than 1%, thermal fatigue failure cannot be suppressed. When Bi is added to the Sn matrix, thermal fatigue failure can be suppressed by the effect of solid solution strengthening of the Sn matrix and the effect of easy creep deformation at high temperatures.
　図４は、厚さ100μｍのSn－3Ag－0.5Cu(mass％)半田と、半田３０の組成範囲に含まれるSn－3Ag－0.5Cu－3Bi(mass％)半田を200℃で2MPaの荷重をかけてクリープ変形させた場合の写真である。図４（Ｂ）に示すSn－3Ag－0.5Cu－3Bi(mass％)半田の方が、図４（Ａ）に示すSn－3Ag－0.5Cu(mass％)半田より大きくクリープ変形することが分かる。この大きなクリープ変形は、Bi含有率が1～4mass％のときに得られる。Sn母相中のBi含有率が4％より高くなった場合、Cu含有率を高くしてもBiが接合界面に偏析しやすくなり、高温環境下における界面反応抑制効果が著しく低下する。 Fig. 4 shows a Sn-3Ag-0.5Cu (mass%) solder with a thickness of 100μm and a Sn-3Ag-0.5Cu-3Bi (mass%) solder included in the composition range of solder 30 at a load of 2MPa at 200 ° C. It is a photograph when it is made to creep-deform over. It can be seen that the Sn-3Ag-0.5Cu-3Bi (mass%) solder shown in FIG. 4 (B) creeps more greatly than the Sn-3Ag-0.5Cu (mass%) solder shown in FIG. 4 (A). . This large creep deformation is obtained when the Bi content is 1 to 4 mass%. When the Bi content in the Sn matrix is higher than 4%, even if the Cu content is increased, Bi tends to segregate at the bonding interface, and the interface reaction suppressing effect in a high temperature environment is significantly reduced.
　次に、Cu含有率について述べる。Cu含有率が3％未満の場合、高温環境下における界面反応抑制効果が著しく低下する。一方、Cu含有率が10％より高くなると、半田の固相線温度が高くなり接合が極めて困難になる。すなわち、Cu含有率10％が接合限界である。 Next, the Cu content will be described. When the Cu content is less than 3%, the interfacial reaction suppression effect in a high temperature environment is significantly reduced. On the other hand, if the Cu content is higher than 10%, the solidus temperature of the solder becomes high and joining becomes extremely difficult. That is, a Cu content of 10% is the joining limit.
　以上のことから、半田３０によれば、良好な接合信頼性が得られると言える。更に、下記においては、本発明の実施の形態の効果についての検討例を示す。 From the above, it can be said that according to the solder 30, good bonding reliability can be obtained. Further, in the following, an example of studying the effect of the embodiment of the present invention will be shown.
　次に、図５は、10mm□のインバー板を、厚さ100μｍの各種半田で、15mm□のCu板に接合したサンプルについて、－55℃⇔200℃の温度サイクル試験を行った結果である。なお、サンプル数（ｎ）はそれぞれ５個である。接合割合とは、温度サイクル試験を行った後の接合面積と温度サイクル試験を行う前（０サイクル）の接合との比率である。一般的に使用されるSn－3Ag－0.5Cu(mass％)半田の場合（グラフの最も下方の曲線Ａ）、500サイクル後には、熱疲労破壊及び接合界面破壊により、10％以下の接合割合（接合面積）になってしまった。 Next, FIG. 5 shows the results of a temperature cycle test of −55 ° C. to 200 ° C. for a sample in which a 10 mm square Invar plate is joined to a 15 mm square Cu plate with various solders having a thickness of 100 μm. Each sample number (n) is five. The bonding ratio is a ratio between the bonding area after the temperature cycle test and the bonding before the temperature cycle test (0 cycle). In the case of commonly used Sn-3Ag-0.5Cu (mass%) solder (curve A in the lowermost part of the graph), after 500 cycles, a joint ratio of 10% or less (due to thermal fatigue failure and joint interface failure) (Joining area).
　また、従来技術である特許文献１に記載された組成であるSn－3Ag－0.5Cu－5In(mass％)半田の場合（グラフの曲線Ｂ）、250サイクルまではある程度の信頼性を維持するが、500～750サイクル後には大きく接合面積が低下した。これは、試験初期の段階では、特許文献１に示すように、疲労破壊抑制の効果が発現しゆっくりと破壊が進むが、その後、図６に示すように、界面反応破壊が大きく進んだために破壊が加速したものである。なお、この図において、符号５はセラミックス基板を、符号１１はインバー板を、そして、符号２１は金属間化合物を示している。加えて、従来技術である特許文献２に記載のSn－7Cu半田の場合（グラフの曲線Ｃ）、界面反応を抑制できるが、熱疲労抑制ができないため、1000サイクル後にはほぼ全破断してしまう。 In the case of Sn-3Ag-0.5Cu-5In (mass%) solder having the composition described in Patent Document 1 which is the prior art (curve B in the graph), a certain level of reliability is maintained up to 250 cycles. After 500 to 750 cycles, the bonding area was greatly reduced. This is because, in the initial stage of the test, as shown in Patent Document 1, the effect of suppressing fatigue fracture is exhibited and the fracture progresses slowly, but then, as shown in FIG. Destruction is accelerated. In this figure, reference numeral 5 denotes a ceramic substrate, reference numeral 11 denotes an Invar plate, and reference numeral 21 denotes an intermetallic compound. In addition, in the case of the Sn-7Cu solder described in Patent Document 2, which is the prior art (curve C in the graph), the interface reaction can be suppressed, but since thermal fatigue cannot be suppressed, almost all fractures occur after 1000 cycles. .
　上述した従来技術に係る半田（グラフの曲線Ｂ、Ｃ）に対し、半田３０の組成範囲に含まれるSn－3Ag－7Cu－3Bi(mass％)半田の場合（グラフの曲線Ｄ）、図５からも明らかなように、接合面積が大きく低下しないので、接合部の界面反応破壊と熱疲労破壊の両方を抑制することができる。 In the case of Sn-3Ag-7Cu-3Bi (mass%) solder included in the composition range of the solder 30 (curve D in the graph), compared to the above-described conventional solder (curve B, C in the graph), from FIG. As is clear, since the bonding area does not decrease greatly, it is possible to suppress both interfacial reaction breakdown and thermal fatigue breakdown of the bonded portion.
　加えて、上述した従来のSn－3Ag－0.5Cu－5In(mass％)半田におけるCu含有率を高めたSn－3Ag－7Cu－5In(mass％)半田について、200℃高温保持試験を行い、界面反応抑制効果を付与できないかの確認を行った。即ち、Sn－3Ag－7Cu－5In(mass％)半田を200℃で500h保持したときの結果を図７（Ｂ）に示しており、他方、半田３０の組成範囲に含まれるSn－3Ag－7Cu－3Bi(mass％)半田についての結果を図７（Ａ）に示す。その結果、これらの断面写真からも明らかなように、Sn－3Ag－7Cu－5In(mass％)半田の組成では、十分な接合信頼性が得られないということが分かった。なお、ここでも、符号５はセラミックス基板を、符号１１はインバー板を、そして、符号２１は金属間化合物を示している。 In addition, a high temperature holding test at 200 ° C was conducted on Sn-3Ag-7Cu-5In (mass%) solder with an increased Cu content in the conventional Sn-3Ag-0.5Cu-5In (mass%) solder described above, and the interface It was confirmed whether the reaction inhibitory effect could not be imparted. That is, the result when the Sn-3Ag-7Cu-5In (mass%) solder is held at 200 ° C. for 500 hours is shown in FIG. 7B, while the Sn-3Ag-7Cu contained in the composition range of the solder 30 is shown. The results for −3 Bi (mass%) solder are shown in FIG. As a result, as is clear from these cross-sectional photographs, it was found that the Sn-3Ag-7Cu-5In (mass%) solder composition cannot provide sufficient joint reliability. Here again, reference numeral 5 denotes a ceramic substrate, reference numeral 11 denotes an Invar plate, and reference numeral 21 denotes an intermetallic compound.
　更に、本発明の他の実施の形態に係るパワー半導体モジュールでは、例えば、添付の図８に示すように、半導体素子３１（例えば、IGBT１又はダイオード２）の上面及び下面電極を、上述した半田３０で、リードフレーム（上側リードおよび下側リード）９に接合している。半導体素子３１とリードフレーム９との各接合部の周囲をハードレジンで封止することが好ましい。半導体素子３１はパワー半導体素子ともいう。 Furthermore, in a power semiconductor module according to another embodiment of the present invention, for example, as shown in attached FIG. 8, the upper and lower electrodes of the semiconductor element 31 (for example, the IGBT 1 or the diode 2) are connected to the solder 30 described above. Thus, the lead frame (upper lead and lower lead) 9 is joined. It is preferable to seal the periphery of each joint between the semiconductor element 31 and the lead frame 9 with a hard resin. The semiconductor element 31 is also called a power semiconductor element.
　このように、半導体素子３１の上下面を、半田３０でリードフレーム９に接合することによれば、放熱性に優れたパワー半導体モジュールを提供することが可能となる。加えて、各接合部の周囲を、例えば、トランスファーモールドにより、所謂、レジン封止することによれば、接合部における歪みを小さく抑えることが可能となり、もって、パワー半導体モジュールの寿命を向上することができる。このとき、レジンの熱膨張率は、10ppm/K以上であることが望ましい。なお、レジンの熱膨張率が10ppm/k未満の場合、接合部の熱衝撃によるクラック進展抑制効果が小さくなる。そして、半田３０を用いることによれば、上述と同じ理由により、高温信頼性を得ることができる。 Thus, by joining the upper and lower surfaces of the semiconductor element 31 to the lead frame 9 with the solder 30, it is possible to provide a power semiconductor module with excellent heat dissipation. In addition, by so-called resin-sealing the periphery of each joint, for example, by transfer molding, it becomes possible to suppress distortion at the joint, thereby improving the life of the power semiconductor module. Can do. At this time, the thermal expansion coefficient of the resin is desirably 10 ppm / K or more. In addition, when the thermal expansion coefficient of the resin is less than 10 ppm / k, the effect of suppressing the progress of cracks due to the thermal shock of the joint portion is reduced. By using the solder 30, high temperature reliability can be obtained for the same reason as described above.
　また、更に、本発明の実施の形態の第１の変形例に係るパワー半導体モジュールでは、半導体素子が接合されたセラミックス基板５を、半田３０にSiを加えたSn－0～3.5Ag－5～10Cu－1～4Bi－0.001～0.1Si(mass％)半田（以下、半田３０Ａという。）により、ベース７に接合している。また、他の実施の形態の半導体素子３１を半田３０Ａにより、リードフレーム９に接合してもよい。 Furthermore, in the power semiconductor module according to the first modification of the embodiment of the present invention, the ceramic substrate 5 to which the semiconductor element is bonded is connected to Sn-0 to 3.5Ag-5 to which Si is added to the solder 30. Bonded to the base 7 by 10Cu-1 to 4Bi-0.001 to 0.1Si (mass%) solder (hereinafter referred to as solder 30A). Further, the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30A.
　このように、半田３０に0.001～0.1Si(mass％)を添加することによれば、Sn母相中に微細なCu－Si化合物などの析出物が分散して析出する。これにより、半田を強化して熱疲労耐性を向上することができる。Si含有率が0.001％未満の場合、十分に半田を強化できない。また、Si含有率が0.1％より高くなると、接合時に半田表面に形成したSi酸化物が濡れを阻害するため、良好な接合ができなくなる。 Thus, by adding 0.001 to 0.1 Si (mass%) to the solder 30, fine precipitates such as Cu—Si compounds are dispersed and precipitated in the Sn matrix. Thereby, solder can be strengthened and thermal fatigue resistance can be improved. When the Si content is less than 0.001%, the solder cannot be sufficiently strengthened. On the other hand, when the Si content is higher than 0.1%, the Si oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
　本発明の実施の形態の第２の変形例に係るパワー半導体モジュールでは、半導体素子が接合されたセラミックス基板５を、半田３０Ａに代えて、Sn－0～3.5Ag－5～10Cu－1～4Bi－0.001～0.1Ti(mass％)半田（以下、半田３０Ｂという。）により、ベース７に接合してもよい。また、他の実施の形態の半導体素子３１を半田３０Ｂにより、リードフレーム９に接合してもよい。 In the power semiconductor module according to the second modification of the embodiment of the present invention, Sn-0 to 3.5Ag-5 to 10Cu-1 to 4Bi are substituted for the ceramic substrate 5 to which the semiconductor element is bonded instead of the solder 30A. It may be joined to the base 7 by -0.001 to 0.1 Ti (mass%) solder (hereinafter referred to as solder 30B). Further, the semiconductor element 31 according to another embodiment may be joined to the lead frame 9 by the solder 30B.
　このように、半田３０に0.001～0.1Ti(mass％)を添加することによれば、第１の変形例の半田３０Ａと同様に、Sn母相中に微細なCu－Si化合物などの析出物が分散して析出する。これにより、半田を強化して熱疲労耐性を向上することができる。Ti含有率が0.001％未満の場合、十分に半田を強化できない。また、Ti含有率が0.1％より高くなると、接合時に半田表面に形成したTi酸化物が濡れを阻害するため、良好な接合ができなくなる。 In this way, by adding 0.001 to 0.1 Ti (mass%) to the solder 30, as in the solder 30A of the first modification, precipitates such as fine Cu-Si compounds in the Sn matrix. Are dispersed and precipitated. Thereby, solder can be strengthened and thermal fatigue resistance can be improved. If the Ti content is less than 0.001%, the solder cannot be strengthened sufficiently. On the other hand, if the Ti content is higher than 0.1%, the Ti oxide formed on the solder surface at the time of bonding inhibits the wetting, so that good bonding cannot be performed.
　更に、半田３０の組成のうち、そのCu組成を5～10(mass％)として、所謂、Sn－0～3.5Ag－5～10Cu－1～4Bi(mass％)半田とすることが好ましい。 Furthermore, it is preferable that the solder composition is a so-called Sn-0 to 3.5Ag-5 to 10Cu-1 to 4Bi (mass%) solder with a Cu composition of 5 to 10 (mass%).
　半田の組成をSn－0～3.5Ag－5～10Cu－1～4Bi(mass％)とすることによれば、特に、高温下における界面反応抑制効果を、高めることができる。ここで、図９に、Sn系半田でNiめっき部材を接合したサンプルについて、200℃で保持したときのNiめっき消失厚さの関係を示す。これから、Cu含有率が3mass％以上で効果が現れるが、特に、5mass％以上の場合、反応抑制効果が極めて大きくなることが分かる。 By setting the solder composition to Sn-0 to 3.5Ag-5 to 10Cu-1 to 4Bi (mass%), the interfacial reaction suppressing effect can be enhanced particularly at high temperatures. Here, FIG. 9 shows the relationship of the Ni plating disappearance thickness when the Ni plated member is joined with Sn-based solder and held at 200 ° C. FIG. From this, it can be seen that the effect appears when the Cu content is 3 mass% or more, but in particular, when the Cu content is 5 mass% or more, the reaction suppressing effect becomes extremely large.
　また、図１に示した実施の形態に係るパワー半導体モジュール又は図８に示した他の実施の形態に係るパワー半導体モジュールの構成において、セラミックス基板５として、Ni系めっきを施した配線を有するセラミックス基板とし、又は、リードフレーム９として、Ni系めっきを施した配線を有するリードフレームとしている。 Further, in the configuration of the power semiconductor module according to the embodiment shown in FIG. 1 or the power semiconductor module according to another embodiment shown in FIG. 8, ceramics having a Ni-plated wiring as the ceramic substrate 5. The substrate or the lead frame 9 is a lead frame having a Ni-plated wiring.
　このように、Ni系めっきを施した配線を有するセラミックス基板５又はリードフレーム９を、半田３０又は半田３０Ａ又は半田３０Ｂで接合することによれば、Ni系めっき上にCu－Sn系化合物が選択的に析出し、これが高温下での界面反応を抑制する拡散バリアとして機能するため、高い高温信頼性が得られる。このとき、Ni系めっきの厚さが0.2μｍ以上が望ましい。Ni系めっきの厚さが0.2μｍ未満の場合、Ni系めっき適用の効果が失われるという恐れがある。 As described above, by bonding the ceramic substrate 5 or the lead frame 9 having the Ni-plated wiring with the solder 30 or the solder 30A or the solder 30B, the Cu—Sn compound is selected on the Ni-based plating. Since this precipitates and functions as a diffusion barrier that suppresses interfacial reactions at high temperatures, high high temperature reliability can be obtained. At this time, the thickness of the Ni-based plating is desirably 0.2 μm or more. If the thickness of the Ni plating is less than 0.2 μm, the effect of applying the Ni plating may be lost.
　この場合、特に、半田３０又は半田３０Ａ又は半田３０Ｂによる接合部の厚さが、50～500μｍであることが好ましい。 In this case, it is particularly preferable that the thickness of the joint portion by the solder 30 or the solder 30A or the solder 30B is 50 to 500 μm.
　これは、接合部の厚さが50μｍ未満になると、応力緩衝能が低下し接合信頼性が得られなくなる恐れがあり、また、接合時にNi系めっき上に選択的に形成されるCu－Sn系化合物の厚さが薄くなり拡散バリアの効果が得られにくくなることによる。他方、接合部の厚さが500μｍより厚い場合、半田の接合界面ではなく、半田中に含まれるCu－Sn化合物が接合部内部で浮島状に存在する割合が増え、接合信頼性の低下に繋がる恐れがある。 This is because if the thickness of the joint is less than 50 μm, the stress buffering ability may be reduced and the joint reliability may not be obtained, and the Cu—Sn system that is selectively formed on the Ni-based plating at the time of joining. This is because the thickness of the compound is reduced and it becomes difficult to obtain the effect of the diffusion barrier. On the other hand, when the thickness of the joint is greater than 500 μm, the proportion of the Cu—Sn compound contained in the solder in the form of floating islands increases in the joint, not in the solder joint interface, leading to a decrease in joint reliability. There is a fear.
　また、上述したパワー半導体モジュールの構成において、半導体素子１、半導体素子２及び半導体素子３１として、それぞれSiC又はGaNを用いることが好ましい。 In the configuration of the power semiconductor module described above, it is preferable to use SiC or GaN as the semiconductor element 1, the semiconductor element 2, and the semiconductor element 31, respectively.
　これは、半導体素子１、半導体素子２及び半導体素子３１としてSiC又はGaNを用いた場合、パワー半導体モジュールの損失を低減することができることによる。また、高温下で動作可能なため、インバータの冷却設備を簡略化して、装置全体の小型・軽量化を可能にする。セラミックス基板下の接合部（セラミックス基板接合部）は、200℃程度まで高温化するが、しかしながら、上述した半田３０又は半田３０Ａ又は半田３０Ｂにより、所望の信頼性が得られる。 This is because, when SiC or GaN is used as the semiconductor element 1, the semiconductor element 2, and the semiconductor element 31, the loss of the power semiconductor module can be reduced. In addition, since it can operate at high temperatures, the cooling equipment for the inverter is simplified, and the entire device can be made smaller and lighter. The joint portion (ceramic substrate joint portion) under the ceramic substrate is heated to about 200 ° C. However, desired reliability can be obtained by the solder 30 or the solder 30A or the solder 30B described above.
　また、上述したパワー半導体モジュールの構成において、半導体素子１及び半導体素子２を、Zn－Alで、セラミックス基板に接合することが望ましい。 In the configuration of the power semiconductor module described above, it is preferable that the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate with Zn-Al.
　これは、Zn－Alの融点は約380℃であるため、半導体素子１及び半導体素子２を搭載したセラミックス基板５を380℃より低い温度でベース７に接合すれば、半導体素子１及び半導体素子２とセラミックス基板とのそれぞれの接合部（半導体素子接合部）を再溶融させること無く接合することができることによる。半田３０又は半田３０Ａ又は半田３０Ｂは約200℃で溶融するが、ボイドや未濡れが無い良好な接合を得るためには接合温度が高い方が有利である。半導体素子接合部にZn－Alを用いることで、接合マージンを確保できる。また、従来の高鉛半田に比べて、熱衝撃に伴う亀裂進展が遅いため、接続信頼性を向上することができる。 This is because the melting point of Zn—Al is about 380 ° C., and therefore, if the ceramic substrate 5 on which the semiconductor elements 1 and 2 are mounted is bonded to the base 7 at a temperature lower than 380 ° C., the semiconductor elements 1 and 2 It is because it can join, without remelting each junction part (semiconductor element junction part) of a ceramic substrate. The solder 30 or the solder 30A or the solder 30B melts at about 200 ° C. However, it is advantageous that the bonding temperature is higher in order to obtain a good bonding without voids or unwetting. By using Zn—Al for the semiconductor element junction, a junction margin can be secured. Moreover, since the crack growth accompanying a thermal shock is slow compared with the conventional high lead solder, connection reliability can be improved.
　また、上述したパワー半導体モジュールの構成において、半導体素子１及び半導体素子２を、焼結Agで、セラミックス基板５に接合することが好ましい。 In the configuration of the power semiconductor module described above, it is preferable that the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with sintered Ag.
　これは、焼結Agの融点は約900℃であるため、半導体素子１及び半導体素子２を搭載したセラミックス基板５を900℃より低い温度でベース７に接合すれば、半導体素子接合部を再溶融させること無く接合することができることによる。半田３０又は半田３０Ａ又は半田３０Ｂは約200℃で溶融するが、ボイドや未濡れが無い良好な接合を得るためには、接合温度が高い方が有利である。半導体素子接合部に焼結Agを用いることにより、接合マージンを確保できる。また、従来の高鉛半田に比べ、熱衝撃に伴う亀裂進展が遅いため、接続信頼性を向上することができる。 This is because the melting point of sintered Ag is about 900 ° C., and if the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 at a temperature lower than 900 ° C., the semiconductor element junction is remelted. It is because it can join without making it. The solder 30 or the solder 30A or the solder 30B melts at about 200 ° C. However, in order to obtain a good joint free from voids and unwetting, it is advantageous that the joint temperature is higher. A bonding margin can be secured by using sintered Ag for the semiconductor element bonding portion. Moreover, since the crack growth accompanying a thermal shock is slow compared with the conventional high lead solder, connection reliability can be improved.
　また、上述したパワー半導体モジュールの構成において、半導体素子１及び半導体素子２を、Cu－Sn系金属間化合物により、セラミックス基板５に接合することが好ましい。 In the configuration of the power semiconductor module described above, it is preferable that the semiconductor element 1 and the semiconductor element 2 are bonded to the ceramic substrate 5 with a Cu—Sn intermetallic compound.
　これは、Cu－Sn系金属間化合物で接合した場合、融点は400℃以上であるため、半導体素子１及び半導体素子２を搭載したセラミックス基板５を400℃より低い温度で接合すれば、半導体素子接合部を再溶融させること無く接合することができることによる。半田３０又は半田３０Ａ又は半田３０Ｂは約200℃で溶融するが、ボイドや未濡れが無い良好な接合を得るためには、接合温度が高い方が有利である。半導体素子接合部にCu－Sn系化合物を用いることで、接合マージンを確保できる。また、従来の高鉛半田に比べ、熱衝撃に伴う亀裂進展が遅いため、接続信頼性を向上することができる。 This is because the melting point is 400 ° C. or higher when bonded with a Cu—Sn based intermetallic compound, so if the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded at a temperature lower than 400 ° C., the semiconductor element It is because it can join, without remelting a junction part. The solder 30 or the solder 30A or the solder 30B melts at about 200 ° C. However, in order to obtain a good joint free from voids and unwetting, it is advantageous that the joint temperature is higher. By using a Cu-Sn compound for the semiconductor element junction, a junction margin can be secured. Moreover, since the crack growth accompanying a thermal shock is slow compared with the conventional high lead solder, connection reliability can be improved.
　更に、半導体素子１及び半導体素子２をセラミックス基板５に接合した後、水素又は蟻酸による還元雰囲気において、半田３０又は半田３０Ａ又は半田３０Ｂを用いて、セラミックス基板５をベース７に接合することが好ましい。また、水素又は蟻酸による還元雰囲気において、半導体素子３１をリードフレーム９に接合することが好ましい。 Further, after bonding the semiconductor element 1 and the semiconductor element 2 to the ceramic substrate 5, it is preferable to bond the ceramic substrate 5 to the base 7 using the solder 30, the solder 30A, or the solder 30B in a reducing atmosphere with hydrogen or formic acid. . Further, it is preferable to join the semiconductor element 31 to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid.
　これは、半導体素子１及び半導体素子２を搭載したセラミックス基板５を水素又は蟻酸による還元雰囲気でベース７に接合することで、又は半導体素子３１を水素又は蟻酸による還元雰囲気でリードフレーム９に接合することで、半田３０又は半田３０Ａ又は半田３０Ｂが良好に部材に濡れ、ボイドや未濡れの少ない接合が得られることによる。ボイドや未濡れが少ない接合を得ることにより、高温信頼性確保を容易にする。 This is because the ceramic substrate 5 on which the semiconductor element 1 and the semiconductor element 2 are mounted is bonded to the base 7 in a reducing atmosphere with hydrogen or formic acid, or the semiconductor element 31 is bonded to the lead frame 9 in a reducing atmosphere with hydrogen or formic acid. This is because the solder 30 or the solder 30A or the solder 30B is satisfactorily wetted by the member, and a joining with less voids and non-wetting is obtained. It is easy to ensure high temperature reliability by obtaining joints with less voids and non-wetting.
　そして、上記において、最高温度が250～350℃で半田３０又は半田３０Ａ又は半田３０Ｂを用いて、セラミックス基板５をベース７に、又は、半導体素子３１をリードフレーム９に接合することが好ましい。 In the above, it is preferable to bond the ceramic substrate 5 to the base 7 or the semiconductor element 31 to the lead frame 9 using the solder 30 or the solder 30A or the solder 30B at a maximum temperature of 250 to 350 ° C.
　これは、半田３０又は半田３０Ａ又は半田３０Ｂの接合温度を、最高温度が250～350℃で接合することにより、耐熱性の高い接合部が得られることによる。250℃より低い場合、半田３０又は半田３０Ａ又は半田３０Ｂの濡れが低下し、ボイドや未濡れが発生しやすくなり、信頼性を損なう恐れがある。一方、350℃より高温になると、半田３０又は半田３０Ａ又は半田３０Ｂが溶融している際、セラミックス基板やリードフレーム（部材）との反応が進み過ぎて、部材のNi系めっきが食われ、高温環境下で信頼性を維持するためのバリア効果が低減する恐れがある。 This is because a joint with high heat resistance can be obtained by joining the solder 30 or 30A or 30B at a maximum temperature of 250 to 350 ° C. When the temperature is lower than 250 ° C., the wetness of the solder 30 or the solder 30A or the solder 30B is reduced, and voids or non-wetting is likely to occur, which may impair reliability. On the other hand, when the temperature is higher than 350 ° C., when the solder 30 or the solder 30A or the solder 30B is melted, the reaction with the ceramic substrate or the lead frame (member) progresses too much, and the Ni-based plating of the member is eaten. There is a risk that the barrier effect for maintaining reliability in the environment may be reduced.
　続いて、上述した半田３０を用いたパワー半導体モジュールについての具体的な実施例について、以下に説明する。
（実施例１～１１） Subsequently, specific examples of the power semiconductor module using the solder 30 described above will be described below.
(Examples 1 to 11)
　まず、図１に示した構造の半導体モジュールに適用した実施例について、以下説明する。実施例１～１１について、表１に示す。即ち、表１に示した基板下接合材料（セラミックス基板接合部の半田）、素子接合材料（半導体素子接合部の接合材）により製造したパワー半導体モジュールについて、－55℃⇔200℃の温度サイクル試験を1000サイクルまで行い、セラミックス基板接合部のクラックがチップ直下まで達した場合に判定を「×」とし、セラミックス基板接合部のクラックがチップ直下まで達しなかった場合に判定を「○」とした。また、200℃1000hの高温保持試験を行い、セラミックス基板接合部の20％以上破壊が生じた場合に判定を「×」とし、セラミックス基板接合部の20％以上破壊が生じなかった場合に判定を「○」とした。その結果は、表１にも示すように、何れの実施例においても、温度サイクル試験、高温保持試験で良好な接合信頼性が得られた。 First, an embodiment applied to the semiconductor module having the structure shown in FIG. 1 will be described below. Examples 1 to 11 are shown in Table 1. That is, a temperature cycle test of −55 ° C. to 200 ° C. for a power semiconductor module manufactured using the bonding material under substrate (solder for ceramic substrate bonding) and element bonding material (bonding material for semiconductor element bonding) shown in Table 1 The determination was made “x” when the crack in the ceramic substrate joint reached just below the chip, and the judgment was made “good” when the crack in the ceramic substrate joint did not reach just below the chip. In addition, a high temperature holding test at 200 ° C for 1000 hours was conducted, and the judgment was "X" when 20% or more of the ceramic substrate joint was broken, and the judgment was made when 20% or more of the ceramic substrate joint was not broken. “○”. As a result, as shown in Table 1, in any of the examples, good bonding reliability was obtained in the temperature cycle test and the high temperature holding test.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
（比較例１～５）
　上記の実施例1～１１と同じ工程で、同じ形状のパワー半導体モジュールを作製した。セラミックス基板の接合に用いた半田（基板下接合材料）を、表２に示す。比較例１～３の何れの半田を用いた場合にも、温度サイクル試験において、セラミックス基板接合部のクラックがチップ直下に達した。また、高温保持試験においても、比較例１～４では、何れも、接合部の20％以上が界面破壊により破壊した。唯一、比較例５のSn－7Cuのみ、高温保持試験において良好な信頼性が得られた。即ち、これら比較例１～５において、温度サイクル試験と高温保持試験の両方で良好な信頼性が得られるものは無かった。 (Comparative Examples 1 to 5)
A power semiconductor module having the same shape was manufactured through the same steps as those in Examples 1 to 11 described above. Table 2 shows the solder (bonding material under the substrate) used for bonding the ceramic substrates. When any of the solders of Comparative Examples 1 to 3 was used, the crack in the ceramic substrate joint reached just below the chip in the temperature cycle test. In the high temperature holding test, in Comparative Examples 1 to 4, 20% or more of the joints were broken due to interface fracture. Only Sn-7Cu of Comparative Example 5 had good reliability in the high temperature holding test. In other words, none of these Comparative Examples 1 to 5 could obtain good reliability in both the temperature cycle test and the high temperature holding test.
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
（実施例１２～２２）
　更に、半田３０を、上記図８にその構造を示したパワー半導体モジュールに適用した実施例について、以下に説明する。 (Examples 12 to 22)
Further, an embodiment in which the solder 30 is applied to the power semiconductor module whose structure is shown in FIG. 8 will be described below.
　即ち、Niめっきを施したCu製リードフレーム９上に、半田３０で半導体素子３１を接合し、パワー半導体モジュールを作製した。実施例１２～２２の半導体素子の接合に用いた半田（接合材料）を表３に示す。 That is, a power semiconductor module was manufactured by joining a semiconductor element 31 with solder 30 on a Cu lead frame 9 plated with Ni. Table 3 shows solders (joining materials) used for joining the semiconductor elements of Examples 12 to 22.
　これらのパワー半導体モジュールについて、－55℃⇔200℃の温度サイクル試験を1000サイクルまで行い、半導体素子接合部の20％までクラックが達した場合に判定を「×」とし、半導体素子接合部の20％までクラックが達しなかった場合に判定を「○」とした。また、200℃1000hの高温保持試験を行い、半導体素子接合部の20％以上破壊が生じた場合に判定を「×」とし、半導体素子接合部の20％以上破壊が生じなかった場合に判定を「○」とした。その結果は、表３に示すように、何れの実施例においても、温度サイクル試験、高温保持試験で良好な接合信頼性が得られた。 For these power semiconductor modules, a temperature cycle test of -55 ° C to 200 ° C was conducted up to 1000 cycles, and when the crack reached 20% of the semiconductor element junction, the judgment was “x”, and the semiconductor element junction 20 When the crack did not reach to%, the judgment was “◯”. In addition, a high temperature holding test at 200 ° C. for 1000 hours is performed, and the determination is “X” when 20% or more of the semiconductor element junction is broken, and the determination is made when 20% or more of the semiconductor element junction is not broken. “○”. As a result, as shown in Table 3, in any of the examples, good bonding reliability was obtained in the temperature cycle test and the high temperature holding test.
（比較例６～１０）
　上記の実施例１２～２２と同じ工程で、同じ形状のパワー半導体モジュールを作製した。半導体素子の接合に用いた半田（接合材料）を、表４に示す。比較例６～１０の何れの半田を用いた場合にも、温度サイクル試験において、半導体素子接合部のクラックがチップ直下に達した。また、高温保持試験においても、表４の比較例６～９では、何れも、半導体素子接合部の20％以上が界面破壊により破壊した。唯一、比較例１０のSn－7Cuのみ高温保持試験において良好な信頼性が得られた。即ち、比較例６～１０において、温度サイクル試験と高温保持試験の両方で良好な信頼性が得られるものは無かった。 (Comparative Examples 6 to 10)
A power semiconductor module having the same shape was fabricated by the same process as in Examples 12 to 22 above. Table 4 shows the solder (joining material) used for joining the semiconductor elements. When any of the solders of Comparative Examples 6 to 10 was used, in the temperature cycle test, the crack at the semiconductor element junction reached just below the chip. Also in the high temperature holding test, in Comparative Examples 6 to 9 in Table 4, 20% or more of the semiconductor element junctions were broken due to the interface failure. Only Sn-7Cu of Comparative Example 10 had good reliability in the high temperature holding test. That is, in Comparative Examples 6 to 10, none of the temperature cycle test and the high temperature holding test yielded good reliability.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000004
Figure JPOXMLDOC01-appb-T000004
　１…半導体素子（IGBT）、２…半導体素子（ダイオード）、３…Cu端子、４…接合材料、５…セラミックス基板、７…ベース、８…ワイヤ、９…リードフレーム、１１…インバー板、２１…金属間化合物、３０…Sn－0～3.5Ag－3～10Cu－1～4Bi(mass％)半田、３１…半導体素子 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element (IGBT), 2 ... Semiconductor element (diode), 3 ... Cu terminal, 4 ... Bonding material, 5 ... Ceramic substrate, 7 ... Base, 8 ... Wire, 9 ... Lead frame, 11 ... Invar plate, 21 ... Intermetallic compound, 30 ... Sn-0 to 3.5Ag-3 to 10Cu-1 to 4Bi (mass%) solder, 31 ... Semiconductor element

Claims (17)

  1. 　パワー半導体素子を搭載したセラミックス基板とベースとを備え、又は、パワー半導体素子とリードフレームとを備える半導体装置であって、
    　前記セラミックス基板と前記ベースとは接合材料で接合して構成され、又は前記パワー半導体素子と前記リードフレームとは接合材料で接合して構成され、
    　前記接合材料は、Snと、前記Snに対して、0～3.5(mass％)のAgと3～10(mass％)のCuと1～4 (mass％)のBiを含む。     A semiconductor device comprising a ceramic substrate and a base on which a power semiconductor element is mounted, or comprising a power semiconductor element and a lead frame,
    The ceramic substrate and the base are configured by bonding with a bonding material, or the power semiconductor element and the lead frame are configured by bonding with a bonding material,
    The bonding material contains Sn, 0 to 3.5 (mass%) Ag, 3 to 10 (mass%) Cu, and 1 to 4 (mass%) Bi with respect to the Sn.
  2. 　請求項１の半導体装置において、前記リードフレームは第１および第２のリードを有し、前記パワー半導体素子は上面及び下面電極を有し、前記上面電極と前記第１のリードとの間に前記接合材料で第１の接合部が構成され、前記下面電極と前記第２のリードとの間に前記接合材料で第２の接合部が構成され、前記第１の接合部および第２の接合部の周囲はハードレジンで封止されている。 2. The semiconductor device according to claim 1, wherein the lead frame includes first and second leads, the power semiconductor element includes an upper surface and a lower surface electrode, and the power semiconductor element is disposed between the upper surface electrode and the first lead. A first bonding portion is formed of a bonding material, and a second bonding portion is formed of the bonding material between the lower surface electrode and the second lead, and the first bonding portion and the second bonding portion. Is sealed with a hard resin.
  3. 　請求項１の半導体装置において、前記接合材料は、さらに、0.001～0.1Si(mass％)を含む。 2. The semiconductor device according to claim 1, wherein the bonding material further includes 0.001 to 0.1 Si (mass%).
  4. 　前記請求項１に記載した半導体装置において、前記接合材料は、さらに、0.001～0.1Ti(mass％)を含む。 In the semiconductor device according to claim 1, the bonding material further includes 0.001 to 0.1 Ti (mass%).
  5. 　請求項１又は２の半導体装置において、前記接合材料の前記Cuは5～10(mass％)である。 3. The semiconductor device according to claim 1, wherein the Cu of the bonding material is 5 to 10 (mass%).
  6. 　請求項１の半導体装置において、前記セラミックス基板および前記リードフレームは、Ni系めっきを施した配線を有している。 2. The semiconductor device according to claim 1, wherein the ceramic substrate and the lead frame have wiring plated with Ni.
  7. 　請求項６の半導体装置において、前記接合材料で構成される接合部の厚さが50～500μmである。 7. The semiconductor device according to claim 6, wherein a thickness of the joint portion made of the joining material is 50 to 500 μm.
  8. 　請求項１の半導体装置において、前記パワー半導体素子として、SiCまたはGaNを用いる。 2. The semiconductor device according to claim 1, wherein SiC or GaN is used as the power semiconductor element.
  9. 　請求項１の半導体装置において、前記パワー半導体素子と前記セラミックス基板とを接合する接合材料は、Zn－Alを含む。 2. The semiconductor device according to claim 1, wherein a bonding material for bonding the power semiconductor element and the ceramic substrate contains Zn—Al.
  10. 　請求項１の半導体装置において、前記パワー半導体素子と前記セラミックス基板を接合する接合材料は、焼結Agを含む。 2. The semiconductor device according to claim 1, wherein a bonding material for bonding the power semiconductor element and the ceramic substrate includes sintered Ag.
  11. 　請求項１の半導体装置において、前記パワー半導体素子と前記セラミックス基板を接合する接合材料は、Cu－Sn系金属間化合物を含む。 2. The semiconductor device according to claim 1, wherein a bonding material for bonding the power semiconductor element and the ceramic substrate contains a Cu—Sn intermetallic compound.
  12. 　半導体装置の製造方法は、
    　（ａ）パワー半導体素子を搭載したセラミックス基板上をベースに半田で接合する工程、又は、（ｂ）パワー半導体素子をリードフレームに半田で接合する工程を備え、
    　前記半田は、Snと、前記Snに対して、0～3.5(mass％)のAgと3～10(mass％)のCuと1～4(mass％)のBiを含む。     The manufacturing method of the semiconductor device is as follows:
    (A) a step of joining a ceramic substrate on which a power semiconductor element is mounted with a solder to a base, or (b) a step of joining the power semiconductor element to a lead frame with a solder,
    The solder contains Sn, 0 to 3.5 (mass%) Ag, 3 to 10 (mass%) Cu, and 1 to 4 (mass%) Bi with respect to the Sn.
  13. 　請求項１２の半導体装置の製造方法において、前記（ａ）工程および前記（ｂ）工程の接合は水素または蟻酸による還元雰囲気で行われる。 13. The method of manufacturing a semiconductor device according to claim 12, wherein the joining in the step (a) and the step (b) is performed in a reducing atmosphere with hydrogen or formic acid.
  14. 　請求項１２の半導体装置の製造方法において、前記（ａ）工程および前記（ｂ）工程で行われる接合の最高温度は250～350℃である。 13. In the method of manufacturing a semiconductor device according to claim 12, the maximum temperature of bonding performed in the step (a) and the step (b) is 250 to 350.degree.
  15. 　パワー半導体素子を搭載したセラミックス基板上をベースに接合し、又は、パワー半導体素子をリードフレームに接合して製造される半導体装置を製造するための半田は、Snと、前記Snに対して、0～3.5(mass％)のAg、3～10(mass％)のCu、1～4(mass％)のBiを含む。 Solder for manufacturing a semiconductor device manufactured by bonding a ceramic substrate on which a power semiconductor element is mounted to a base, or bonding a power semiconductor element to a lead frame is Sn and 0 with respect to the Sn. -3.5 (mass%) Ag, 3-10 (mass%) Cu, 1-4 (mass%) Bi.
  16. 　請求項１５の半導体装置を製造するための半田は、前記Cuを5～10(mass％)含む。 The solder for manufacturing the semiconductor device according to claim 15 includes 5 to 10 (mass%) of Cu.
  17. 　請求項１６の半導体装置を製造するための半田は、更に、Siを0.001～0.1(mass％)含む。 The solder for manufacturing the semiconductor device according to claim 16 further contains 0.001 to 0.1 (mass%) of Si.
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