WO2015018721A1 - Circuit électronique de puissance présentant un contact électrique planaire - Google Patents

Circuit électronique de puissance présentant un contact électrique planaire Download PDF

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Publication number
WO2015018721A1
WO2015018721A1 PCT/EP2014/066417 EP2014066417W WO2015018721A1 WO 2015018721 A1 WO2015018721 A1 WO 2015018721A1 EP 2014066417 W EP2014066417 W EP 2014066417W WO 2015018721 A1 WO2015018721 A1 WO 2015018721A1
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WO
WIPO (PCT)
Prior art keywords
power electronic
electronic circuit
layer
substrate
buffer layer
Prior art date
Application number
PCT/EP2014/066417
Other languages
German (de)
English (en)
Inventor
Gerhard Mitic
Karl Weidner
Stefan Kiefl
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO2015018721A1 publication Critical patent/WO2015018721A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399—Material
    • H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]

Definitions

  • the invention relates to a power electronic circuit with planar electrical contacting, comprising a substrate, at least one arranged on the substrate examelek ⁇ tronic component, the substrate and the power electronic device at least in part covering electrically insulating layer and at least one elec ⁇ trically insulating Layer comprises at least partially covering metal layer. Electrical failure of IGBT modules releases significant thermal energy before the module shuts down or a permanent short circuit occurs. This thermal energy may then lead to the destruction of the materials, which are then thrown away with high energy, which has the character of an explosion.
  • a partially covering electrically insulating layer is applied on the substrate and the power electronic component.
  • This layer may be for example a isolie ⁇ Rende film, particularly a polyimide film.
  • the film comprises windows, ie, holes, in the area of contact surfaces of the power electronic device.
  • the electrically insulating layer is further provided at least one at least in parts covering ⁇ de metal layer.
  • the metal layer can form ei ⁇ ne or more separate interconnects. It can also be available over a wide area.
  • the metal layer preferably consists essentially of copper.
  • the metal layer may consist of several sub-layers, wherein the upper layer is applied by electroplating.
  • the power electronic circuit comprises we ⁇ ips overall a metal layer form-fitting manner at least partially covering buffer layer structure for buffering against mechanical expansion.
  • the buffer layer structure includes we ⁇ ipss a first layer of a ductile first Materi ⁇ al and at least a second layer of a divezug- compared with the ductile material, high pressure and high tear-fixed maximum second material.
  • a good explosion protection can be achieved by a buffer is realized layer structure of a form fit.
  • the buffer layer structure includes ⁇ thereby energy absorbing layers.
  • the kinetic energy is absorbed by the multilayer system of first and second layers and lends large area spread.
  • the kinetic energy is absorbed by the layer structure without the materials of the electronic power circuit penetrating to the outside and causing damage in the environment.
  • the planar construction technology is particularly suitable for the application of the multilayer coating structure, since the power electronic circuit has no bonding wires and the layers can be applied directly to the electrical connections.
  • Layer structure is advantageously adapted to the power density of the power electronic circuit.
  • the layer of ductile material may, for example, have a single- or multi-layered network or film structure, for example made of tear-resistant fabric of carbon fibers (kevlar, aramid) or plastics, such as ultrahigh molecular weight polyethylene.
  • structured metal foams with targeted porosities can serve as a ductile layer.
  • the layer of the second material may be a metal layer, preferably of hard metals, eg nickel alloys, tungsten aramid.
  • Other examples of the second material are functional ceramics such as oxide ceramic A1203 or silicon carbide SiC or AlSiCu, A1N, LTCC, HTCC, metals (iron alloys), polyethylene plates or glass cloth layers.
  • the layers are preferably applied galvanically, but can also be laminated as films, plasma or cold gas sprayed.
  • a preferred, but by no means limitative exporting ⁇ approximately example of the invention will be based on the
  • Figure 1 and 2 a power electronic circuit
  • FIG. 1 shows a cross section of a first power electronic circuit 100 with planar contacting technology.
  • the power electronic circuit 100 is constructed on a DCB substrate 110.
  • the DCB substrate 110 comprises a non-further structured underside copper layer
  • the upper copper layer 112 is largely ent ⁇ removed and only in this example, two places available, to which a contact is made.
  • an IGBT 131 is deposited over a solder layer 130.
  • the IGBT 131 is contacted on the lower side by the upper-side copper layer 112. The areas between the contact points of the topside copper layer
  • Polyimide film 120 a copper layer 140 is applied, which allows contacting of the IGBT 131 from above.
  • the copper layer 140 is connected to the topside copper layer 112 via a second window.
  • a further electrically insulating layer 160 is applied covering the entire structure.
  • This is positively and covering the entire structure, a buffer layer 160 of ductile material, game as applied in a sprayed metal foam ⁇ .
  • a third insulating layer 170 covers the buffer layer 160.
  • a metal layer 180 that is highly tear-resistant compared to the buffer layer 160, for example iron or iron alloys or metal composite materials such as tungsten carbide.
  • This metal layer 180 again covers the entire structure and is electrically separated from the power electronic elements by the insulating layers 150, 170.
  • FIG. 2 shows a very similar construction of a second power electronic circuit 200, in which most of the elements match those of the first power electronic circuit 100.
  • a heat sink 210 is arranged on the top side of the IGBT 131. In the process, it penetrates the insulating layers 150, 170 and the buffer layer 160 and thus establishes a direct heat conduction connection between the IGBT 131 and the metal layer 180. Thereby, a ef ⁇ fizienter heat transport from the IGBT 131 to the outside, ⁇ example, to a the power electronic circuit 200 sur- rounding coolant forth.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

L'invention concerne un circuit électronique de puissance présentant : - un substrat, - au moins un composant électronique de puissance disposé sur le substrat, - une couche électriquement isolante recouvrant en partie le substrat et le composant électronique de puissance, - au moins une couche métallique recouvrant au moins par parties la couche électriquement isolante, - au moins une structure de couche tampon recouvrant au moins partiellement et par complémentarité de forme la couche métallique pour la régulation contre une dilatation mécanique, la structure de couche tampon présentant au moins une première couche en un premier matériau ductile et au moins une deuxième couche en un deuxième matériau hautement résistant à la déchirure.
PCT/EP2014/066417 2013-08-07 2014-07-30 Circuit électronique de puissance présentant un contact électrique planaire WO2015018721A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102013215592.1 2013-08-07
DE201310215592 DE102013215592A1 (de) 2013-08-07 2013-08-07 Leistungselektronische Schaltung mit planarer elektrischer Kontaktierung

Publications (1)

Publication Number Publication Date
WO2015018721A1 true WO2015018721A1 (fr) 2015-02-12

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Application Number Title Priority Date Filing Date
PCT/EP2014/066417 WO2015018721A1 (fr) 2013-08-07 2014-07-30 Circuit électronique de puissance présentant un contact électrique planaire

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DE (1) DE102013215592A1 (fr)
WO (1) WO2015018721A1 (fr)

Citations (10)

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WO2003030247A2 (fr) 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques
WO2005027222A2 (fr) * 2003-09-12 2005-03-24 Siemens Aktiengesellschaft Composant electrique comportant une feuille d'isolation electrique disposee sur un substrat et procede de fabrication dudit dispositif
EP1548829A2 (fr) * 2003-11-29 2005-06-29 Semikron Elektronik GmbH Patentabteilung Module à semi-conducteur de puissance et procédé pour sa fabrication
WO2005096374A1 (fr) * 2004-03-15 2005-10-13 Siemens Aktiengesellschaft Produit electrotechnique comprenant un element electrique et une masse de scellement pour l'isolation electrique de l'element, et procede de fabrication associe
WO2006067021A1 (fr) * 2004-12-22 2006-06-29 Siemens Aktiengesellschaft Dispositif d'un module semi-conducteur et un ensemble de barres electriques
WO2006069855A1 (fr) * 2004-12-28 2006-07-06 Siemens Aktiengesellschaft Ensemble comprenant un composant electrique et un dispositif de refroidissement a deux phases
WO2007012558A1 (fr) * 2005-07-26 2007-02-01 Siemens Aktiengesellschaft Ensemble constitue d'un composant electrique et d'un composite a base de films contrecolle sur ce composant et procede de production de cet ensemble
EP1956647A1 (fr) * 2007-02-10 2008-08-13 SEMIKRON Elektronik GmbH & Co. KG Installation de commutation dotée d'un dispositif de liaison et son procédé de fabrication
EP2463900A2 (fr) * 2010-12-07 2012-06-13 SEMIKRON Elektronik GmbH & Co. KG Procédé de fabrication d'un agencement de commutation
DE102011083627A1 (de) * 2011-09-28 2013-03-28 Continental Automotive Gmbh Verfahren zur Kontaktierung eines elektronischen Bauteils und Baugruppe mit einem elektronischen Bauteil auf einem Substrat

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DE10055454A1 (de) * 2000-11-09 2002-05-23 Fujitsu Siemens Computers Gmbh Kühlkörper
EP2062294B1 (fr) * 2006-09-14 2019-04-03 Siemens Aktiengesellschaft Module à semi-conducteur de puissance comprenant une protection en cas d'explosion
DE102007005233B4 (de) * 2007-01-30 2021-09-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Leistungsmodul
DE102007039905A1 (de) * 2007-08-23 2008-08-28 Siemens Ag Verfahren zur Herstellung einer wärmeleitfähigen Materialschicht
DE102007039904A1 (de) * 2007-08-23 2008-08-28 Siemens Ag Verfahren zur Herstellung einer wärmeleitfähigen Materialschicht
DE102012201612B3 (de) * 2012-02-03 2013-06-13 Siemens Aktiengesellschaft Kühlelement für Leistungshalbleiter-Bauelemente

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003030247A2 (fr) 2001-09-28 2003-04-10 Siemens Aktiengesellschaft Procede d'etablissement de contact pour des surfaces de contact electriques situees sur un substrat et dispositif constitue d'un substrat pourvu de surfaces de contact electriques
WO2005027222A2 (fr) * 2003-09-12 2005-03-24 Siemens Aktiengesellschaft Composant electrique comportant une feuille d'isolation electrique disposee sur un substrat et procede de fabrication dudit dispositif
EP1548829A2 (fr) * 2003-11-29 2005-06-29 Semikron Elektronik GmbH Patentabteilung Module à semi-conducteur de puissance et procédé pour sa fabrication
WO2005096374A1 (fr) * 2004-03-15 2005-10-13 Siemens Aktiengesellschaft Produit electrotechnique comprenant un element electrique et une masse de scellement pour l'isolation electrique de l'element, et procede de fabrication associe
WO2006067021A1 (fr) * 2004-12-22 2006-06-29 Siemens Aktiengesellschaft Dispositif d'un module semi-conducteur et un ensemble de barres electriques
WO2006069855A1 (fr) * 2004-12-28 2006-07-06 Siemens Aktiengesellschaft Ensemble comprenant un composant electrique et un dispositif de refroidissement a deux phases
WO2007012558A1 (fr) * 2005-07-26 2007-02-01 Siemens Aktiengesellschaft Ensemble constitue d'un composant electrique et d'un composite a base de films contrecolle sur ce composant et procede de production de cet ensemble
EP1956647A1 (fr) * 2007-02-10 2008-08-13 SEMIKRON Elektronik GmbH & Co. KG Installation de commutation dotée d'un dispositif de liaison et son procédé de fabrication
EP2463900A2 (fr) * 2010-12-07 2012-06-13 SEMIKRON Elektronik GmbH & Co. KG Procédé de fabrication d'un agencement de commutation
DE102011083627A1 (de) * 2011-09-28 2013-03-28 Continental Automotive Gmbh Verfahren zur Kontaktierung eines elektronischen Bauteils und Baugruppe mit einem elektronischen Bauteil auf einem Substrat

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