WO2015014080A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2015014080A1
WO2015014080A1 PCT/CN2013/089626 CN2013089626W WO2015014080A1 WO 2015014080 A1 WO2015014080 A1 WO 2015014080A1 CN 2013089626 W CN2013089626 W CN 2013089626W WO 2015014080 A1 WO2015014080 A1 WO 2015014080A1
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Prior art keywords
metal
layer
array substrate
film
aluminum
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French (fr)
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刘翔
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/407,011 priority Critical patent/US20160268305A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4405—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H10W20/4407—Aluminium alloys

Definitions

  • Thin Film Transistor Liquid Crystal Display (Thin Film TFT LCD) has a small size, low power consumption, no radiation, and is dominant in the current flat panel display market.
  • TFT LCD Thin Film Transistor Liquid Crystal Display
  • the array substrate and manufacturing process determine its performance, yield and quality.
  • the array substrate mainly comprises a substrate and a pixel unit on the substrate, and the pixel unit is mainly composed of a gate scan line, a data scan line, and a thin film transistor.
  • the gate scan line and the data scan line are respectively used for transmitting the scan signal and the data signal.
  • the metal or metal alloy with good conductivity is generally used as the gate scan line and the data scan line.
  • the material of the gate scan line and the data scan line is converted into a low-resistance pure aluminum (A1) material by the original high-resistance material chromium (( ), molybdenum (Mo), aluminum lanthanum (AlNd).
  • the thermal stability is poor. After heating to a certain extent, a hillock will appear, which will pierce the gate insulating layer, resulting in a gate scan line and a source electrode, a drain electrode, or a gate. A short circuit occurs between the scan line and the data scan line.
  • the mechanism of the hillock is: due to the difference in thermal expansion coefficient between the glass and the A1 film, the A1 film undergoes expansion deformation when heated, and the A1 film is restricted on the side against the glass. When the temperature reaches a certain level (generally 130 degrees Celsius), the A1 film reaches the maximum internal compressive stress limit, and the atoms in the Ai film move, releasing the internal stress, generally released along the grain boundary, forming Hillock.
  • the present invention provides an array substrate and a display device capable of forming a metal pattern of an array substrate to generate hillocks due to heat.
  • An array substrate comprising a substrate and a metal pattern on the substrate, the metal pattern comprising A metal layer formed of a mixture of aluminum and a second metal, wherein a molar ratio of the second metal to aluminum in the metal layer is less than 1/99.
  • the molar ratio of the second metal to aluminum is between 1/999 1/199.
  • the second metal acts as a rod in the aluminum metal film to prevent the aluminum atoms from moving after being heated, thereby avoiding the formation of hillocks.
  • the second metal is formed at a grain boundary where a film is formed of aluminum.
  • the metal pattern is a two-layer structure, wherein a first layer adjacent to the substrate is the metal layer; and a second layer above the first layer is a film layer formed of a molybdenum material.
  • the metal pattern is a three-layer structure in which a plurality of layers are sequentially stacked, wherein a first layer adjacent to the substrate is a film layer formed of a molybdenum material; a second layer located above the first layer is the metal layer; The third layer above the second layer is a film layer composed of a molybdenum, titanium or tantalum material.
  • the second metal is tantalum, titanium, zirconium, hafnium, tantalum or copper.
  • the metal pattern is at least one of a gate electrode, a gate scan line, a data scan line, a source electrode, and a drain electrode.
  • the metal layer has a thickness ranging from 4000A to 8000A.
  • a display device comprising the array substrate.
  • a trace amount of other metal elements are added to aluminum (A1) to form an alloy, such as niobium (Nd), titanium (niobium), zirconium (Zr), niobium ( ⁇ , ⁇ (Sc) or copper (Cii).
  • an alloy such as niobium (Nd), titanium (niobium), zirconium (Zr), niobium ( ⁇ , ⁇ (Sc) or copper (Cii).
  • An array substrate includes a substrate and a metal pattern on the substrate, the metal pattern comprising a metal layer formed of a mixture of aluminum and a second metal, wherein the second metal and aluminum in the metal layer
  • the molar ratio is less than 1/99.
  • the molar ratio of the second metal to aluminum is, for example, between 1/999 and 1/199.
  • the second metal is formed at a grain boundary formed by a film of aluminum, that is, a film formed of the A1 metal is composed of crystal grains, and grain boundaries are formed between adjacent crystal grains (it can be understood as a grain boundary) Wherein the second metal is formed at the grain boundary.
  • the second metal acts as a rod in the aluminum film to prevent the aluminum atoms from moving after being heated, thereby avoiding the formation of hillocks.
  • the metal pattern is a two-layer structure, wherein a first layer adjacent to the substrate is the metal layer; and a second layer above the first layer is a film layer formed of a Mo material.
  • the metal pattern is a three-layer structure in which a plurality of layers are sequentially stacked, wherein a first layer adjacent to the substrate is a film layer formed of a Mo material; a second layer located above the first layer is the metal layer; The third layer above the second layer is a film layer composed of ⁇ , ⁇ or a material.
  • the second metal is tantalum, titanium, zirconium, hafnium, tantalum or copper.
  • the metal pattern is at least one of a gate electrode, a gate scan line, a data scan line, a source electrode, and a drain electrode.
  • An array substrate comprising at least a metal pattern on a substrate and a substrate, the metal pattern comprising a metal layer according to an embodiment of the invention, the metal pattern at least forming a gate scan line, a data scan line, and a thin film transistor,
  • the thin film transistor includes at least a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the gate scan line, the data scan line, the source electrode, and the drain electrode includes the metal layer of the present invention.
  • the first method is to form a metal film with a high melting point on the A1 metal layer, or on the upper and lower sides, which can suppress the release of stress and prevent the generation of hillocks.
  • Another method is to add other elements in A1 to form an alloy, such as Nd, Ti, Zr, Sc, Cu, etc.
  • the added metal is formed at the grain boundary of the Al metal forming film, which acts as a fixing to prevent The formation of hillocks.
  • the ffi AiNd alloy is used, the molar ratio of Nd is relatively high, generally between 2% and 20%, and it is generally considered that such a content can better control the formation of hillocks.
  • the Nd content is controlled to be less than 1% H, and the problem of hillocks is well solved.
  • the Nd content is controlled to be 0.1% - 0, 5%. . If a metal film with a high melting point is formed on the upper and lower sides of the metal layer formed by the AlNd alloy, and the double-layer structure or the three-layer structure is combined, the hillock problem is well solved. The yield is 1%-8% higher than before.
  • the present invention will be described below in conjunction with the metal pattern described in the present invention as a two-layer structure and a three-layer structure.
  • the present invention provides an array substrate comprising a substrate and a metal pattern on the substrate, the metal pattern being a two-layer structure, wherein a first layer structure adjacent to the substrate is composed of the second metal and A];
  • the second layer structure above the layer structure consists of Mo.
  • the invention adds a second metal element to form a alloy in A1, such as Nd, Ti, Zr, T a , Sc, Cii and the like, and the added metal is formed at the grain boundary to play a role of fixing the formation of the hillock. .
  • the molar ratio of the second metal to A] in the metal layer is less than 1/99, for example, the molar ratio of the second metal to A1 is between 1/999-1/199. While reducing the cost, it can solve the production of a small number of hillocks in the prior art, thereby improving the yield of the product by 1%-8%.
  • a metal film having a high defect is formed on the A1 metal layer, and the film can suppress the release of stress and prevent the generation of hillocks.
  • other elements are added to form an alloy in A1.
  • a metal such as Nd, Ti, Zr, Sc, Cu, etc., and the content of other metals in the metal layer of the embodiment of the present invention is controlled to be between 0.1 and 0.5%, and the added metal is formed at the grain boundary to serve
  • the role of the tie, to prevent the formation of hillocks, and the addition of a small amount of metal is relatively low in price, low in electrical resistance, and can also break the limitation of A1 film, which can increase the thickness of single layer of A1 film from 2000A to 4000A to 8000A. .
  • this material has low price and low electrical resistance.
  • the pure A1 film the price and resistance are almost equal, but the product yield can be improved.
  • the second metal is Nd, T.i, Zr, Sc or Cu, and these metals are all high melting point metals.
  • the metal pattern may be at least one of a gate, a gate scan line, a data scan line, a source electrode, and a drain electrode.
  • the present invention provides an array substrate comprising a substrate and a metal pattern deposited on the substrate, the metal pattern being a layered structure in which layers are sequentially stacked, wherein the first layer structure is composed of Mo;
  • the second metal is composed of A1;
  • the second layer structure is composed of ⁇ , ⁇ or Ta.
  • the third layer structure is a barrier layer.
  • other metal elements are added to form an alloy, such as Nd, ⁇ Zr, Ta, Sc, Cu and other metals, the added metal is formed at the grain boundary, which acts as a fixed tie to prevent the formation of hillocks.
  • the molar ratio of the second metal to Ai in the metal layer is less than 1/99, for example, the molar ratio of the second metal to A1 is between 1/999 1A99. While reducing costs, it can solve the production of a small number of hillocks in the prior art, thereby increasing the yield of the product by 1%-8%.
  • a three-layer structure of Mo/Ai/Mo is used to form a metal film with a high melting point on the upper and lower surfaces of the Ai metal layer.
  • the film can suppress the release of stress and prevent the generation of hillocks.
  • other elements are added to form an alloy in A1. , such as Nd, Ti, Zr, Ta, Sc, Cu and other metals, and the content of other metals in the metal layer is controlled between 0.1-0.5%, the added metal is formed at the grain boundary, and plays a role of 3 ⁇ 4, Preventing the formation of hillocks, and adding a small amount of metal is relatively low in price, low in electrical resistance, and can also break the limitation of A1 film, which can increase the thickness of A1 film from 2000A to 4000A. Compared with the conventional alloy materials, this material has a low price and a low electrical resistance. Compared with the pure A1 film, the price and resistance are almost equal, but the product yield can be improved.
  • the second metal is Nd, Ti, Zr, T3 ⁇ 4, Sc or Cu. These metals are all high-pitched metals.
  • the metal pattern may be at least one of a gate, a gate scan line, a data scan line, a source electrode, and a drain electrode.
  • the present invention also provides a display device comprising the above described array substrate.
  • the display device may be: a liquid crystal panel, an electronic paper, an organic light emitting display (OLED) panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, and the like. Or parts.
  • the invention adds other metal elements in A1 to form an alloy, such as Nd, Ti, Zr, T3 ⁇ 4, Sc, Cu and the like metal, and the added metal is formed in the crystal to play a role of fixing, preventing the A1 atom from moving and forming small after being heated. mound.
  • the content of other metals in the metal layer of the present invention is controlled to be less than 1%, for example, between 0,1 and 0.5%, using an Al/Mo double layer structure or ⁇ / ⁇ 1/ ⁇ , so that the original base can be used. On the basis of further reducing the number of hillocks, it can even eliminate the occurrence of hillocks, thereby increasing the yield of 1-8% products.
  • Other metals may be metals such as Ti, Zr, T a , Sc, Cu, and the like.
  • the content of other metals in the Al film is reduced by at least 20 times. Compared with the conventional alloy materials, this material has low price and low electrical resistance. Compared with pure A1 film, the price and resistance are almost equal, but the product yield can be improved.
  • the present invention can effectively solve the problem that the Mo/AI/Mo structure cannot effectively suppress hillocks as the thickness of A1 increases, such as more than 3000A.
  • the material used in the present invention may be added with a small amount of metal such as Nd in the pure A] film, and the content is ⁇ 1%, so that the hillock phenomenon does not occur when the thickness of Al is more than 3000A by using a three-layer structure such as ⁇ / ⁇ 1/ ⁇ . Can effectively improve the yield rate.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)

Abstract

提供了一种阵列基板及显示装置。阵列基板包括基板和基板上的金属图案，金属图案包括由铝和第二金属的混合物形成的金属层，金属层中第二金属与铝的摩尔比低于1/99。通过将金属层中第二金属的含量控制在低于1%，并将金属层应用在栅极扫描线和数据扫描线中，能够抑制栅极扫描线和数据扫描线由于受热而产生小丘的现象。

Description

阵列基板及显示装置
Figure imgf000002_0001
薄膜晶体管液晶显 器 ( Thin Film Transistor Liquid Crystal Display,简禾尔 TFT-LCD ) 具有体积小、 功耗低、 无辐射等特点， 在当前的平板显示器市场 中占据了主导地位。对于 TFT CD来说， 阵列基板以及制造工艺决定了其产 性能、 成品率和^格。
一般而言， 阵列基板主要包括基板以及基板上的像素单元， 像素单元主 要由栅极扫描线、 数据扫描线、 薄膜晶体管组成。 栅极扫描线和数据扫描线 分别用来传输扫描信号和数据信号， 为了防止信号在传输过程中产生信号失 真， 一般用导电性能好的金属或金属合金 ^来做栅极扫描线和数据扫描线的 材料。栅极扫描线和数据扫描线的材料由原来高电阻材料铬（( )、钼（Mo)、 铝钕 （AlNd) 逐歩转化成低电阻纯铝 （A1 ) 材料。 但是， 低电阻纯 A1 薄膜 的缺点是热稳定性差， 加热到一定程度之后， 会出现小丘 （Miock) , 该小丘 会刺穿栅极绝缘层， 从而导致栅极扫描线和源电极、 漏电极之间， 或者栅极 扫描线与数据扫描线之间发生短路。小丘产生的机理是： 由于玻璃和 A1薄膜 之间的热膨胀系数不同， 受热时 A1薄膜发生膨胀形变， 而 A1薄膜在靠玻璃 的一侧由于受到限制， 当温度达到一定程度时 （一般为 130摄氏度）， A1薄 膜达到内部最大的承受压缩应力的极限， Ai薄膜内的原子发生移动， 释放内 部的应力， 一般沿着晶界的方向释放， 就形成小丘。
因此， 如何更好的抑制小丘的形成成为本领域亟待解决的技术问题。
本发明提供一种阵列基板及显示装置， 能够 W制阵列基板的金属图案由 于受热而产生小丘。
一种阵列基板， 包括基板和所述基板上的金属图案， 所述金属图案包括 由铝和第二金属的混合物形成的金属层， 所述金属层中第二金属与铝的摩尔 比低于 1/99。
所述第二金属与铝的摩尔比在 1/999 1/199之间。
所述第二金属在金属铝薄膜内起到定扎的作用， 防止铝原子受热之后发 生移动， 从而避免了小丘的形成。
所述第二金属形成在由铝形成薄膜的晶界处。
所述金属图案为双层结构， 其中， 靠近所述基板的第一层为所述金属层； 位于所述第一层上面的第二层为由钼材料形成的膜层。
所述金属图案为依次叠加的三层结构， 其中， 靠近所述基板的第一层为 由钼材料形成的膜层； 位于所述第一层上面的第二层为所述金属层； 位于所 述第二层上面的第三层为由钼、 钛或钽材料组成的膜层。
所述第二金属为钕、 钛、 锆、 钽、 钪或者铜。
所述金属图案为栅电极、 栅极扫描线、 数据扫描线、 源电极、 漏电极中 的至少一种。
所述金属层的厚度范围为 4000A至 8000A。
一种显示装置， 包括所述的阵列基板。
本发明实施例的上述技术方案的有益效果如下：
本发明实施例在铝 (A1)中添加微量的其它金属元素形成合金，如钕（Nd)、 钛 （Ή)、 锆 （Zr)、 钽 （Τ∑ϋ、 钪 （Sc) 或者铜 （Cii) 等金属， 降低成本， 同 时添加的金属在晶体内起到定扎的作用， 防止 A1原子受热移动形成小丘， 与 纯 A1的三层结构一起使 ^可以提高产品的良品率， 大约可以提高 1%- 8%。 具体实施方式
为使本发明要解决的技术问题、 技术方案和优点更加清楚， 下面将结合 具体实施例进行详细描述。
本发明所述的一种阵列基板， 包括基板和所述基板上的金属图案， 所述 金属图案包括由铝和第二金属的混合物形成的金属层， 所述金属层中第二金 属与铝的摩尔比低于 1/99。
所述第二金属与铝的摩尔比例如在 1/999-1/199之间。 所述第二金属形成在由铝形成薄膜的晶界处,也就是说由 A1金属形成的 薄膜是有晶粒组成的，相邻的晶粒之间形成晶界（可以理解成晶粒的交界处）, 所述第二金属形成在该晶界处。 所述第二金属在铝薄膜内起到定扎的作用， 防止铝原子受热之后发生移动， 认而避免了小丘的形成。
所述金属图案为双层结构， 其中， 靠近所述基板的第一层为所述金属层； 位于所述第一层上面的第二层为由 Mo材料形成的膜层。
所述金属图案为依次叠加的三层结构， 其中， 靠近所述基板的第一层为 由 Mo材料形成的膜层； 位于所述第一层上面的第二层为所述金属层； 位于 所述第二层上面的第三层为由 Μο、 Ή或 材料组成的膜层。
所述第二金属为钕、 钛、 锆、 钽、 钪或者铜。
所述金属图案为栅电极、 栅极扫描线、 数据扫描线、 源电极、 漏电极中 的至少一种。
一种阵列基板， 至少包括基板和基板上的金属图案， 所述金属图案包括 本发明实施例所述的金属层， 所述金属图案至少 ^于形成栅极扫描线、 数据 扫描线和薄膜晶体管， 所述薄膜晶体管至少包括栅电极、 源电极和漏电极， 所述栅电极、 栅极扫描线、 数据扫描线、 源电极、 漏电极至少一种包括本发 明所述的金属层。
目前解决 A1薄膜产生的小丘有两种方法： 第一个方法就是在 A1金属层 上面， 或者上下两面形成一层熔点很高的金属薄膜， 该薄膜可以抑制应力的 释放， 阻止小丘的产生； 另外一个方法是在 A1中添加其它元素形成合金， 如 Nd、 T.i, Zr、 、 Sc、 Cu等金属， 添加的金属形成在 Al金属形成薄膜的晶 界处， 起到定扎的作用， 防止小丘的形成。 在使 ffi AiNd合金时， Nd的摩尔 比较高， - -般在 2% 20%之间， 通常认为这样的含量可以更好的控制小丘的 形成。 但是， 在现有的 AiNd合金中添加高含量的 Nd, 不仅使 AlNd合金电 阻比较大， 同时 Nd金属比较贵， 造成成本的浪费， 本发明的实施例中， 在 AlNd合金中添加微量的 Nd， 在 AiNd合金中将 Nd含量控制在低于 1%H寸， 小丘的问题得到了很好的解决， 例如， 所述 AiNd合金中将 Nd含量控制在 0.1%- 0,5%时效果较好。 若在 AlNd合金形成的金属层上下两面形成一层熔点 很高的金属薄膜， 结合双层结构或三层结构， 小丘问题得到了很好的解决， 良品率相比之前提高了 1%-8%。
下面结合本发明所述的金属图案为双层结构及三层结构对本发明迸行迸 一步描述。
实施例 1
本发明提供一种阵列基板， 包括基板和所述基板上的金属图案， 所述金 属图案为双层结构，其中，靠近基板的第一层结构由所述第二金属和 A】组成; 第一层结构上面的第二层结构由 Mo组成。本发明在 A1中添加第二金属元素 形成合金， 如 Nd、 Ti、 Zr、 Ta、 Sc、 Cii等金属， 添加的金属形成在晶界处， 起到定扎的作用， 防止小丘的形成。
其中， 所述金属层中第二金属与 A】的摩尔比低于 1/99, 例如， 所述第二 金属与 A1的摩尔比在 1/999-1/199之间。 在降低成本的同时， 可以解决现有 技术中少量小丘的产生， 从而提高产品的良品率 1 %- 8%。
这样，采用 Al/Mo双层结构，在 A1金属层上面形成一层瑢点很高的金属 薄膜， 该薄膜可以抑制应力的释放阻止小丘的产生， 另外， 在 A1中添加其它 元素形成合金， 如 Nd、 Ti、 Zr、 、 Sc、 Cu等金属， 且将本发明实施例的金 属层中的其他金属的含量控制在 0.1- 0.5%之间， 添加的金属形成在晶界处， 起到定扎的作用， 防止小丘的形成， 且添加少量的金属价格相对低， 电阻小， 同时还可以打破 A1 薄膜的限制， 可以使 A1 薄膜的单层厚度从原来的 2000A- 4000A之间增加到 8000A。这种材料与以往的合金材料相比， 价格低、 电阻小； 与纯 A1薄膜相比，价格和电阻几乎相等，但可以提升产品的良品率。
其中， 所述第二金属为 Nd、 T.i, Zr、 、 Sc或者 Cu， 这些金属都为高 熔点金属。
其中， 所述金属图案可以为栅极、 栅极扫描线、 数据扫描线、 源电极、 漏电极中的至少一种。
实施例 2
本发明提供一种阵列基板， 包括基板和沉积在所述基板上的金属图案， 所述金属图案为依次叠加的≡层结构， 其中， 第一层结构由 Mo组成； 第二 层结构由所述第二金属和 A1组成； 第≡层结构由 Μο、 Ή或 Ta组成。 第三 层结构为阻挡层。本发明实施例在 A1中添加其它金属元素形成合金， 如 Nd、 Τ Zr、 Ta, Sc、 Cu等金属， 添加的金属形成在晶界处， 起到定扎的作用， 防止小丘的形成。
其中， 所述金属层中第二金属与 Ai的摩尔比低于 1/99， 例如， 所述第二 金属与 A1的摩尔比在 1/999 1A99之间。 在降低成本的同时， 可以解决现有 技术中少量小丘的产生， 从而提高产品的良品率 1%- 8%。
采用 Mo/Ai/Mo三层结构， 在 Ai金属层上下表面各形成一层熔点很高的 金属薄膜， 该薄膜可以抑制应力的释放阻止小丘的产生， 另外， 在 A1中添加 其它元素形成合金， 如 Nd、 Ti、 Zr、 Ta, Sc、 Cu等金属， 且金属层中的其他 金属的含量控制在 0.1- 0.5%之间， 添加的金属形成在晶界处， 起到定 ¾的作 用， 防止小丘的形成， 且添加少量的金属价格相对低， 电阻小， 同时还可以 打破 A1薄膜的限制， 可以使 A1薄膜的厚度从原来的 2000A 4000A之间增加 到 8000A。 这种材料与以往的合金材料相比， 价格低、 电阻小； 与纯 A1薄膜 相比， 价格和电阻几乎相等， 但可以提升产品的良品率。
其中， 所述第二金属为 Nd、 Ti、 Zr、 T¾、 Sc或者 Cu。 这些金属都为高 瑢点金属。
其中， 所述金属图案可以为栅极、 栅极扫描线、 数据扫描线、 源电极、 漏电极中的至少一种。
本发明还提供一种显示装置， 包括上述所述的阵列基板。 所述显示装置 可以为：液晶面板、电子纸、有机电致发光显示 OLED ( Organic Light Emitting Display, 简称 OLED) 面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平 板电脑等任何具有显示功能的产品或部件。
现有技术中， 业界的面板厂商一般使用纯 A1薄膜， 这种方式的电阻低、 价格便宜。 但对 Ai薄膜的厚度有一定限制， 一般在 2000A- 4000A之间， 随 着 A1薄膜厚度的增加， 顶层 Mo 的厚度也在不断的增加， 从 500A增加到 2000A。 这种方式不能从根本解决小丘的产生， 仍然会有少量的小丘产生。
本发明在 A1中添加其它金属元素形成合金， 如 Nd、 Ti、 Zr, T¾、 Sc、 Cu等金属， 添加的金属形成在晶体中， 起到定扎的作用， 防止 A1原子受热 后移动形成小丘。本发明的金属层中的其他金属的含量控制在低于 1%，例如 在 0,1 - 0.5%之间，采用 Al/Mo双层结构或者 Μο/Α1/Μο，这样就可以在原来基 础上进一步减少小丘的数量， 甚至可以杜绝小丘的产生， 从而提高 1-8%的产 品良品率。 这样做不仅可以减少了小丘引起的不良， 相对以往的合金材料， 价格相对低， 电阻小， 同时还可以打破 A1薄膜的限制， 可以使 A1薄膜的厚 度增加到 8000A。 其他金属可以是 Ti、 Zr、 Ta、 Sc、 Cu等金属。 使得 Al薄 膜中其他金属的含量至少降低为原来的 20倍。这种材料与以往的合金材料相 比， 价格低、 电阻小； 与纯 A1薄膜相比， 价格和电阻几乎相等， 但可以提升 产品的良品率。 本发明可以有效地解决随着 A1厚度的增加， 如大于 3000A, Mo/AI/Mo结构不能有效地抑制小丘的问题。 本发明使用的材料可以在纯 A】 薄膜中添加少量的 Nd等金属，含量 <1%，这样在采用三层结构如 Μο/Α1/Μο， Al的厚度大于 3000A时不再发生小丘现象， 可以有效地提升良品率。
以上所述是本发明的几种实施方式， 应当指出， 对于本技术领域的普通 技术人员来说， 在不脱离本发明所述原理的前提下， 还可以作出若干改进和 润饰， 这些改进和润饰也应视为本发明的保护范围。

Claims

1. 一种阵列基板， 包括基板和所述基板上的金属图案， 其特征在于， 所 述金属图案包括由铝和第二金属的混合物形成的金属层， 所述金属层中第二 金属与铝的摩尔比低于 1/99。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述第二金属与铝的 摩尔比在 1/999 1/199之间。
3. 根据权利要求 1所述的阵列基板， 其特征在于， 所述第二金属形成在 由铝形成薄膜的晶界处。
4. 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述金属图案为 双层结构， 其中， 靠近所述基板的第一层为所述金属层； 位于所述第一层上 面的第二层为由钼材料形成的膜层。
5. 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述金属图案为 依次叠加的≡层结构， 其中， 靠近所述基板的第一层为由钼材料形成的膜层; 位于所述第一层上面的第二层为所述金属层； 位于所述第二层上面的第≡层 为由钼、 钛或钽材料组成的膜层。
6. 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述第二金属为 欽、 钛、 错、 钽、 钪或者-铜。
7. 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述金属图案为 栅电极、 栅极扫描线、 数据扫描线、 源电极、 漏电极中的至少一种。
8. 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述金属层的厚
Figure imgf000008_0001
9. 一种显示装置， 其特征在于， 包括权利要求 1 -8中任一项所述的阵列
PCT/CN2013/089626 2013-08-01 2013-12-17 阵列基板及显示装置 Ceased WO2015014080A1 (zh)

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