WO2015002125A1 - Ｐｗｍ制御回路およびスイッチング電源装置 - Google Patents

Ｐｗｍ制御回路およびスイッチング電源装置 Download PDF

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WO2015002125A1
WO2015002125A1 PCT/JP2014/067324 JP2014067324W WO2015002125A1 WO 2015002125 A1 WO2015002125 A1 WO 2015002125A1 JP 2014067324 W JP2014067324 W JP 2014067324W WO 2015002125 A1 WO2015002125 A1 WO 2015002125A1
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circuit
signal
square wave
capacitor
potential
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PCT/JP2014/067324
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English (en)
French (fr)
Japanese (ja)
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井尻康則
三橋宗太郎
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株式会社村田製作所
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Priority to CN201480027874.4A priority Critical patent/CN105210285B/zh
Priority to JP2015525198A priority patent/JP6115637B2/ja
Publication of WO2015002125A1 publication Critical patent/WO2015002125A1/ja

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
    • H02M7/53803—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration with automatic control of output voltage or current

Definitions

  • the present invention relates to a PWM control circuit that generates two PWM signals having a phase difference, and a switching power supply device including the PWM control circuit in a switching control unit.
  • Patent Document 1 An example of a switching control circuit by PWM control in a switching power supply device is shown in Patent Document 1. Further, Patent Document 2 discloses a power supply device that applies an alternating voltage by a pseudo rectangular wave to a capacitive load.
  • a PWM control circuit basically includes a triangular wave generation circuit that generates a triangular wave (sawtooth wave) and a comparison circuit that compares the triangular wave signal with a modulation signal.
  • the modulation signal is an output voltage detection signal, and the switching element is driven by the output signal of the PWM control circuit.
  • FIG. 15 is a circuit diagram of the power supply device disclosed in Patent Document 2.
  • a switching circuit SW1 and SW2 and capacitors C1 and C2 constitute a bridge circuit.
  • the primary winding N1 of the transformer T is connected to the bridge circuit via the inductor L1.
  • a capacitive load Cload or the like is connected to the secondary winding N2 of the transformer T.
  • the switching elements SW1 and SW2 are alternately turned on / off by the control circuit 20. As a result, a pseudo rectangular wave signal is generated, and an AC voltage is applied to the capacitive load Cload.
  • JP 59-191478 A Japanese Patent No. 3228298
  • the control circuit 20 is a circuit that alternately distributes a PWM signal having a fixed period between the high side and the low side, and therefore the phase difference of the drive signal with respect to the switching elements SW1 and SW2 is 180 °.
  • the duty ratio of the pseudo rectangular wave to be generated is 50%. Therefore, even if a PWM control circuit as shown in Patent Document 1 is applied to the control circuit 20 shown in FIG. 15, the on-periods of the switching elements SW1 and SW2 are maintained while maintaining the phase difference of 180 °. It is only controlled.
  • phase difference between the drive signals of the high-side switching element SW1 and the low-side switching element SW2 it is necessary to set the phase difference between the drive signals of the high-side switching element SW1 and the low-side switching element SW2 to a value other than 180 °.
  • phase difference cannot be set in a conventional general PWM control circuit that generates a PWM signal by comparing a triangular wave signal and a modulation signal.
  • An object of the present invention is to provide a PWM control circuit capable of generating two PWM signals having an arbitrary phase difference without complicating the circuit, or a PWM capable of obtaining a pseudo rectangular wave signal having an arbitrary duty ratio. It is to provide a control circuit and to provide a switching power supply device including the PWM control circuit.
  • the PWM control circuit of the present invention is configured as follows.
  • a square wave signal setting means for inputting a square wave signal of a predetermined (arbitrary frequency and duty ratio) from the outside or generating internally,
  • a modulation signal input terminal for inputting a modulation signal;
  • First and second modulated signal output terminals for outputting two modulated signals having different timings (phases);
  • a first ramp wave generating circuit for starting sweeping of the first ramp wave in synchronization with a rising edge of the square wave signal;
  • a second ramp wave generating circuit for starting a sweep of the second ramp wave in synchronization with a falling edge of the square wave signal;
  • a first comparison circuit that compares the first ramp wave with the modulation signal and generates a first modulated signal by inverting the level according to the comparison result;
  • a second comparison circuit for comparing the second ramp wave and the modulation signal and generating a second modulated signal by inverting the level according to the comparison result; It is provided with.
  • the first ramp wave is reset to a potential at which a sweep starts between the falling and rising edges of the square wave signal
  • the second ramp wave is a rising and falling edge of the square wave signal. It is preferable to reset to the potential at which the sweep starts.
  • the first ramp wave is reset to the potential at which the sweep starts at the rising edge of the square wave signal
  • the second ramp wave is reset to the potential at which the sweep starts at the falling edge of the square wave signal. May be.
  • the first ramp wave is reset to the potential at which the sweep starts at the falling edge of the square wave signal
  • the second ramp wave is reset to the potential at which the sweep starts at the rising edge of the square wave signal. May be.
  • the first and second ramp waves are reset to the potential at which the sweep starts, so that a ramp wave that does not affect the comparison with the modulation signal can be obtained.
  • the first ramp wave generating circuit includes a first time constant circuit including a first capacitor connected between a reference potential (GND) and a power source, and the first time constant circuit.
  • a first time constant circuit including a first capacitor connected between a reference potential (GND) and a power source
  • the first time constant circuit are connected in series, and the first switch element whose on / off state changes in accordance with the level of the square wave signal and the state of the first time constant circuit are reset in synchronization with the fall of the square wave signal.
  • a first reset circuit and outputs an output voltage of the first time constant circuit as the first ramp wave
  • the second ramp wave generating circuit is connected in series with a second time constant circuit including a second capacitor connected between a reference potential (GND) and a power source, and the second time constant circuit.
  • a second switch element whose on / off state changes according to the level of the square wave signal, and a second reset that resets the state of the second time constant circuit in synchronization with the rising of the square wave signal.
  • a circuit that outputs the output voltage of the second time constant circuit as the second ramp wave.
  • the start and discharge (reset) of the capacitor of the time constant circuit is performed by controlling the switch element, so that a simple circuit can be configured.
  • the first ramp wave generating circuit is connected in series to the first time constant circuit having a first capacitor on the reference potential (GND) side, and the square wave A first switch element whose on / off state changes in accordance with a signal level; and a diode connected to the first capacitor in a direction in which a discharge current of the first capacitor flows through the first switch element.
  • the second ramp wave generating circuit is connected in series with a second time constant circuit having a second capacitor on the reference potential (GND) side, and the level of the square wave signal.
  • a second switching element whose on / off state changes in response to the second switching element, and a diode connected to the second capacitor in a direction in which the discharge current of the second capacitor flows via the second switching element,
  • the start and discharge (reset) of the capacitor of the time constant circuit is performed by controlling the switch element, so that a simple circuit can be configured.
  • the first time constant circuit includes a first constant current circuit that supplies a constant charging current to the first capacitor, and the second time constant.
  • the circuit preferably includes a second constant current circuit for supplying a constant charging current to the second capacitor.
  • the switching power supply device of the present invention is configured as follows.
  • the switching control circuit includes the PWM control circuit according to any one of (1) to (7),
  • the modulation signal is an output feedback signal of a switching power supply circuit, and the first modulated signal and the second modulated signal are control signals for the two switching elements.
  • an AC voltage can be generated by an arbitrary pseudo rectangular wave signal having a duty ratio other than 50% with a switching control circuit having a simple circuit configuration.
  • two PWM signals synchronized with the rising edge and falling edge of the square wave signal are generated without forming a complicated logic circuit. Further, since the two PWM signals are synchronized with the rising and falling edges of the square wave signal, the timing difference (phase difference) between the two PWM signals can be freely set.
  • FIG. 1 is a block diagram of a PWM control circuit 101 according to the first embodiment of the present invention.
  • FIG. 2 is a circuit diagram of the PWM control circuit 101.
  • FIG. 3 is a voltage waveform diagram of each part of the PWM control circuit 101.
  • FIG. 4 is a circuit diagram of the PWM control circuit 102 according to the second embodiment.
  • FIG. 5 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off.
  • FIG. 6 is a voltage waveform diagram of each part of the PWM control circuit 102.
  • FIG. 7 is a circuit diagram of the PWM control circuit 103 according to the third embodiment.
  • FIG. 8 is a voltage waveform diagram of each part of the PWM control circuit 103.
  • FIG. 9 is a circuit diagram of the PWM control circuit 104 according to the fourth embodiment.
  • FIG. 10 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off.
  • FIG. 11 is a voltage waveform diagram of each part of the PWM control circuit 104.
  • FIG. 12 is a circuit diagram of the switching power supply device 201 of the fifth embodiment.
  • FIG. 13 is a waveform diagram showing an example of the state of switching elements Q1 and Q2, the square wave signal, and the output voltage to capacitive load Cload in FIG.
  • FIG. 14 is a waveform diagram showing an example of the state of switching elements Q1 and Q2, the square wave signal, and the output voltage to capacitive load Cload in FIG.
  • FIG. 15 is a circuit diagram of the power supply device disclosed in Patent Document 2. In FIG.
  • FIG. 1 is a block diagram of a PWM control circuit 101 according to the first embodiment of the present invention.
  • the PWM control circuit 101 includes a square wave signal input terminal 11 for inputting a square wave signal, a modulation signal input terminal 12, a first modulated signal output terminal 21, and a second modulated signal output terminal 22.
  • the PWM control circuit 101 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42.
  • the second ramp wave generating circuit 32 includes a ramp wave generating circuit 30 and an inverting circuit 29.
  • the first ramp wave generating circuit 31 generates a first ramp wave synchronized with the rising edge of the square wave signal input to the square wave signal input terminal 11.
  • the ramp wave here is a waveform in which the sweep of the potential is started from a predetermined potential, and thereafter it is repeatedly reset to the predetermined potential.
  • the ramp wave generation circuit 30 has the same configuration as that of the first ramp wave generation circuit 31 and generates a ramp wave synchronized with the rising edge of the input signal.
  • the inverting circuit 29 inverts the polarity of the square wave input to the square wave signal input terminal 11. Therefore, the second ramp wave generation circuit 32 generates a second ramp wave that is synchronized with the falling edge of the square wave signal input to the square wave signal input terminal 11.
  • the first comparison circuit 41 compares the first ramp wave with the modulation signal, and inverts the level according to the comparison result to generate the first modulated signal.
  • the second comparison circuit 42 compares the second ramp wave with the modulation signal, and inverts the level according to the comparison result to generate the second modulated signal.
  • FIG. 2 is a circuit diagram of the PWM control circuit 101.
  • the PWM control circuit 101 operates using the power supply Vdc1 as a power supply.
  • the first ramp wave generation circuit 31 includes a constant current circuit CC1, a first capacitor C11, a diode D11, a resistor R12, and a first switch element SW11.
  • the second ramp wave generating circuit 32 includes a constant current circuit CC2, a second capacitor C21, a diode D21, a resistor R22, an inverting circuit 29, and a second switch element SW21.
  • Both the first comparison circuit 41 and the second comparison circuit 42 are constituted by comparators.
  • the constant current circuits CC1 and CC2 are variable impedance type constant current circuits.
  • a first time constant circuit 51 is constituted by the constant current circuit CC1 and the first capacitor C11.
  • a second time constant circuit 52 is configured by the constant current circuit CC2 and the second capacitor C21.
  • the diode D11, the resistor R12, and the first switch element SW11 constitute a first reset circuit 61.
  • a second reset circuit 62 is configured by the diode D21, the resistor R22, and the second switch element SW21.
  • FIG. 3 is a voltage waveform diagram of each part of the PWM control circuit 101.
  • the first switch element SW11 is turned on.
  • the constant current circuit CC1 starts charging the first capacitor C11 with a constant current. Therefore, the potential at the point b is swept and rises. Since the potential of the first capacitor C11 is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the first comparison circuit 41 at the timing t0. (Potential at point e), that is, the first modulated signal is at a high level.
  • the output (potential at the point e) of the first comparison circuit 41 that is, the first One modulated signal is at a low level.
  • the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.
  • the second switch element SW21 is turned on. Thereby, the constant current circuit CC2 starts charging the second capacitor C21 with a constant current. Therefore, the potential at the point c is swept and rises. Since the potential of the second capacitor C21 is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the second comparison circuit 42 at timing t2. (Potential at point f), that is, the second modulated signal is at a high level.
  • the output (potential at the point f) of the second comparison circuit 42 that is, the first The second modulated signal is at a low level.
  • the second modulated signal becomes a high-level rectangular wave signal from timing t2 to t3.
  • the constant current value of the constant current circuit CC1 and the capacitance value of the first capacitor C11 are determined so that the rate of increase of the charging potential (ramp of the ramp wave) of the first capacitor C11 becomes a predetermined value.
  • the constant current value of the constant current circuit CC2 and the capacitance value of the second capacitor C21 are determined such that the rate of increase of the charging potential (ramp of the ramp wave) of the second capacitor C21 becomes a predetermined value.
  • the slopes of the two ramp waves are equal.
  • the first switch element SW11 when the first switch element SW11 is turned off at the timing t2, the charge of the first capacitor C11 is discharged through the path of the diode D11 ⁇ the resistor R12 ⁇ the capacitor C11. However, since the first switch element SW11 is off at this time, the potential at the point b is kept at a high level even during the discharge of the capacitor C11.
  • the value of the resistor R12 is determined so as to have a discharge time constant at which the potential of the first capacitor C11 becomes approximately zero until the next timing t0.
  • the second switch element SW2 when the second switch element SW2 is turned off at the timing t0, the charge of the second capacitor C21 is discharged through the path of the diode D21 ⁇ the resistor R22 ⁇ the capacitor C21. At this time, since the second switch element SW2 is off, the potential at the point c is kept at a high level even during the discharge of the capacitor C21.
  • the value of the resistor R22 is determined so as to have a discharge time constant at which the potential of the second capacitor C21 becomes approximately zero until the next timing t2.
  • the first modulated signal is generated in synchronization with the rising timing of the square wave signal
  • the second modulated signal is generated in synchronization with the falling timing of the square wave signal.
  • the first modulated signal and the second modulated signal can have an arbitrary phase difference other than 180 °.
  • FIG. 4 is a circuit diagram of the PWM control circuit 102 according to the second embodiment.
  • the PWM control circuit 102 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42.
  • the difference from the PWM control circuit 101 shown in FIG. 2 in the first embodiment is that resistors R11 and R21 are provided instead of the constant current circuits CC1 and CC2. That is, in the PWM control circuit 102, the resistor R11 and the first capacitor C11 constitute a first time constant circuit 51. Similarly, a second time constant circuit 52 is configured by the resistor R21 and the second capacitor C21.
  • FIG. 5 is a diagram showing a charging current path when the first switch element SW11 is turned on and a discharge current path when the first switch element SW11 is turned off.
  • a charging current flows through the path of the resistor R11 and the capacitor C11, and the potential of the capacitor C11 increases exponentially.
  • a discharge current flows through the diode D11 and the resistor R12, thereby resetting.
  • FIG. 6 is a voltage waveform diagram of each part of the PWM control circuit 102.
  • the first switch element SW11 is turned on. As a result, charging of the first capacitor C11 is started. Therefore, the potential at the point b is swept and rises exponentially. Since the potential of the first capacitor C11 is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the first comparison circuit 41 at the timing t0. (Potential at point e), that is, the first modulated signal is at a high level.
  • the output (potential at the point e) of the first comparison circuit 41 that is, the first One modulated signal is at a low level.
  • the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.
  • the second switch element SW21 is turned on. Thereby, charging of the second capacitor C21 is started. Therefore, the potential at the point c is swept and rises exponentially. Since the potential of the second capacitor C21 is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output of the second comparison circuit 42 at timing t2. (Potential at point f), that is, the second modulated signal is at a high level.
  • the output (potential at the point f) of the second comparison circuit 42 that is, the first The second modulated signal is at a low level.
  • the second modulated signal becomes a high-level rectangular wave signal from timing t2 to t3.
  • the ramp wave generating circuit is constituted by the CR time constant circuit, the first and second modulated signals subjected to PWM modulation can be generated.
  • FIG. 7 is a circuit diagram of the PWM control circuit 103 according to the third embodiment.
  • the PWM control circuit 103 operates using the power supply Vdc1 as a power supply voltage.
  • the first ramp wave generating circuit 31 includes a constant current circuit CC1, a first capacitor C11, a diode D11, a resistor R12, a first switch element SW11, and an inverting circuit 29.
  • the second ramp wave generation circuit 32 includes a constant current circuit CC2, a second capacitor C21, a diode D21, a resistor R22, and a second switch element SW21.
  • Both the first comparison circuit 41 and the second comparison circuit 42 are constituted by comparators.
  • the first time constant circuit 51 is constituted by the constant current circuit CC1 and the first capacitor C11.
  • a second time constant circuit 52 is configured by the constant current circuit CC2 and the second capacitor C21.
  • resistors R12 and R22 are not resistors that determine a charging time constant.
  • a diode D11 and a first switch element SW11 constitute a first reset circuit 61.
  • a second reset circuit 62 is configured by the diode D21 and the second switch element SW21.
  • the resistor R13 and the diode D12 constitute a first level shift circuit 71.
  • a second level shift circuit 72 is configured by the resistor R23 and the diode D22.
  • FIG. 8 is a voltage waveform diagram of each part of the PWM control circuit 103.
  • the first switch element SW11 is turned off.
  • the constant current circuit CC1 starts charging the first capacitor C11 with a constant current.
  • the potential at the point n rises in a ramp waveform. Since the n-point potential is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential of the p-point) is input to the non-inverting input, the output (r-point) of the first comparison circuit 41 at timing t0. ), That is, the first modulated signal is at a high level.
  • the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.
  • the second switch element SW21 is turned off. Thereby, the constant current circuit CC2 starts charging the second capacitor C21 with a constant current. Therefore, the potential at point o rises in a ramp waveform. Since the potential at the point o is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point q) is input to the non-inverting input, the output (point s) of the second comparison circuit 42 at the timing t2. ), That is, the second modulated signal is at a high level.
  • the second modulated signal becomes a high-level rectangular wave signal from timing t2 to t3.
  • the voltage of the inverting input of the first comparison circuit 41 decreases, but the non-inversion of the first comparison circuit 41
  • the input voltage (potential at point p) is shifted to a low level. In this state, the voltage of the inverting input (potential at the n point) is higher than the voltage of the non-inverting input of the first comparison circuit 41 (potential at the p point) by the drop voltage of the resistor R12. The output remains low.
  • the second switch element SW21 since the second switch element SW21 is in the ON state from timing t0 to t1, the voltage of the inverting input of the second comparison circuit 42 (potential at the point o) decreases, but the non-inverting input of the second comparison circuit 42 Is shifted to a low level. In this state, the voltage at the inverting input (potential at the point o) is higher than the voltage at the non-inverting input (potential at the point q) of the second comparison circuit 42 by the drop voltage of the resistor R22. The output remains low.
  • FIG. 9 is a circuit diagram of the PWM control circuit 104 according to the fourth embodiment.
  • the PWM control circuit 104 includes a first ramp wave generation circuit 31, a second ramp wave generation circuit 32, a first comparison circuit 41, and a second comparison circuit 42.
  • the third embodiment differs from the PWM control circuit 103 shown in FIG. 7 in that resistors R11 and R21 are provided instead of the constant current circuits CC1 and CC2.
  • the resistors R11 and R12 and the first capacitor C11 constitute a first time constant circuit 51.
  • a second time constant circuit 52 is configured by the resistors R21 and R22 and the second capacitor C21.
  • FIG. 10 is a diagram showing a charging current path when the first switch element SW11 is on and a discharge current path when the first switch element SW11 is off.
  • a charging current flows through the path of the resistors R11, R12 and the capacitor C11, and the potential of the capacitor C11 increases exponentially.
  • a discharge current flows through the diode D11 and is reset thereby.
  • FIG. 11 is a voltage waveform diagram of each part of the PWM control circuit 104.
  • the first switch element SW11 is turned off.
  • charging of the first capacitor C11 is started. Therefore, the potential at the point n rises exponentially (substantially in a ramp waveform). Since the n-point potential is input to the inverting input of the first comparison circuit 41 and the voltage of the modulation signal (potential of the p-point) is input to the non-inverting input, the output (r-point) of the first comparison circuit 41 at timing t0. ), That is, the first modulated signal is at a high level.
  • the first modulated signal becomes a high-level rectangular wave signal from timing t0 to timing t1.
  • the second switch element SW21 is turned off. Thereby, charging of the second capacitor C21 is started. Therefore, the potential at point o rises exponentially (substantially in a ramp waveform). Since the potential at the point o is input to the inverting input of the second comparison circuit 42 and the voltage of the modulation signal (potential at the point d) is input to the non-inverting input, the output (point f) of the second comparison circuit 42 at timing t2. ), That is, the second modulated signal is at a high level.
  • the second modulated signal becomes a high-level rectangular wave signal from timing t2 to t3.
  • the ramp wave generating circuit is constituted by the CR time constant circuit, the first and second modulated signals subjected to PWM modulation can be generated.
  • FIG. 12 is a circuit diagram of the switching power supply device 201 of the fifth embodiment.
  • the switching power supply device 201 includes a transformer T, a capacitor Cr, an inductor Lr, driver circuits 211 and 212, switching elements Q1 and Q2, an output feedback circuit 220, an error amplifier 221 and a PWM control circuit 101.
  • the PWM control circuit 101 functions as a switching control circuit that controls the switching elements Q1 and Q2.
  • the PWM control circuit 101 is the PWM control circuit 101 shown in FIG. 1, but may be any of the PWM control circuits 102, 103, and 104 of another embodiment.
  • FIGS. 13 and 14 are waveform diagrams showing the relationship between the states of the switching elements Q1 and Q2, the square wave signal, and the output voltage to the capacitive load Cload in FIG.
  • the output voltage rises during the on period of the low side switching element Q1, and after the low side switching element Q1 is turned off, the output voltage further rises only during the on period of the body diode of the high side switching element Q2. To do. Further, the output voltage decreases during the ON period of the high side switching element Q2, and after the high side switching element Q2 is turned OFF, the output voltage further decreases only during the ON period of the body diode of the low side switching element Q1.
  • the square wave signal input to the square wave signal input terminal 11 is a square wave signal having a frequency of 3 kHz and a duty of 30%.
  • a pseudo rectangular wave AC voltage having a frequency of 3 kHz and a duty of 30% is applied to the capacitive load Cload.
  • the on-time Ton of the switching elements Q1 and Q2 is feedback-controlled so that the amplitude of the output voltage becomes constant according to the output voltage of the output feedback circuit 220 and the error amplifier 221.
  • the duty of the output voltage (pseudo rectangular wave) can be controlled by the ON timing difference between the switching elements Q1 and Q2, that is, the ON period T of the square wave signal.
  • the on-time Ton of the switching elements Q1, Q2 is feedback-controlled.
  • the amplitude of the output voltage is controlled by adjusting the voltage input to the modulation signal input terminal 12.
  • a circuit may be configured.
  • a square wave signal generation circuit is provided externally and a square wave signal is input from the external square wave signal generation circuit.
  • the square wave signal generation circuit is included in the PWM control circuit. May be provided.
  • This square wave signal generating circuit includes, for example, a triangular wave generating circuit and a comparator, and the circuit is configured to set the duty of the square wave signal by controlling a reference signal input to the comparator.
  • the present invention can be applied to a circuit system having high-side and low-side switching elements such as a push-pull system and a half-bridge system.
  • C11 First capacitor
  • C21 Second capacitors CC1, CC2: Constant current circuit Cload ... capacitive load Cr ... resonant capacitors D11, D12, D21, D22 ... diode L1 ... inductor Lr ... resonant inductor Q1 ... low-side switching element Q2 ... high-side switching element SW11 ... first switch element SW21 ... second switch element T ... Transformer Vdc1 ... Power source 11 ... Square wave signal input terminal 12 ... Modulated signal input terminal 21 ... First modulated signal output terminal 22 ... Second modulated signal output terminal 29 ... Inverting circuit 31 ...

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  • Dc-Dc Converters (AREA)
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PCT/JP2014/067324 2013-07-02 2014-06-30 Ｐｗｍ制御回路およびスイッチング電源装置 WO2015002125A1 (ja)

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CN201480027874.4A CN105210285B (zh) 2013-07-02 2014-06-30 Pwm控制电路以及开关电源装置
JP2015525198A JP6115637B2 (ja) 2013-07-02 2014-06-30 Ｐｗｍ制御回路およびスイッチング電源装置

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JP2013138644 2013-07-02

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