WO2015000255A1 - 阵列基板、显示装置及阵列基板的制造方法 - Google Patents

阵列基板、显示装置及阵列基板的制造方法 Download PDF

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Publication number
WO2015000255A1
WO2015000255A1 PCT/CN2013/088384 CN2013088384W WO2015000255A1 WO 2015000255 A1 WO2015000255 A1 WO 2015000255A1 CN 2013088384 W CN2013088384 W CN 2013088384W WO 2015000255 A1 WO2015000255 A1 WO 2015000255A1
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Prior art keywords
layer
gate
via hole
array substrate
substrate
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English (en)
French (fr)
Inventor
阎长江
张家祥
郭建
谢振宇
陈旭
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/386,651 priority Critical patent/US9543324B2/en
Publication of WO2015000255A1 publication Critical patent/WO2015000255A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating an array substrate. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • TFT-LCD display modes mainly include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, and AD-SDS (ADvanced).
  • TN Transmission Nematic
  • VA Very Alignment
  • IPS In-Plane-Switching
  • AD-SDS ADvanced
  • Super Dimension Switch advanced super-dimensional field conversion technology, cartridge ADS
  • the resin passivation layer has the characteristics of flat surface and low dielectric constant, in the actual production of the TFT-LCD array substrate, a resin passivation layer is usually introduced to further increase the aperture ratio and display brightness of the TFT-LCD product, and reduce The signal delay of TFT-LCD products ultimately improves the competitiveness of the product.
  • the array substrate includes: a set of gate scan lines and a set of data scan lines, defined by the set of gate scan lines and a set of data scan lines. Pixel cells arranged in an array.
  • each layer of the array substrate is formed by a patterning process, and each patterning process usually includes processes such as masking, exposure, development, etching, and stripping.
  • An object of the present invention is to provide an array substrate, a display device, and a method for manufacturing an array substrate, which can effectively reduce the manufacturing cost of the array substrate, greatly shorten the manufacturing process, and further improve the yield of the product.
  • An embodiment of the present invention provides an array substrate, including: a substrate substrate and a plurality of pixel units on a substrate of the substrate, each of the pixel units including a thin film transistor unit, wherein
  • the thin film transistor unit includes: a gate electrode on the substrate of the substrate, a gate insulating layer above the gate, an active layer above the gate insulating layer and opposite to the gate position, An ohmic layer over the active layer, a source and a drain over the ohmic layer, and a resin passivation layer over the source and drain and covering the substrate.
  • Another embodiment of the present invention provides a display device comprising the array substrate of the foregoing technical solution.
  • a further embodiment of the present invention provides a method of fabricating an array substrate, including:
  • a resin passivation layer over the source drain metal, the metal lead, and the data scan line and covering the substrate, forming a second via, a third via, and a fourth via of the resin passivation layer by a patterning process, a second via corresponding to a position at which a drain is to be formed, the third via corresponding to a position of the metal lead, and a position at which a channel is formed between the fourth via and the source and the drain Corresponding;
  • the resin passivation layer directly covers the source and drain metal, after the pattern of the source and drain electrodes is formed in the manufacturing process of the array substrate, the fabrication of the channel protective layer is omitted. .
  • the invention effectively reduces the manufacturing cost of the array substrate, greatly shortens the manufacturing process, effectively improves the display brightness of the TFT-LCD product, and improves the yield of the product.
  • FIG. 1 is a schematic cross-sectional view of a pixel unit of an embodiment of an array substrate according to the present invention (taking the ADS mode as an example);
  • FIG. 2 is a schematic cross-sectional view of a pixel unit after forming a gate according to an embodiment of the method of the present invention
  • FIG. 3 is a schematic cross-sectional view showing a pixel unit after forming an active layer and an ohmic layer according to an embodiment of the method of the present invention
  • FIG. 4 is a cross-sectional structural view showing a pixel unit after forming a first via hole of a gate insulating layer according to an embodiment of the method of the present invention
  • FIG. 5 is a schematic cross-sectional view of a pixel unit after forming a source and drain metal according to an embodiment of the method of the present invention
  • FIG. 6 is a schematic top plan view of a pixel unit after forming a source/drain metal according to an embodiment of the method of the present invention
  • FIG. 7 is a schematic cross-sectional view showing a pixel unit after forming a resin passivation layer according to an embodiment of the method of the present invention.
  • FIG. 8 is a schematic top plan view of a pixel unit after forming a resin passivation layer according to an embodiment of the method of the present invention
  • FIG. 9 is a cross-sectional view showing a structure of a pixel unit after forming a transparent conductive metal film according to an embodiment of the method of the present invention.
  • FIG. 10 is a schematic cross-sectional view showing a pixel unit after forming a source, a drain, and a first transparent electrode according to an embodiment of the method of the present invention
  • FIG. 11 is a top plan view showing a pixel unit after forming a source, a drain, and a first transparent electrode according to an embodiment of the method;
  • FIG. 12 is a schematic cross-sectional view showing a pixel unit after forming a second passivation layer according to an embodiment of the method of the present invention. detailed description
  • One of the objects of the present invention is to provide an array substrate, a display device, and a method of fabricating the array substrate.
  • the resin passivation layer of the array substrate directly covers the source and drain metal, in the manufacturing process of the array substrate After the pattern of the source and drain electrodes is formed, the fabrication of the channel protective layer is omitted.
  • the invention can effectively reduce the manufacturing cost of the array substrate, greatly shorten the manufacturing process, and effectively improve the manufacturing process.
  • the array substrate provided by the embodiment of the present invention includes a substrate substrate 1 and a plurality of pixel units located on the substrate 1 (in the figure, a cross section of one pixel unit is taken as an example).
  • the array substrate also includes a GOA unit.
  • Each of the pixel units includes a thin film transistor unit.
  • the GOA unit includes: a first gate 2a (ie, a lead gate gate, hereinafter referred to as a first gate) located on the substrate 1 of the substrate, a gate insulating layer 3 overlying the first gate 2a and covering the substrate, and A metal lead 6c located above the gate insulating layer 3.
  • a first gate 2a ie, a lead gate gate, hereinafter referred to as a first gate
  • a gate insulating layer 3 overlying the first gate 2a and covering the substrate
  • a metal lead 6c located above the gate insulating layer 3.
  • the thin film transistor unit includes: a second gate 2b (ie, a gate of a thin film transistor, hereinafter referred to as a second gate) located above the substrate 1 and located above the gate insulating layer 3 and at the position of the second gate 2b
  • a second gate 2b ie, a gate of a thin film transistor, hereinafter referred to as a second gate
  • the opposite active layer 4 the ohmic layer 5 over the active layer 4, the source 6a and the drain 6b above the ohmic layer 5, and the resin blunt over the source 6a and the drain 6b and covering the substrate Layer 8.
  • the GOA unit is located in a signal guiding area around the substrate.
  • One pixel unit including a thin film transistor unit is schematically illustrated in the drawing and is adjacent to the GOA unit, however, not all of the pixel units are adjacent to the GOA unit.
  • the substrate substrate 1 may be a glass substrate, a plastic substrate or a substrate of other materials.
  • the material of the first gate 2a, the second gate 2b, the source 6a, the drain 6b and the metal lead 6c may be a single layer film of aluminum (A1), phase (Mo) or molybdenum-tungsten alloy (MoW).
  • the material of the gate insulating layer 3 may be silicon nitride.
  • the material of the active layer 4 is amorphous silicon (a-Si).
  • the material of the ohmic layer 5 is a doped semiconductor (n + a-Si).
  • the first gate 2a and the second gate 2b are located in the same layer.
  • the array substrate further includes: a first transparent electrode 9 located on the resin passivation layer 8 , a second passivation layer 10 located above the first transparent electrode 9 and covering the substrate, A second transparent electrode 11 above the second passivation layer 10 and having a slit structure.
  • the material of the first transparent electrode 9 and the second transparent electrode 11 may be indium tin oxide or the like.
  • the second passivation layer 10 may be an inorganic insulating film such as silicon nitride or the like, or an organic insulating film such as a photosensitive resin material or a non-photosensitive resin material.
  • the material of the resin passivation layer 8 is preferably a photosensitive resin material.
  • the resin passivation layer 8 is in direct contact with the source 6a and the drain 6b.
  • the second passivation layer 10 is in direct contact with the active layer.
  • the present invention reduces the array substrate.
  • the cost of production has greatly reduced the manufacturing process.
  • the material of the channel protective layer is usually an inorganic insulating film such as silicon nitride
  • the transmittance of the silicon nitride channel protective layer is 90% for visible light
  • the transmittance of the resin passivation layer is 95%.
  • the array substrate according to the embodiment of the invention further improves the display brightness of the TFT-LCD product, improves the yield of the product, and effectively reduces the power consumption of the TFT-LCD product.
  • the embodiment of the invention provides an array substrate in the ADS mode, which can improve the picture quality of the TFT-LCD product, and has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeezing.
  • the embodiment of the invention further provides a display device comprising any one of the above array substrates.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • Step 301 forming a gate metal film on the substrate 1 and forming a first gate 2a, a second gate 2b, and a gate scan line connected to the second gate 2b by a patterning process (not shown) Out) the graphics.
  • a patterning process not shown
  • the patterning process usually includes the steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist stripping, etc.; the metal layer is usually formed by physical vapor deposition (for example, magnetron sputtering).
  • the pattern is formed by wet etching, and the film is formed by chemical vapor deposition for the non-metal layer, and the pattern is formed by dry etching. The following steps are the same and will not be described again.
  • Step 302 Forming a gate insulating layer 3, an active material layer and an ohmic material layer covering the substrate on the substrate on which the step 301 is completed, and forming the active layer 4 and the ohmic layer 5 by a patterning process.
  • the cross-sectional structure of one pixel unit after forming the active layer 4 and the ohmic layer 5 is shown in Fig. 3.
  • a gate insulating layer 3, an active material layer and an ohmic material layer are sequentially formed over the patterns of the first gate 2a, the second gate 2b and the gate scan line;
  • the active layer 4 and the ohmic layer 5 are formed by a semi-transmissive film patterning process.
  • the material of the active material layer is amorphous silicon (a-Si), and the material of the ohmic layer 5 is a doped semiconductor (n+ a-Si).
  • Step 303 Form a first via hole H1 of the gate insulating layer 3 at a position corresponding to the first gate electrode 2a on the substrate on which the step 302 is completed by a patterning process.
  • the cross-sectional structure of one pixel unit after forming the first via hole HI of the gate insulating layer 3 is shown in FIG.
  • Step 304 Form a data line metal film covering the substrate on the substrate on which the step 303 is completed, and form a pattern of the source and drain metal, a pattern of the metal lead 6c, and a pattern of a data scan line (not shown) by a patterning process.
  • the structure of one pixel unit after forming the source/drain metal is shown in Figs. 5 and 6.
  • the source 6a and the drain 6b are not formed, that is, the channel between the source 6a and the drain 6b is not formed, and the source and drain metal at this time temporarily functions as a channel protective layer, effectively protecting the channel.
  • the TFT characteristics of the channel are not formed, that is, the channel between the source 6a and the drain 6b is not formed, and the source and drain metal at this time temporarily functions as a channel protective layer, effectively protecting the channel.
  • Step 305 Forming a resin passivation layer 8 covering the substrate on the substrate of the completion step 304, forming a second via hole H2, a third via hole H3, and a fourth via hole H4 of the resin passivation layer 8 by a patterning process.
  • the structure of one pixel unit after forming the resin passivation layer 8 is shown in Figs. 7 and 8.
  • the second via hole H2 corresponds to a position where a drain is to be formed
  • the third via hole H3 is located in a signal guiding region of the substrate
  • the third via hole H3 corresponds to a position of the metal lead 6c
  • the fourth The via hole H4 corresponds to a position at which a channel is to be formed between the source 6a and the drain 6b.
  • the material of the channel protective layer is usually made of silicon nitride material. Since the lateral etching rate of the silicon nitride material and the resin material are different, once the silicon nitride channel is under the resin passivation layer 8 The lateral etch rate of the layer is fast, which causes poor via chamfering at the channel.
  • the source 6a and the drain 6b are not formed in step 305, and the active layer 4 at the channel is covered by the source and drain metal, thereby preventing the active layer at the channel from being blunt by the resin. The influence of the layer effectively solves the problem of poor chamfering when the fourth via hole H4 is formed in this step, and improves the yield of the product.
  • Step 306 forming a transparent conductive metal film covering the substrate on the substrate on which step 305 is completed, and forming a source electrode 6a, a drain electrode 6b, a fifth via hole H5 of the ohmic layer 5, and a first transparent electrode 9 by a patterning process.
  • the fifth via hole H5 corresponds to the position of the fourth via hole H4 of the resin passivation layer 8.
  • the material of the transparent conductive metal film may be indium tin oxide or the like.
  • the transparent conductive metal film forming the cover substrate in this step exposes the photoresist 12 to form the source 6a, the drain 6b, and the fifth via hole H5 of the ohmic layer 5 by a semi-transmissive film patterning process.
  • the fifth via hole H5 corresponds to the position of the fourth via hole H4;
  • the first transparent electrode 9 is formed by a gray tone mask patterning process.
  • the structure of the one pixel unit after forming the source 6a, the drain 6b and the first transparent electrode 9 is shown in Figs. 10 and 11 .
  • the first transparent electrode 9 is connected to the metal layer where the drain 6b is to be formed through the second via hole H2.
  • Step 307 Form a second passivation layer 10 covering the substrate on the substrate on which the step 306 is completed, and form a sixth via hole H6 of the second passivation layer 10 in the signal guiding region of the substrate by a patterning process.
  • the cross-sectional structure of one pixel unit after forming the second passivation layer 10 is shown in Fig. 12.
  • Step 308 forming a transparent conductive metal film covering the substrate on the substrate of the step 307, and forming a second transparent electrode 11 having a slit structure by a patterning process.
  • a cross-sectional structure of a pixel unit forming an array substrate of an embodiment of the present invention is shown in Fig. 1.
  • the resin passivation layer 8 is in direct contact with the source 6a and the drain 6b; and the second passivation layer 10 is in direct contact with the active layer.
  • the manufacturing method of the array substrate of the embodiment of the invention eliminates the fabrication of the channel protection layer, reduces the manufacturing cost, and reduces the production process, thereby greatly improving the yield of the product.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)

Abstract

一种阵列基板、显示装置及阵列基板的制造方法。阵列基板包括：衬底基板（1）和位于衬底基板（1）之上的多个像素单元，每个像素单元包括薄膜晶体管单元。薄膜晶体管单元包括：位于衬底基板（1）上的栅极，位于栅极上的栅极绝缘层（3），位于栅极绝缘层（3）上且与栅极位置相对的有源层（4），位于有源层（4）上的欧姆层（5），位于欧姆层（5）上的源极（6a）和漏极（6b），以及位于源极（6a）和漏极（6b）之上并覆盖基板的树脂钝化层（8）。

Description

阵列基板、 显示装置及阵列基板的制造方法 技术领域
本发明的实施例涉及一种阵列基板、 显示装置及阵列基板的制造方法。 背景技术
在平板显示装置中， 薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗低、 制造成本相对较低和无辐 射等特点， 在当前的平板显示装置市场占据了主导地位。
目前， TFT-LCD的显示模式主要有 TN ( Twisted Nematic, 扭曲向列 ) 模式、 VA ( Vertical Alignment, 垂直取向）模式、 IPS ( In-Plane-Switching, 平面方向转换）模式和 AD-SDS ( ADvanced Super Dimension Switch , 高级超 维场转换技术， 筒称 ADS )模式等。
由于树脂钝化层具有表面平坦， 低介电常数的特点， 因此， 在 TFT-LCD 阵列基板的实际生产中， 通常引入树脂钝化层以进一步提高 TFT-LCD产品 的开口率和显示亮度， 降低 TFT-LCD产品的信号延迟， 最终提高产品的竟 争力。
以 ADS模式的 TFT-LCD阵列基板为例， 该阵列基板包括： 一组栅极扫 描线和一组数据扫描线， 由所述一组栅极扫描线和一组数据扫描线所界定的 多个呈阵列状排布的像素单元。 通常阵列基板的各个图层都是通过构图工艺 形成的， 而每一次构图工艺通常包括掩模、 曝光、 显影、 刻蚀和剥离等工序。
现有阵列基板在制作过程中， 形成源极和漏极之后， 依次形成沟道保护 层（用于保护沟道）和树脂钝化层， 因此， 阵列基板的制造成本较高， 且制 造工艺较为复杂， 容易导致产品缺陷。 发明内容
本发明的目的之一是提供一种阵列基板、 显示装置及阵列基板的制造方 法， 能够有效地降低阵列基板的制作成本， 大大地筒化制造工艺， 进一步提 高产品的良品率。 本发明的一个实施例提供一种阵列基板， 包括： 村底基板和位于村底基 板之上的多个像素单元， 每个像素单元包括薄膜晶体管单元， 其中，
薄膜晶体管单元包括： 位于村底基板之上的栅极， 位于所述栅极之上的 栅极绝缘层， 位于所述栅极绝缘层之上且与所述栅极位置相对的有源层， 位 于所述有源层之上的欧姆层， 位于所述欧姆层之上的源极和漏极以及位于所 述源极和漏极之上并覆盖基板的树脂钝化层。
本发明的另一个实施例提供一种显示装置， 包括前述技术方案所述的阵 列基板。
本发明的再一个实施例提供一种阵列基板的制造方法， 包括：
形成位于有源层和欧姆层之上并覆盖基板的数据线金属薄膜， 通过构图 工艺形成源漏极金属、 金属引线和数据扫描线；
形成位于源漏极金属、 金属引线和数据扫描线之上并覆盖基板的树脂钝 化层， 通过构图工艺形成树脂钝化层的第二过孔、 第三过孔和第四过孔， 所 述第二过孔与要形成漏极的位置相对应， 所述第三过孔与所述金属引线的位 置相对应， 所述第四过孔与源极和漏极之间要形成沟道的位置相对应；
形成位于树脂钝化层之上并覆盖基板的透明导电金属薄膜， 通过构图工 艺形成源极、 漏极、 欧姆层的第五过孔和第一透明电极， 所述第五过孔与所 述第四过孔的位置相对应。
在本发明实施例的技术方案中， 由于树脂钝化层直接覆盖源漏极金属， 因此， 在阵列基板的制造过程中， 形成源漏极金属的图形之后， 省去了沟道 保护层的制作。 本发明有效地降低了阵列基板的制作成本， 大大地筒化了制 造工艺， 有效地提高了 TFT-LCD产品的显示亮度， 提高了产品的良品率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明阵列基板一实施例的一个像素单元的截面结构示意图 （以 ADS模式为例） ；
图 2 为本发明方法一实施例形成栅极后一个像素单元的截面结构示意 图；
图 3为本发明方法一实施例形成有源层和欧姆层后一个像素单元的截面 结构示意图；
图 4为本发明方法一实施例形成栅极绝缘层第一过孔后一个像素单元的 截面结构示意图；
图 5为本发明方法一实施例形成源漏极金属后一个像素单元的截面结构 示意图；
图 6为本发明方法一实施例形成源漏极金属后一个像素单元的俯视结构 示意图；
图 7为本发明方法一实施例形成树脂钝化层后一个像素单元的截面结构 示意图；
图 8为本发明方法一实施例形成树脂钝化层后一个像素单元的俯视结构 示意图；
图 9为本发明方法一实施例形成透明导电金属薄膜后一个像素单元的截 面结构示意图；
图 10为本发明方法一实施例形成源极、漏极和第一透明电极后一个像素 单元的截面结构示意图；
图 11为本发明方法一实施例形成源极、漏极和第一透明电极后一个像素 单元的俯视结构示意图；
图 12 为本发明方法一实施例形成第二钝化层后一个像素单元的截面结 构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的目的之一是提供一种阵列基板、 显示装置及阵列基板的制造方 法。 该阵列基板的树脂钝化层直接覆盖源漏极金属， 在阵列基板的制造过程 中， 形成源漏极金属的图形之后， 省去了沟道保护层的制作。 本发明能够有 效地降低了阵列基板的制作成本， 大大地筒化了制造工艺， 有效地提高了
TFT-LCD产品的良品率。
如图 1所示的实施例， 本发明实施例提供的阵列基板， 包括村底基板 1 和位于村底基板 1之上的多个像素单元（图中以一个像素单元的截面为例）。 该阵列基板还包括 GOA单元。 每个像素单元包括薄膜晶体管单元。
GOA单元包括： 位于村底基板 1之上的第一栅极 2a (即引线区栅极， 以下称第一栅极），位于第一栅极 2a之上并覆盖基板的栅极绝缘层 3以及位 于栅极绝缘层 3之上的金属引线 6c。 薄膜晶体管单元包括： 位于村底基板 1 之上的第二栅极 2b (即薄膜晶体管的栅极， 以下称第二栅极）， 位于栅极绝 缘层 3之上且与第二栅极 2b位置相对的有源层 4,位于有源层 4之上的欧姆 层 5, 位于欧姆层 5之上的源极 6a和漏极 6b以及位于源极 6a和漏极 6b之 上并覆盖基板的树脂钝化层 8。
例如， GOA单元位于基板周边的信号引导区。 附图中示意性地示出包括 薄膜晶体管单元的一个像素单元且该像素单元与 GOA单元相邻， 然而， 并 非所有像素单元均与 GOA单元相邻。
本发明的实施例中， 所述村底基板 1可以为玻璃基板、 塑料基板或其他 材料的基板。 所述第一栅极 2a、 第二栅极 2b、 源极 6a、 漏极 6b和金属引线 6c的材质可以为铝（A1 ) 、 相 （Mo )或钼钨合金 ( MoW ) 的单层膜。 栅极 绝缘层 3的材质可以为氮化硅。 有源层 4的材质为非晶硅（ a-Si )。 欧姆层 5 的材质为掺杂质半导体（n+ a-Si ) 。
所述第一栅极 2a和第二栅极 2b位于同一图层。
如图 1所示， 所述阵列基板还包括： 位于所述树脂钝化层 8之上的第一 透明电极 9, 位于第一透明电极 9之上并覆盖基板的第二钝化层 10, 位于第 二钝化层 10之上且具有狭缝结构的第二透明电极 11。
第一透明电极 9和第二透明电极 11的材质可以为氧化铟锡等。第二钝化 层 10可以采用无机绝缘膜， 例如氮化硅等， 或有机绝缘膜， 例如感光树脂材 料或者非感光树脂材料等。
树脂钝化层 8的材质优选感光树脂材料。
例如， 树脂钝化层 8与源极 6a和漏极 6b直接接触。 例如， 第二钝化层 10与有源层直接接触。
本发明实施例所提供的阵列基板中， 由于树脂钝化层 8位于与源极 6a 和漏极 6b之上且层叠接触， 省去了沟道保护层的制作， 因此， 本发明降低了 阵列基板的制作成本， 大大地筒化了制造工艺。 同时， 由于沟道保护层材质 通常采用无机绝缘膜， 例如氮化硅等， 对于可见光， 氮化硅沟道保护层的透 过率为 90%, 树脂钝化层的透过率为 95%。 本发明实施例所述的阵列基板进 一步提高了 TFT-LCD产品的显示亮度， 提高了产品的良品率， 有效地降低 了 TFT-LCD产品的功耗。
本发明实施例提供的是 ADS模式下的阵列基板， 可以提高 TFT-LCD产 品的画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低 色差、 无挤压水波纹（ push Mura )等优点。
本发明实施例还提供了一种显示装置， 其包括上述任意一种阵列基板。 所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产 品或部件。
根据本发明实施例的阵列基板的制造方法包括：
步骤 301: 在村底基板 1上形成栅金属薄膜， 通过构图工艺形成第一栅 极 2a、 第二栅极 2b和与所述第二栅极 2b相连接的栅极扫描线 (图中未示出） 的图形。 形成栅极后一个像素单元的截面结构参照图 2所示。
一次构图工艺通常包括基板清洗、 成膜、 光刻胶涂覆、 曝光、 显影、 刻 蚀、 光刻胶剥离等工序； 对于金属层通常采用物理气相沉积方式（例如磁控 溅射法）成膜， 通过湿法刻蚀形成图形， 而对于非金属层通常采用化学气相 沉积方式成膜， 通过干法刻蚀形成图形， 以下步骤道理相同， 不再赘述。
步骤 302:在完成步骤 301的基板上形成覆盖基板的栅极绝缘层 3、有源 材料层和欧姆材料层，通过构图工艺形成有源层 4和欧姆层 5。形成有源层 4 和欧姆层 5后一个像素单元的截面结构参照图 3所示。
该步骤中优选的， 依次形成位于第一栅极 2a、 第二栅极 2b和栅极扫描 线的图形之上的栅极绝缘层 3、 有源材料层和欧姆材料层；
通过半透膜构图工艺形成有源层 4和欧姆层 5。 有源材料层材质为非晶 硅 (a-Si ) , 欧姆层 5的材质为掺杂质半导体 (n+ a-Si)。 步骤 303: 在完成步骤 302的基板上通过构图工艺在与第一栅极 2a相对 应的位置形成栅极绝缘层 3的第一过孔 Hl。 形成栅极绝缘层 3的第一过孔 HI后一个像素单元的截面结构参照图 4所示。
步骤 304: 在完成步骤 303的基板上形成覆盖基板的数据线金属薄膜， 通过构图工艺形成源漏极金属的图形、 金属引线 6c的图形和数据扫描线 (图 中未示出）的图形。形成源漏极金属后一个像素单元的结构参照图 5和图 6所 示。
该步骤没有形成源极 6a和漏极 6b工艺， 即未形成源极 6a和漏极 6b之 间的沟道， 此时的源漏极金属暂时起到了沟道保护层的作用， 有效的保护了 沟道的 TFT特性。
步骤 305:在完成步骤 304的基板上形成覆盖基板的树脂钝化层 8,通过 构图工艺形成树脂钝化层 8的第二过孔 H2、 第三过孔 H3和第四过孔 H4。 形成树脂钝化层 8后一个像素单元的结构参照图 7和图 8所示。
第二过孔 H2对应于要形成漏极的位置，所述第三过孔 H3位于基板的信 号引导区， 所述第三过孔 H3与所述金属引线 6c的位置相对应， 所述第四过 孔 H4与源极 6a和漏极 6b之间要形成沟道的位置相对应。
在现有技术中， 沟道保护层的材质通常采用氮化硅材料， 由于氮化硅材 料和树脂材料横向刻蚀速率不一样， 一旦位于树脂钝化层 8之下的氮化硅沟 道保护层横向刻蚀速率快， 就会造成沟道处的过孔倒角不良。 在本发明的实 施例中， 在步骤 305中未形成源极 6a和漏极 6b, 沟道处的有源层 4被源漏 极金属所覆盖， 避免了沟道处的有源层受树脂钝化层的影响， 有效地解决了 该步骤中制作第四过孔 H4时倒角不良的问题， 提高了产品的良品率。
步骤 306:在完成步骤 305的基板上形成覆盖基板的透明导电金属薄膜， 通过构图工艺形成源极 6a、 漏极 6b、 欧姆层 5的第五过孔 H5和第一透明电 极 9。
所述第五过孔 H5与所述树脂钝化层 8的第四过孔 H4的位置相对应。透 明导电金属薄膜的材质可以为氧化铟锡等。
例如， 如图 9所示， 该步骤中形成覆盖基板的透明导电金属薄膜通过半 透膜构图工艺将光刻胶 12曝光形成源极 6a、 漏极 6b和欧姆层 5的第五过孔 H5, 所述第五过孔 H5与所述第四过孔 H4的位置相对应； 通过灰色调掩膜构图工艺形成第一透明电极 9。 形成源极 6a、 漏极 6b 和第一透明电极 9后一个像素单元的结构参照图 10和图 11所示。 第一透明 电极 9通过第二过孔 H2与将要形成漏极 6b的金属层连接。
步骤 307: 在完成步骤 306的基板上形成覆盖基板的第二钝化层 10, 通 过构图工艺在基板的信号引导区形成第二钝化层 10的第六过孔 H6。 形成第 二钝化层 10后一个像素单元的截面结构参照图 12所示。
步骤 308:在完成步骤 307的基板上形成覆盖基板的透明导电金属薄膜， 通过构图工艺形成具有狭缝结构的第二透明电极 11。形成本发明实施例阵列 基板的一个像素单元的截面结构参照图 1所示。
例如，在上述制造方法中，树脂钝化层 8与源极 6a和漏极 6b直接接触； 第二钝化层 10与有源层直接接触。
可见， 本发明实施例阵列基板的制造方法省去了沟道保护层的制作， 降 低了制造成本， 筒化了生产工艺， 大大提升了产品的良品率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板，包括：村底基板和位于村底基板之上的多个像素单元， 每个像素单元包括薄膜晶体管单元， 其中，
薄膜晶体管单元包括： 位于村底基板之上的栅极， 位于所述栅极之上的 栅极绝缘层， 位于所述栅极绝缘层之上且与所述栅极位置相对的有源层， 位 于所述有源层之上的欧姆层， 位于所述欧姆层之上的源极和漏极以及位于所 述源极和漏极之上并覆盖基板的树脂钝化层。
2、如权利要求 1所述的阵列基板，还包括： 位于所述树脂钝化层之上的 第一透明电极， 位于所述第一透明电极之上并覆盖基板的第二钝化层， 位于 所述第二钝化层之上且具有狭缝结构的第二透明电极。
3、如权利要求 1或 2所述的阵列基板， 其中， 所述树脂钝化层的材质为 感光树脂。
4、 如权利要求 1-3任一项所述的阵列基板， 其中， 所述树脂钝化层直接 接触所述源极和所述漏极， 并具有露出所述源极和所述漏极之间的沟道的过 孔。
5、如权利要求 2所述的阵列基板， 其中， 所述第二钝化层直接接触所述 有源层。
6、 如权利要求 1-5任一项所述的阵列基板， 还包括行驱动单元， 所述行 驱动单元包括： 位于所述村底基板之上的引线区栅极， 所述栅极绝缘层覆盖 于所述引线区栅极之上， 以及位于所述栅极绝缘层之上的金属引线。
7、 一种显示装置， 包括如权利要求 1-6中任一项所述的阵列基板。
8、 一种阵列基板的制造方法， 包括：
形成位于有源层和欧姆层之上并覆盖基板的数据线金属薄膜， 通过构图 工艺形成源漏极金属、 金属引线和数据扫描线；
形成位于源漏极金属、 金属引线和数据扫描线之上并覆盖基板的树脂钝 化层， 通过构图工艺形成树脂钝化层的第二过孔、 第三过孔和第四过孔， 所 述第二过孔与要形成漏极的位置相对应， 所述第三过孔与所述金属引线的位 置相对应， 所述第四过孔与源极和漏极之间要形成沟道的位置相对应；
形成位于树脂钝化层之上并覆盖基板的透明导电金属薄膜， 通过构图工 艺形成源极、 漏极、 欧姆层的第五过孔和第一透明电极， 所述第五过孔与所 述第四过孔的位置相对应。
9、如权利要求 8所述的阵列基板的制造方法， 其中， 所述形成位于有源 层和欧姆层之上并覆盖基板的数据线金属薄膜， 通过构图工艺形成源漏极金 属、 金属引线和数据扫描线之前， 该方法还包括：
在村底基板上形成栅金属薄膜， 通过构图工艺形成第一栅极、 第二栅极 和与所述第二栅极相连接的栅极扫描线的图形； 所述第一栅极位于所述金属 引线下方， 所述第二栅极位于所述有源层下方；
形成位于第一栅极、 第二栅极和栅极扫描线的图形之上的栅极绝缘层、 有源材料层和欧姆材料层， 通过构图工艺形成有源层和欧姆层；
通过构图工艺在与第一栅极相对应的位置形成栅极绝缘层的第一过孔。
10、 如权利要求 8或 9所述的阵列基板的制造方法， 其中， 所述形成位 于树脂钝化层之上并覆盖基板的透明导电金属薄膜,通过构图工艺形成源极、 漏极、 欧姆层的第五过孔和第一透明电极， 所述第五过孔与所述第四过孔的 位置相对应之后， 还包括：
形成位于第一透明电极之上并覆盖基板的第二钝化层， 通过构图工艺在 对应于所述第三过孔的位置形成第二钝化层的第六过孔。
11、 如权利要求 10所述的阵列基板的制造方法， 还包括：
形成位于第二钝化层之上并覆盖基板的透明导电金属薄膜， 通过构图工 艺形成具有狭缝结构的第二透明电极。
12、 如权利要求 9所述的阵列基板的制造方法， 其中， 所述形成位于第 一栅极、 第二栅极和栅极扫描线的图形之上的栅极绝缘层、 有源材料层和欧 姆材料层， 通过构图工艺形成有源层和欧姆层包括：
依次形成位于第一栅极、 第二栅极和与所述第二栅极相连接的栅极扫描 线的图形之上的栅极绝缘层、 有源材料层和欧姆材料层；
通过半透膜构图工艺形成有源层和欧姆层。
13、 如权利要求 8-12任一项所述的阵列基板的制造方法， 其中， 所述形 成位于树脂钝化层之上并覆盖基板的透明导电金属薄膜， 通过构图工艺形成 源极、 漏极、 欧姆层的第五过孔和第一透明电极， 所述第五过孔与所述第四 过孔位置相对应包括： 形成位于树脂钝化层之上并覆盖基板的透明导电金属薄膜， 通过半透膜 构图工艺形成源极、 漏极和欧姆层的第五过孔， 所述第五过孔与所述第四过 孔的位置相对应；
通过灰色调掩膜构图工艺形成第一透明电极。
14、 如权利要求 8-13任一项所述的阵列基板的制造方法， 其中， 所述树 脂钝化层直接接触所述源极和漏极。
15、 如权利要求 8-14任一项所述的阵列基板的制造方法， 其中， 所述树 脂钝化层的材质为感光树脂。
PCT/CN2013/088384 2013-07-03 2013-12-03 阵列基板、显示装置及阵列基板的制造方法 Ceased WO2015000255A1 (zh)

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