WO2014206181A1 - Moniteur et appareil d'échange de données à mémoire multi-mcu pour celui-ci - Google Patents

Moniteur et appareil d'échange de données à mémoire multi-mcu pour celui-ci Download PDF

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Publication number
WO2014206181A1
WO2014206181A1 PCT/CN2014/079150 CN2014079150W WO2014206181A1 WO 2014206181 A1 WO2014206181 A1 WO 2014206181A1 CN 2014079150 W CN2014079150 W CN 2014079150W WO 2014206181 A1 WO2014206181 A1 WO 2014206181A1
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WO
WIPO (PCT)
Prior art keywords
mcu
memory
mcus
spi
exchange device
Prior art date
Application number
PCT/CN2014/079150
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English (en)
Chinese (zh)
Inventor
马锐
易明生
Original Assignee
深圳市科曼医疗设备有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市科曼医疗设备有限公司 filed Critical 深圳市科曼医疗设备有限公司
Publication of WO2014206181A1 publication Critical patent/WO2014206181A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the invention relates to the field of medical equipment, in particular to a monitor and a multi-MCU memory data exchange device thereof.
  • MCUs Micro Control Unit
  • Control Unit Micro Control Unit
  • one MCU handles tasks with low real-time requirements, such as data storage, user interaction, etc., and the other handles high-time work such as high-speed drawing and decoding.
  • a certain high-speed communication mechanism is inevitable between the two MCUs.
  • the usual practice is to share the same piece of memory, mutually exclusive access, and use the memory bus to achieve a higher data transfer rate.
  • the solution of using shared memory is generally to directly connect two or more MCUs and the same memory chip by using a memory bus, so that a large number of addresses and data buses are necessary to be directly connected through the memory bus, and the physical connection is complicated.
  • the board requirements are high.
  • the control is more complicated, and it takes a lot of system overhead to control, and the system efficiency is low.
  • a multi-MCU memory data exchange device includes at least two MCUs, an SPI bus and at least two memories, wherein the MCUs are connected to each other through the SPI bus, and the MCUs are independently connected to the memory;
  • the SPI bus is a direct memory access (Direct Memory In the SPI bus in the Access, DMA) mode, the memory connected to the MCU exchanges data with each other through the SPI bus in the DMA mode.
  • DMA Direct Memory In the SPI bus in the Access
  • the sizes of the memories are equal. In one of the embodiments, the memory is a separate memory area partitioned within the MCU.
  • the memory is a memory chip disposed outside the MCU and connected to the MCU.
  • the multi-MCU memory data exchange device further includes a power source connected to the MCU.
  • the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
  • the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters and an LVDS bus, and the MCU is connected to the SPI/LVDS converter through the SPI bus, each of two The SPI/LVDS converters are connected by the LVDS bus.
  • a monitor comprising a multi-MCU memory data exchange device as described above.
  • the above multiple MCU memory data exchange device The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus.
  • the SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds).
  • a fixed clock frequency for example, 100 milliseconds.
  • MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI
  • the DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
  • FIG. 1 is a schematic structural diagram of a first embodiment of the multi-MCU memory data exchange device
  • FIG. 2 is a schematic structural diagram of a second embodiment of the multi-MCU memory data exchange device.
  • a multi-MCU memory data exchange device includes at least two MCUs 100, an SPI bus 200, and at least two memories 300.
  • the MCUs 100 are connected to each other through the SPI bus 200, and the MCUs 100 are independently connected.
  • the SPI bus 200 is an SPI bus in the DMA mode, and the memory 300 connected to the MCU 100 exchanges data with each other through the SPI bus in the DMA mode.
  • the SPI bus is a synchronous serial peripheral interface that allows the MCU to communicate with various peripheral devices in a serial manner to exchange information. Its hardware functions are very powerful, so the software related to SPI is quite simple, and the MCU can handle it. More other things. DMA direct memory access technology is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on the large interrupt load of the MCU.
  • the above multiple MCU memory data exchange device The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus.
  • the SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds).
  • a fixed clock frequency for example, 100 milliseconds.
  • MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI
  • the DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
  • the sizes of the memories are equal.
  • the memory is a separate memory area partitioned within the MCU.
  • the memory is an independent memory area divided in the MCU, and the memory is directly disposed in the MCU, which simplifies the structure of the multi-MCU memory data exchange device, and improves the data exchange rate between the MCU and the memory. It is beneficial to increase the speed of data transmission by the multi-MCU memory data exchange device.
  • the memory is a memory chip disposed outside the MCU and connected to the MCU.
  • the memory is a memory chip that is external to the MCU.
  • the chip size can be changed according to the needs of actual use.
  • the maximum memory size is not limited by the performance of the MCU, and meets the actual use requirements in many different situations.
  • the multi-MCU memory data exchange device further includes a power supply 400 connected to the MCU 100.
  • a power supply 400 is used to power the devices of the multi-MCU memory data exchange device.
  • the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
  • the clk data line, the nss data line, the mosi data line and the miso data line are the four data lines used by the SPI.
  • the basic functions of the SPI can be realized by using the above four data lines, so in the embodiment, the SPI bus includes clk.
  • the data line, nss data line, mosi data line, and miso data line can minimize the structure and reduce the implementation cost while ensuring the basic functions of the SPI.
  • the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters 500 and an LVDS bus 600 through which the MCU 100 communicates with the SPI/ The LVDS converter 500 is connected, and each of the two SPI/LVDS converters 500 is connected through the LVDS bus 600.
  • the efficient communication distance of the SPI bus is only 50cm, when the two MCUs are far apart, multiple SPI bus connections are required.
  • at least two SPI/LVDS converters and an LVDS bus are provided.
  • two MCUs are first connected to the SPI/LVDS converter through the SPI bus, respectively.
  • the /LVDS converters are connected via an LVDS bus.
  • the SPI/LVDS converter and the LVDS bus can be multiple so that the MCUs can be connected over the SPI bus at greater distances.
  • the SPI/LVDS converter can be a converter of other signals and SPI, and the converter is connected by a bus of the signal.
  • a monitor comprising a multi-MCU memory data exchange device as described above.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un moniteur et un appareil d'échange de données à mémoire multi-MCU pour celui-ci, lesquels comprennent au moins deux MCU (100), un bus SPI (200), et au moins deux mémoires (300). Les MCU (100) sont connectées les unes aux autres via le bus SPI (200). Les MCU (100) sont respectivement et indépendamment connectées aux mémoires (300). Le bus SPI (200) est un bus SPI (200) en mode DMA, et les mémoires (300) connectées aux MCU (100) échangent des données les unes avec les autres via le bus SPI (200) en mode DMA. Le moniteur et l'appareil associé d'échange de données à mémoire multi-CMU échangent automatiquement des données dans les mémoires (300) respectivement connectées aux MCU (100) à une fréquence d'horloge fixe. Pour les MCU (100), les données qui doivent être échangées doivent simplement être placées dans les mémoires respectives (300) à une telle fréquence d'horloge fixe de manière à atteindre un objectif de communication à grande vitesse; en outre, les MCU sont connectés via le bus SPI (200). L'appareil possède un câblage simple dans son ensemble. Étant donné que l'on utilise un mode DMA SPI, l'intervention d'une MCU n'est pas requise, de sorte qu'une charge de travail du système est allégée et que l'efficacité du système est améliorée.
PCT/CN2014/079150 2013-06-28 2014-06-04 Moniteur et appareil d'échange de données à mémoire multi-mcu pour celui-ci WO2014206181A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310271914.7 2013-06-28
CN201310271914.7A CN103345455B (zh) 2013-06-28 2013-06-28 监护仪及其多mcu内存数据交换装置

Publications (1)

Publication Number Publication Date
WO2014206181A1 true WO2014206181A1 (fr) 2014-12-31

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CN (1) CN103345455B (fr)
WO (1) WO2014206181A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
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CN103345455B (zh) * 2013-06-28 2016-03-30 深圳市科曼医疗设备有限公司 监护仪及其多mcu内存数据交换装置
CN112416832A (zh) * 2020-11-06 2021-02-26 光华临港工程应用技术研发(上海)有限公司 基于mips架构处理器的通信系统

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