WO2014206181A1 - Patent monitor and multi-mcu memory data exchange device for same - Google Patents

Patent monitor and multi-mcu memory data exchange device for same Download PDF

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Publication number
WO2014206181A1
WO2014206181A1 PCT/CN2014/079150 CN2014079150W WO2014206181A1 WO 2014206181 A1 WO2014206181 A1 WO 2014206181A1 CN 2014079150 W CN2014079150 W CN 2014079150W WO 2014206181 A1 WO2014206181 A1 WO 2014206181A1
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mcu
memory
mcus
spi
exchange device
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PCT/CN2014/079150
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French (fr)
Chinese (zh)
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马锐
易明生
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深圳市科曼医疗设备有限公司
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Publication of WO2014206181A1 publication Critical patent/WO2014206181A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Definitions

  • the invention relates to the field of medical equipment, in particular to a monitor and a multi-MCU memory data exchange device thereof.
  • MCUs Micro Control Unit
  • Control Unit Micro Control Unit
  • one MCU handles tasks with low real-time requirements, such as data storage, user interaction, etc., and the other handles high-time work such as high-speed drawing and decoding.
  • a certain high-speed communication mechanism is inevitable between the two MCUs.
  • the usual practice is to share the same piece of memory, mutually exclusive access, and use the memory bus to achieve a higher data transfer rate.
  • the solution of using shared memory is generally to directly connect two or more MCUs and the same memory chip by using a memory bus, so that a large number of addresses and data buses are necessary to be directly connected through the memory bus, and the physical connection is complicated.
  • the board requirements are high.
  • the control is more complicated, and it takes a lot of system overhead to control, and the system efficiency is low.
  • a multi-MCU memory data exchange device includes at least two MCUs, an SPI bus and at least two memories, wherein the MCUs are connected to each other through the SPI bus, and the MCUs are independently connected to the memory;
  • the SPI bus is a direct memory access (Direct Memory In the SPI bus in the Access, DMA) mode, the memory connected to the MCU exchanges data with each other through the SPI bus in the DMA mode.
  • DMA Direct Memory In the SPI bus in the Access
  • the sizes of the memories are equal. In one of the embodiments, the memory is a separate memory area partitioned within the MCU.
  • the memory is a memory chip disposed outside the MCU and connected to the MCU.
  • the multi-MCU memory data exchange device further includes a power source connected to the MCU.
  • the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
  • the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters and an LVDS bus, and the MCU is connected to the SPI/LVDS converter through the SPI bus, each of two The SPI/LVDS converters are connected by the LVDS bus.
  • a monitor comprising a multi-MCU memory data exchange device as described above.
  • the above multiple MCU memory data exchange device The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus.
  • the SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds).
  • a fixed clock frequency for example, 100 milliseconds.
  • MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI
  • the DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
  • FIG. 1 is a schematic structural diagram of a first embodiment of the multi-MCU memory data exchange device
  • FIG. 2 is a schematic structural diagram of a second embodiment of the multi-MCU memory data exchange device.
  • a multi-MCU memory data exchange device includes at least two MCUs 100, an SPI bus 200, and at least two memories 300.
  • the MCUs 100 are connected to each other through the SPI bus 200, and the MCUs 100 are independently connected.
  • the SPI bus 200 is an SPI bus in the DMA mode, and the memory 300 connected to the MCU 100 exchanges data with each other through the SPI bus in the DMA mode.
  • the SPI bus is a synchronous serial peripheral interface that allows the MCU to communicate with various peripheral devices in a serial manner to exchange information. Its hardware functions are very powerful, so the software related to SPI is quite simple, and the MCU can handle it. More other things. DMA direct memory access technology is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on the large interrupt load of the MCU.
  • the above multiple MCU memory data exchange device The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus.
  • the SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds).
  • a fixed clock frequency for example, 100 milliseconds.
  • MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI
  • the DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
  • the sizes of the memories are equal.
  • the memory is a separate memory area partitioned within the MCU.
  • the memory is an independent memory area divided in the MCU, and the memory is directly disposed in the MCU, which simplifies the structure of the multi-MCU memory data exchange device, and improves the data exchange rate between the MCU and the memory. It is beneficial to increase the speed of data transmission by the multi-MCU memory data exchange device.
  • the memory is a memory chip disposed outside the MCU and connected to the MCU.
  • the memory is a memory chip that is external to the MCU.
  • the chip size can be changed according to the needs of actual use.
  • the maximum memory size is not limited by the performance of the MCU, and meets the actual use requirements in many different situations.
  • the multi-MCU memory data exchange device further includes a power supply 400 connected to the MCU 100.
  • a power supply 400 is used to power the devices of the multi-MCU memory data exchange device.
  • the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
  • the clk data line, the nss data line, the mosi data line and the miso data line are the four data lines used by the SPI.
  • the basic functions of the SPI can be realized by using the above four data lines, so in the embodiment, the SPI bus includes clk.
  • the data line, nss data line, mosi data line, and miso data line can minimize the structure and reduce the implementation cost while ensuring the basic functions of the SPI.
  • the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters 500 and an LVDS bus 600 through which the MCU 100 communicates with the SPI/ The LVDS converter 500 is connected, and each of the two SPI/LVDS converters 500 is connected through the LVDS bus 600.
  • the efficient communication distance of the SPI bus is only 50cm, when the two MCUs are far apart, multiple SPI bus connections are required.
  • at least two SPI/LVDS converters and an LVDS bus are provided.
  • two MCUs are first connected to the SPI/LVDS converter through the SPI bus, respectively.
  • the /LVDS converters are connected via an LVDS bus.
  • the SPI/LVDS converter and the LVDS bus can be multiple so that the MCUs can be connected over the SPI bus at greater distances.
  • the SPI/LVDS converter can be a converter of other signals and SPI, and the converter is connected by a bus of the signal.
  • a monitor comprising a multi-MCU memory data exchange device as described above.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
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  • Bus Control (AREA)

Abstract

A patient monitor and a multi-MCU memory data exchange device for same comprise at least two MCUs (100), an SPI bus (200), and at least two memories (300). The MCUs (100) are connected to each other through the SPI bus (200). The MCUs (100) are each independently connected to the memories (300). The SPI bus (200) is an SPI bus (200) in DMA mode, and the memories (300) connected to the MCUs (100) exchange data with each other through the SPI bus (200) in DMA mode. The patient monitor and the multi-MCU memory data exchange apparatus of same automatically exchange data in the memories (300) respectively connected to the MCUs (100) at a fixed clock frequency. For the MCUs (100), data that needs to be exchanged only needs to be placed in the respective memories (300) at such a fixed clock frequency, so as to achieve the objective of high speed communication; in addition, as the MCUs (100) are connected through the SPI bus (200), wiring of the entire apparatus is simple. Because an SPI DMA mode is used, the intervention of an MCU is not needed, so that a system overhead is lowered and system efficiency is enhanced.

Description

监护仪及其多MCU内存数据交换装置 Monitor and its multi-MCU memory data exchange device
【技术领域】[Technical Field]
本发明涉及医疗设备领域，特别是涉及监护仪及其多MCU内存数据交换装置。The invention relates to the field of medical equipment, in particular to a monitor and a multi-MCU memory data exchange device thereof.
【背景技术】【Background technique】
目前为了满足监护仪中系统对实时性能的高要求，在一个系统里会使用到两个或两个以上MCU （Micro Control Unit，微控制单元）， 对于最简单的使用两个MCU的情况来说，通常一个MCU处理实时性要求不高的工作，如数据存储，用户交互等，另一个处理实时性较高的工作，如高速绘图、解码等工作。这两个MCU之间必然需要某种高速通信机制，通常的做法是共享同一片内存，互斥访问，利用内存总线达到较高的数据传输率。Currently, in order to meet the high real-time performance requirements of the system in the monitor, two or more MCUs (Micro) will be used in one system. Control Unit, Micro Control Unit), For the simplest case of using two MCUs, usually one MCU handles tasks with low real-time requirements, such as data storage, user interaction, etc., and the other handles high-time work such as high-speed drawing and decoding. . A certain high-speed communication mechanism is inevitable between the two MCUs. The usual practice is to share the same piece of memory, mutually exclusive access, and use the memory bus to achieve a higher data transfer rate.
采用共享内存的方案，一般是使用内存总线直接连接两个或两个以上的MCU与同一个内存芯片，这样直接通过内存总线连接必然需要排布大量的地址和数据总线，物理连线复杂，布板要求较高，另外为了协调这些MCU和内存的工作其控制会较为复杂，需要消耗大量的系统开销进行控制，系统效率低。The solution of using shared memory is generally to directly connect two or more MCUs and the same memory chip by using a memory bus, so that a large number of addresses and data buses are necessary to be directly connected through the memory bus, and the physical connection is complicated. The board requirements are high. In addition, in order to coordinate the work of these MCUs and memory, the control is more complicated, and it takes a lot of system overhead to control, and the system efficiency is low.
【发明内容】 [Summary of the Invention]
基于此，有必要针对一般多MCU内存数据交换装置实现复杂且系统效率低问题，提供一种实现简单、系统效率高且能满足高速通信的监护仪及其多MCU内存数据交换装置。Based on this, it is necessary to implement a complex and low system efficiency problem for a general multi-MCU memory data exchange device, and provide a monitor that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication, and a multi-MCU memory data exchange device.
一种多MCU内存数据交换装置，包括至少两个MCU、SPI总线和至少两个内存，所述MCU间通过所述SPI总线相互连接，所述MCU分别独立连接所述内存；A multi-MCU memory data exchange device includes at least two MCUs, an SPI bus and at least two memories, wherein the MCUs are connected to each other through the SPI bus, and the MCUs are independently connected to the memory;
所述SPI总线为直接内存存取（Direct Memory Access，DMA）模式下的SPI总线，与所述MCU连接的内存通过DMA模式下的SPI总线相互交换数据。The SPI bus is a direct memory access (Direct Memory In the SPI bus in the Access, DMA) mode, the memory connected to the MCU exchanges data with each other through the SPI bus in the DMA mode.
在其中一个实施例中，所述内存的大小相等。在其中一个实施例中，所述内存为所述MCU内划分的独立内存区域。In one of the embodiments, the sizes of the memories are equal. In one of the embodiments, the memory is a separate memory area partitioned within the MCU.
在其中一个实施例中，所述内存为设置于所述MCU外且与所述MCU连接的内存芯片。In one embodiment, the memory is a memory chip disposed outside the MCU and connected to the MCU.
在其中一个实施例中，所述多MCU内存数据交换装置还包括与所述MCU连接的电源。In one of the embodiments, the multi-MCU memory data exchange device further includes a power source connected to the MCU.
在其中一个实施例中，所述SPI总线包括clk数据线、nss数据线、mosi数据线和miso数据线，所述MCU间通过所述clk数据线、所述nss数据线、所述mosi数据线和所述miso数据线连接。In one embodiment, the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
在其中一个实施例中，所述多MCU内存数据交换装置还包括至少两个SPI/LVDS转换器和LVDS总线，所述MCU通过所述SPI总线与所述SPI/LVDS转换器连接，每两个所述SPI/LVDS转换器间通过所述LVDS总线连接。In one embodiment, the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters and an LVDS bus, and the MCU is connected to the SPI/LVDS converter through the SPI bus, each of two The SPI/LVDS converters are connected by the LVDS bus.
一种监护仪，包括如上述的多MCU内存数据交换装置。A monitor comprising a multi-MCU memory data exchange device as described above.
上述多MCU内存数据交换装置， MCU分别独立连接有内存，采用高速SPI总线连接MCU，其SPI总线设置为DMA直接内存存取方式，即采用一种定时机制，以固定的时钟频率（如100毫秒）自动交换MCU间各自连接的内存中的数据，MCU 之间只需要按这个固定的时钟频率将需要交互的数据放入各自的内存中，达到高速通信的目的，另外MCU间通过SPI总线连接，整个装置布线简单。由于使用SPI 的DMA模式，无需MCU干预，大大降低了系统开销，提高系统效率，所以上述多MCU内存数据交换装置是一种实现简单、系统效率高且能满足高速通信的装置。The above multiple MCU memory data exchange device, The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus. The SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds). In-memory data, MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI The DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
【附图说明】[Description of the Drawings]
图1为所述多MCU内存数据交换装置第一个实施例的结构示意图；1 is a schematic structural diagram of a first embodiment of the multi-MCU memory data exchange device;
图2为所述多MCU内存数据交换装置第二个实施例的结构示意图。2 is a schematic structural diagram of a second embodiment of the multi-MCU memory data exchange device.
【具体实施方式】 【detailed description】
为了使本发明的目的、技术方案及优点更加清楚明白，以下根据附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施仅仅用以解释本发明，并不限定本发明。In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the present invention will be further described in detail below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
为了便于解释说明所述多MCU内存数据交换装置，在下述实施例以及附图中，均采用2个MCU的情况进行解释说明，应当理解，当MCU数量是两个以上时，其实施例以及附图仅仅是简单的数量累加。In order to facilitate the explanation of the multi-MCU memory data exchange device, in the following embodiments and the accompanying drawings, two MCUs are used for explanation. It should be understood that when the number of MCUs is two or more, the embodiment and the accompanying The graph is simply a simple sum total.
如图1所示，一种多MCU内存数据交换装置，包括至少两个MCU100、SPI总线200和至少两个内存300，所述MCU100间通过所述SPI总线200相互连接，所述MCU100分别独立连接所述内存300；As shown in FIG. 1 , a multi-MCU memory data exchange device includes at least two MCUs 100, an SPI bus 200, and at least two memories 300. The MCUs 100 are connected to each other through the SPI bus 200, and the MCUs 100 are independently connected. The memory 300;
所述SPI总线200为DMA模式下的SPI总线，与所述MCU100连接的内存300通过DMA模式下的SPI总线相互交换数据。The SPI bus 200 is an SPI bus in the DMA mode, and the memory 300 connected to the MCU 100 exchanges data with each other through the SPI bus in the DMA mode.
SPI总线是一种同步串行外设接口，它可以使MCU与各种外围设备以串行方式进行通信以交换信息，其硬件功能很强大，所以与SPI有关的软件就相当简单，MCU能够处理更多的其他事物。DMA直接内存存取技术是所有现代电脑的重要特色，它允许不同速度的硬件装置来沟通，而不需要依于MCU的大量中断负载。The SPI bus is a synchronous serial peripheral interface that allows the MCU to communicate with various peripheral devices in a serial manner to exchange information. Its hardware functions are very powerful, so the software related to SPI is quite simple, and the MCU can handle it. More other things. DMA direct memory access technology is an important feature of all modern computers, allowing hardware devices of different speeds to communicate without relying on the large interrupt load of the MCU.
上述多MCU内存数据交换装置， MCU分别独立连接有内存，采用高速SPI总线连接MCU，其SPI总线设置为DMA直接内存存取方式，即采用一种定时机制，以固定的时钟频率（如100毫秒）自动交换MCU间各自连接的内存中的数据，MCU 之间只需要按这个固定的时钟频率将需要交互的数据放入各自的内存中，达到高速通信的目的，另外MCU间通过SPI总线连接，整个装置布线简单。由于使用SPI 的DMA模式，无需MCU干预，大大降低了系统开销，提高系统效率，所以上述多MCU内存数据交换装置是一种实现简单、系统效率高且能满足高速通信的装置。The above multiple MCU memory data exchange device, The MCUs are independently connected to the memory, and the MCU is connected by a high-speed SPI bus. The SPI bus is set to the DMA direct memory access mode, that is, a timing mechanism is used to automatically exchange the respective connections between the MCUs at a fixed clock frequency (for example, 100 milliseconds). In-memory data, MCU Only need to press the fixed clock frequency to put the data that needs to be exchanged into the respective memory to achieve the purpose of high-speed communication, and the MCU is connected through the SPI bus, and the whole device is simply wired. Thanks to using SPI The DMA mode does not require MCU intervention, which greatly reduces system overhead and improves system efficiency. Therefore, the above multi-MCU memory data exchange device is a device that is simple in implementation, high in system efficiency, and capable of satisfying high-speed communication.
在其中一个实施例中，所述内存的大小相等。In one of the embodiments, the sizes of the memories are equal.
将内存大小设置为相同的便于实现内存数据交换，因为每个内存区域中的数据都是以一个相同的传输参数在进行交换，内存大小相等能够简化所述多MCU内存数据交换装置中的布线，提高其数据交换速率。在其中一个实施例中，所述内存为所述MCU内划分的独立内存区域。Setting the memory size to the same is convenient for memory data exchange, because the data in each memory area is exchanged with the same transmission parameter, and the equal memory size can simplify the wiring in the multi-MCU memory data exchange device. Increase its data exchange rate. In one of the embodiments, the memory is a separate memory area partitioned within the MCU.
在本实施例中，所述内存为MCU内划分的独立的内存区域，内存直接设置在MCU中简化了所述多MCU内存数据交换装置的结构，提高了MCU与内存之间数据交换的速率，有利于提升所述多MCU内存数据交换装置传输数据的速度。In this embodiment, the memory is an independent memory area divided in the MCU, and the memory is directly disposed in the MCU, which simplifies the structure of the multi-MCU memory data exchange device, and improves the data exchange rate between the MCU and the memory. It is beneficial to increase the speed of data transmission by the multi-MCU memory data exchange device.
在其中一个实施例中，所述内存为设置于所述MCU外且与所述MCU连接的内存芯片。In one embodiment, the memory is a memory chip disposed outside the MCU and connected to the MCU.
内存为外设于MCU外的内存芯片，其芯片大小能够根据实际使用的需要而进行改变，其内存的最大值不会受到MCU性能的限制，满足了多种不同情况下的实际使用需求。The memory is a memory chip that is external to the MCU. The chip size can be changed according to the needs of actual use. The maximum memory size is not limited by the performance of the MCU, and meets the actual use requirements in many different situations.
如图2所示，在其中一个实施例中，所述多MCU内存数据交换装置还包括与所述MCU100连接的电源400。As shown in FIG. 2, in one embodiment, the multi-MCU memory data exchange device further includes a power supply 400 connected to the MCU 100.
电源400用于为所述多MCU内存数据交换装置的器件供电。A power supply 400 is used to power the devices of the multi-MCU memory data exchange device.
在其中一个实施例中，所述SPI总线包括clk数据线、nss数据线、mosi数据线和miso数据线，所述MCU间通过所述clk数据线、所述nss数据线、所述mosi数据线和所述miso数据线连接。In one embodiment, the SPI bus includes a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data line, the nss data line, and the mosi data line pass between the MCUs. Connected to the miso data line.
clk数据线、nss数据线、mosi数据线和miso数据线为SPI使用的4根数据线，使用上述4根数据线即可实现SPI的基本功能，所以在本实施例中所述SPI总线包括clk数据线、nss数据线、mosi数据线和miso数据线可以在确保SPI基本功能的前提下，最大限度简化其结构，降低其实施成本。The clk data line, the nss data line, the mosi data line and the miso data line are the four data lines used by the SPI. The basic functions of the SPI can be realized by using the above four data lines, so in the embodiment, the SPI bus includes clk. The data line, nss data line, mosi data line, and miso data line can minimize the structure and reduce the implementation cost while ensuring the basic functions of the SPI.
如2所示，在其中一个实施例中，所述多MCU内存数据交换装置还包括至少两个SPI/LVDS转换器500和LVDS总线600，所述MCU100通过所述SPI总线200与所述SPI/LVDS转换器500连接，每两个所述SPI/LVDS转换器500间通过所述LVDS总线600连接。As shown in FIG. 2, in one embodiment, the multi-MCU memory data exchange device further includes at least two SPI/LVDS converters 500 and an LVDS bus 600 through which the MCU 100 communicates with the SPI/ The LVDS converter 500 is connected, and each of the two SPI/LVDS converters 500 is connected through the LVDS bus 600.
由于SPI总线高效通信距离只有50cm，当两个MCU之间相距较远时，就需要多个SPI总线连接。在本实施例中，设置有至少两个SPI/LVDS转换器和LVDS总线，两个MCU间需要远距离SPI连接时，两个MCU先分别通过SPI总线与所述SPI/LVDS转换器连接，SPI/LVDS转换器之间又通过LVDS总线连接。应当理解SPI/LVDS转换器和LVDS总线可以为多个以便MCU间可以更远距离通过SPI总线连接。另外还需理解，在本实施例中SPI/LVDS转换器可以为其他信号的与SPI的转换器，其转换器之间通过该信号的总线连接。Since the efficient communication distance of the SPI bus is only 50cm, when the two MCUs are far apart, multiple SPI bus connections are required. In this embodiment, at least two SPI/LVDS converters and an LVDS bus are provided. When a long-distance SPI connection is required between two MCUs, two MCUs are first connected to the SPI/LVDS converter through the SPI bus, respectively. The /LVDS converters are connected via an LVDS bus. It should be understood that the SPI/LVDS converter and the LVDS bus can be multiple so that the MCUs can be connected over the SPI bus at greater distances. In addition, it should be understood that in this embodiment, the SPI/LVDS converter can be a converter of other signals and SPI, and the converter is connected by a bus of the signal.
一种监护仪，包括如上述的多MCU内存数据交换装置。A monitor comprising a multi-MCU memory data exchange device as described above.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (8)

  1. 一种多MCU内存数据交换装置，其特征在于，包括至少两个MCU、SPI总线和至少两个内存，所述MCU间通过所述SPI总线相互连接，所述MCU分别独立连接所述内存；A multi-MCU memory data exchange device, comprising: at least two MCUs, an SPI bus, and at least two memories, wherein the MCUs are connected to each other through the SPI bus, and the MCUs are independently connected to the memory;
    所述SPI总线为DMA模式下的SPI总线，与所述MCU连接的内存通过DMA模式下的SPI总线相互交换数据。The SPI bus is an SPI bus in DMA mode, and the memory connected to the MCU exchanges data with each other through the SPI bus in the DMA mode.
  2. 根据权利要求1所述的多MCU内存数据交换装置，其特征在于，所述内存的大小相等。The multi-MCU memory data exchange device according to claim 1, wherein the sizes of the memories are equal.
  3. 根据权利要求1或2所述的多MCU内存数据交换装置，其特征在于，所述内存为所述MCU内划分的独立内存区域。The multi-MCU in-memory data exchange device according to claim 1 or 2, wherein the memory is an independent memory area divided in the MCU.
  4. 根据权利要求1或2所述的多MCU内存数据交换装置，其特征在于，所述内存为设置于所述MCU外且与所述MCU连接的内存芯片。The multi-MCU memory data exchange device according to claim 1 or 2, wherein the memory is a memory chip disposed outside the MCU and connected to the MCU.
  5. 根据权利要求1或2所述的多MCU内存数据交换装置，其特征在于，还包括与所述MCU连接的电源。The multi-MCU memory data exchange device according to claim 1 or 2, further comprising a power source connected to the MCU.
  6. 根据权利要求1或2所述的多MCU内存数据交换装置，其特征在于，所述SPI总线包括clk数据线、nss数据线、mosi数据线和miso数据线，所述MCU间通过所述clk数据线、所述nss数据线、所述mosi数据线和所述miso数据线连接。The multi-MCU memory data exchange device according to claim 1 or 2, wherein the SPI bus comprises a clk data line, an nss data line, a mosi data line, and a miso data line, and the clk data is passed between the MCUs. A line, the nss data line, the mosi data line, and the miso data line are connected.
  7. 根据权利要求1或2所述的多MCU内存数据交换装置，其特征在于，还包括至少两个SPI/LVDS转换器和LVDS总线，所述MCU通过所述SPI总线与所述SPI/LVDS转换器连接，每两个所述SPI/LVDS转换器间通过所述LVDS总线连接。The multi-MCU memory data exchange device according to claim 1 or 2, further comprising at least two SPI/LVDS converters and an LVDS bus, said MCU passing said SPI bus and said SPI/LVDS converter Connected, each of the two SPI/LVDS converters is connected by the LVDS bus.
  8. 一种监护仪，其特征在于，包括如权利要求1-7中任意一项所述的多MCU内存数据交换装置。A monitor comprising the multi-MCU memory data exchange device according to any one of claims 1-7.
PCT/CN2014/079150 2013-06-28 2014-06-04 Patent monitor and multi-mcu memory data exchange device for same WO2014206181A1 (en)

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