CN101930422A - Multi-core CPU interconnection structure based on multilayer AHB bus - Google Patents
Multi-core CPU interconnection structure based on multilayer AHB bus Download PDFInfo
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Abstract
The invention discloses a multi-core CPU interconnection structure based on a multilayer AHB bus, which belongs to the technical field of electronics. In the structure, the multilayer AHB bus is applied to data transmission among multiple CPU cores in the multi-core CPU. Compared with the prior art, the multi-core CPU interconnection structure of the invention has the characteristics of high efficiency, high speed, low power consumption and the like.
Description
Technical field
The present invention relates to electronic technology field, specifically a kind of multi-core CPU interconnection structure based on multilayer AHB bus.
Background technology
Along with the development of semiconductor process techniques and IC designing technique, more and more Fu Za function is integrated on the chip, so SOC (system on a chip) SOC (System on a chip) occurred.Improvement and development as the structure of the microprocessor (CPU) of ingredient important among the SOC then are important links that improves whole SOC performance.
In order to improve the computing power of microprocessor, we will consider two kinds of methods, and the one, the frequency of raising single-chip, the 2nd, adopt multi-core parallel concurrent to calculate.Present problem is along with the raising power consumption and the thermal value of frequency are increasing, but adopting multi-core parallel concurrent to calculate power consumption can't be multiplied, many core CPU structure also has steering logic simple simultaneously, advantages such as communication delay is low are so the emphasis of microprocessor research is at present transferred on the multi-core parallel concurrent computation structure gradually.
Sometimes need to carry out data sharing and synchronous between each core cpu executive routine of multi-core processor, so hardware configuration must be supported internuclear communication, communication mechanism is the high performance important assurances of many core CPU efficiently, efficient communication mechanism has two kinds on the sheet of main flow at present, a kind of cache structure that bus is shared, a kind of interconnect architecture that is based on the sheet of being based on.Here adopt based on the interconnect architecture on the sheet, and each core cpu of this structure has independently processing unit and cache, and each core cpu is got in touch together by modes such as cross bar switch or network-on-chips.
Ahb bus has following characteristics as the SOC (system on a chip) bus of SOC: the operation of single clock edge, the implementation of non-three-state, support burst transfer, support segment transmissions, support a plurality of primary controllers, support 32-128 highway widths, support the transmission of byte, half-word and word.AHB is mainly used in the transmission between the high-performance module, as CPU, and DSP, DMA etc.
Summary of the invention
Technical assignment of the present invention is at above-mentioned the deficiencies in the prior art, and a kind of multi-core CPU interconnection structure based on multilayer AHB bus of efficient, fast, low power consumption is provided.
Technical assignment of the present invention is realized in the following manner: based on the multi-core CPU interconnection structure of multilayer AHB bus, be characterized in multilayer AHB bus is applied to the data transmission between each CPU nuclear in the multi-core CPU.
Each CPU nuclear inside all comprises corresponding master device module and slave unit module in the multi-core CPU, each CPU nuclear in as the main equipment of ahb bus also as the slave unit of other main equipments.That is to say that each CPU nuclear has two parts with the interface of internal system ahb bus, a part is the main equipment module, and the interface when being used for realizing CPU as main equipment master sends to control signal and data on the ahb bus; Another part is the slave unit module, and the interface when being used for realizing CPU as slave unit slave is used for receiving control signal that other CPU send over and data etc. from ahb bus.
In order further to promote the overall operation efficiency of many kernels CPU architecture, multiport register can be adopted in each CPU nuclear inside, makes the CPU of inside examine and endorse simultaneously register is conducted interviews by the connected CPU of ahb bus.
The present invention is used for data transmission between the multi-core CPU with multilayer AHB bus, compared with prior art has can reduce power consumption, reduce communication delay, thereby promotes the overall operation efficiency of many kernels CPU architecture.
Description of drawings
Accompanying drawing 1 is the multilayer AHB bus structural representation;
Accompanying drawing 2 is based on the multi-core CPU interconnection structure synoptic diagram of multilayer AHB bus.
Embodiment
Explain below multi-core CPU interconnection structure based on multilayer AHB bus of the present invention being done with specific embodiment with reference to Figure of description.
Embodiment:
The related multilayer AHB bus structure of multi-core CPU interconnection structure of the present invention as shown in Figure 1.It comprises a plurality of main equipment control modules, a plurality of slave unit control modules, and main equipment is to the MUX of slave unit, and slave unit is to the MUX of main equipment and bus arbiter etc.Wherein AHB main equipment control module is used to receive the order that main equipment sends over, and sends application to the ahb bus moderator, and carries out exchanges data with corresponding AHB slave unit controller module after obtaining the bus arbiter mandate; AHB slave unit control module obtains information from bus arbiter, for write operation, open the AHB slave unit, and corresponding data are write in the AHB slave unit, for read operation, opens the AHB slave unit, reads in the slave unit corresponding data and delivers on the ahb bus; The ahb bus moderator, write down the application that each AHB main equipment control module is sent, arbitrate according to configuration requirement, give AHB main equipment controller module and corresponding AHB slave unit control module arbitration result, give the high AHB main equipment of priority with bus grant, open corresponding AHB slave unit simultaneously, AHB main equipment and AHB slave unit carry out exchanges data by ahb bus then.Each layer while can only have a main equipment control module authorized in the multilayer AHB bus structure, occupies bus.
Multi-core CPU interconnection structure based on multilayer AHB bus of the present invention as shown in Figure 2.Promptly comprise AHB main equipment control module in each CPU nuclear of multi-core CPU, also comprised the slave unit control module.Such as the core A in the multi-core CPU, he is the main equipment of A layer ahb bus, still be the slave unit of B layer ahb bus and C layer ahb bus simultaneously, and wherein core B and core C are the slave units of A layer ahb bus, so when core A works, it not only can handle the data of oneself, can also visit data among core B and the core C by A layer ahb bus, thereby realizes the data communication between the multinuclear heart; In this process, meanwhile, core B and core C also can come the data in other two other cores are conducted interviews by B layer ahb bus and C layer ahb bus respectively, thereby realize the concurrent operation between each core of multi-core CPU.Having is exactly the inner multiport register that adopts of each CPU nuclear of multi-core CPU again, and its inner CPU examines and endorses simultaneously register is conducted interviews by the connected CPU of ahb bus like this, promotes the overall operation efficiency of many kernels CPU architecture.
The process of carrying out data communication in this multi-core CPU interconnection structure between each CPU nuclear all is the control signal that is produced by the ahb bus moderator, comprise the control signal of giving AHB main equipment control module and AHB slave unit control module, so the ahb bus moderator is a very important module in this multi-core CPU interconnection structure.
Claims (3)
1. the multi-core CPU interconnection structure based on multilayer AHB bus is characterized in that: multilayer AHB bus is applied to the data transmission between each CPU nuclear in the multi-core CPU.
2. the multi-core CPU interconnection structure based on multilayer AHB bus according to claim 1, it is characterized in that, each CPU nuclear inside all comprises corresponding master device module and slave unit module in the multi-core CPU, each CPU nuclear in as the main equipment of ahb bus also as the slave unit of other main equipments.
3. the multi-core CPU interconnection structure based on multilayer AHB bus according to claim 1, it is characterized in that, the inner multiport register that adopts of each CPU nuclear, inner CPU examines and endorses simultaneously register is conducted interviews by the connected CPU of ahb bus.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102301364A (en) * | 2011-06-27 | 2011-12-28 | 华为技术有限公司 | Cpu interconnecting device |
| CN102710890A (en) * | 2012-04-06 | 2012-10-03 | 东莞中山大学研究院 | Video processing on-chip system of double AHB (Advanced High Performance Bus) buses |
| CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
| US8909979B2 (en) | 2011-06-27 | 2014-12-09 | Huawei Technologies Co., Ltd. | Method and system for implementing interconnection fault tolerance between CPU |
| CN110134640A (en) * | 2018-02-09 | 2019-08-16 | 上海中研久弋科技有限公司 | Multi-core sensing data handles chip and operation method |
| CN110347635A (en) * | 2019-06-28 | 2019-10-18 | 西安理工大学 | A kind of heterogeneous polynuclear microprocessor based on multilayer bus |
| WO2020087249A1 (en) * | 2018-10-30 | 2020-05-07 | 北京比特大陆科技有限公司 | Multi-core chip structure |
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| CN101071405A (en) * | 2006-05-08 | 2007-11-14 | 中兴通讯股份有限公司 | Asynchrous AHB interconnection matrix interface device |
| CN101145140A (en) * | 2007-07-11 | 2008-03-19 | 南京大学 | Dynamic self-adaptive bus arbiter based on microprocessor-on-chip |
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- 2010-08-26 CN CN2010102632296A patent/CN101930422A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101071405A (en) * | 2006-05-08 | 2007-11-14 | 中兴通讯股份有限公司 | Asynchrous AHB interconnection matrix interface device |
| CN101145140A (en) * | 2007-07-11 | 2008-03-19 | 南京大学 | Dynamic self-adaptive bus arbiter based on microprocessor-on-chip |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8990460B2 (en) | 2011-06-27 | 2015-03-24 | Huawei Technologies Co., Ltd. | CPU interconnect device |
| WO2012103712A1 (en) * | 2011-06-27 | 2012-08-09 | 华为技术有限公司 | Cpu interconnect device |
| CN102301364A (en) * | 2011-06-27 | 2011-12-28 | 华为技术有限公司 | Cpu interconnecting device |
| US8909979B2 (en) | 2011-06-27 | 2014-12-09 | Huawei Technologies Co., Ltd. | Method and system for implementing interconnection fault tolerance between CPU |
| CN102710890A (en) * | 2012-04-06 | 2012-10-03 | 东莞中山大学研究院 | Video processing on-chip system of double AHB (Advanced High Performance Bus) buses |
| CN102710890B (en) * | 2012-04-06 | 2014-11-05 | 东莞中山大学研究院 | Video processing on-chip system of double AHB (Advanced High Performance Bus) buses |
| CN103218337A (en) * | 2013-03-13 | 2013-07-24 | 北京安拓思科技有限责任公司 | SoC (System on Chip) and method for realizing communication between master modules and between slave modules based on wishbone bus |
| CN103218337B (en) * | 2013-03-13 | 2015-10-07 | 北京安拓思科技有限责任公司 | Based on wishbone bus realize main and master and slave with from the SOC (system on a chip) communicated and method |
| CN110134640A (en) * | 2018-02-09 | 2019-08-16 | 上海中研久弋科技有限公司 | Multi-core sensing data handles chip and operation method |
| CN110134640B (en) * | 2018-02-09 | 2024-03-01 | 上海中研久弋科技有限公司 | Multi-core sensor data processing chip and operation method |
| WO2020087249A1 (en) * | 2018-10-30 | 2020-05-07 | 北京比特大陆科技有限公司 | Multi-core chip structure |
| CN110347635A (en) * | 2019-06-28 | 2019-10-18 | 西安理工大学 | A kind of heterogeneous polynuclear microprocessor based on multilayer bus |
| CN110347635B (en) * | 2019-06-28 | 2021-08-06 | 西安理工大学 | Heterogeneous multi-core microprocessor based on multilayer bus |
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Application publication date: 20101229 |