CN110134640A - Multi-core sensing data handles chip and operation method - Google Patents
Multi-core sensing data handles chip and operation method Download PDFInfo
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Abstract
The present invention provides a kind of multi-core sensing data processing chip and operation method, the data processing chip includes multi-core array area, input module, output module, control module etc., and wherein multi-core array area includes multiple bus marco cores, multiple data processing cores, multiple data/address bus；All bus marco cores are connected with data processing core by data/address bus；Bus marco core passes through configuration of the control module dynamic adjusting data processing core between different data bus according to the data information of input.Multi-core sensing data processing chip of the invention can carry out dynamic layered processing to input pickup data, improve the flexibility and trackability of cognitive function, the value of industrial utilization with height.
Description
Technical field
The invention belongs to semiconductor storage integrated circuit fields, it is related to a kind of multi-core sensing data processing chip and fortune
Row method.
Background technique
With the development of science and technology, i.e., it will enter the internet of things era, after a large amount of sensor accesses network, to sensor
Data processing proposes very high requirement, wherein several critical issues are:
1, how a large amount of data are timely handled；
2, the processing mode and type of sensing data are closely related, different types of data need different algorithms into
Row processing；
3, highly effective information is kept in sensing data, it, can be to a certain degree although promoting data-handling capacity
It is upper to solve the problems, such as that data volume is big and type is abundant, but realize that data cognition is still very difficult.
In this case, the needs of meeting us only has been difficult to by developing miscellaneous data processor.
The brain of people handles a large amount of information by vision, the sense of hearing, tactile etc. number of ways daily, reasoning, identification,
The ability of association, prediction etc. etc. is that computer system is difficult to be equal to, but it is estimated that the brain power consumption of an adult only
Only there was only 20W or so, and the transmission speed of information in the brain is also only capable of reaching a millisecond magnitude.How from the work of human brain
It is inspired in mode, improves the method for operation of computer architecture, to achieve the purpose that high efficiency low power consumption is run, while can
Processing data are gone according to the mode of thinking of the mankind, the service of providing is then numerous researchers and company's urgent problem to be solved.
Brain science result of study shows that neuron is in human brain to be layered network construction form interconnection, and cognitive process just exists
Under this layering networking mode, completed by the cooperation between neuron.On the one hand the mode of this collaborative work passes through parallel
So that response speed can also complete a large amount of perception task well below the neuron of electronic device, many aspects even compare for work
High-performance computer is done better；On the other hand, by study and layered filtration, a large amount of invalid information are filtered, and are had
The information of effect can remain into finally, to be unlikely to cause because of excessive data human thinking process to overload, while will not make
Effective information is flooded by a large amount of invalid information.
Neural computing has formd a highly developed perfect theoretical system, imitate cerebral nerve network and
Row treatment mechanism forms multi-input multi-output system, by the training of mass data so that the system have it is more and more accurately pre-
Survey ability.This system is initially to realize in computer software, and in order to improve computational efficiency, more hardware systems are at
Manage the hardware that the technologies such as device, FPGA (Field Programmable Gate Array, field programmable gate array) realize algorithm
Accelerate.Further, IBM Corporation is newly developed in the Watson computer system project for starting artificial intelligence many years ago
Second generation TrueNorth chip realize the processing chips of 1,000,000 neurons of simulation, power consumption only 70mW has led intelligence
The research and development of chip field are handled, and " cognition calculates " that IBM Corporation proposes also becomes the research and development focus of academia and business circles.
However these schemes do not embody brain although having accomplished that the node of homogeneity solves complicated cognitive function
The process of neuron autonomic function differentiation, algorithm it is abstract under, functional meaning is not present in node, only exists mathematical logic meaning
Justice, the result of formation are exactly that whole system can only be worked in a manner of black box, when result is unsatisfactory, can not be traced whole
A cognitive process problem.It is also only certain although having there are some means to go artificially to divide region and function at present
Improvement in degree is not accomplished to solve at all, this affects systematic difference effect.
The present invention exactly in this context, by the chip topology structure of the multilayer of flexible design, exists for processing chip
It imitates in neural fusion cognitive process, realizes that nodal function differentiation provides hardware supported.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide at a kind of multi-core sensing data
Reason chip handles the flexibility of realization cognition by sensing data and can be traced for promoting computer architecture in the prior art
Property problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of multi-core sensing data processing chip,
The chip include multi-core array area, input module, output module, control module and chip input pin, chip output draw
Foot and chip controls pin, in which:
The multi-core array area includes M bus marco core, N number of data processing core and M data bus, wherein
M is the integer greater than 2, and N is the integer greater than 1；All bus marco cores are connected with data processing core by data/address bus,
One bus marco core is connected by every data bus with N number of data processing core；Each data processing core, passes through difference
Data/address bus realize that the data processing core and different bus marco cores are connected；It is each for each data processing core
An output end and an output end is arranged in bus, connects for corresponding data processing core；
The input module has an input interface and an output interface, and the input interface of the input module connects
The chip input pin, the output interface of the input module connect at least one in the data/address bus, referred to as input
Layer bus；
The output module has an input interface and an output interface, and the output interface of the output module connects
The chip output pin, the input interface of the output module connect at least one in the data/address bus, referred to as export
Layer bus；
The control module connects the data processing core, bus marco core, input module and output module, according to
The output information of the data/address bus generate corresponding control signal export to the data processing core, bus marco core,
Input module or output module.
Optionally, each data processing core has an output interface and an input interface, passes through one respectively
A outlet selector and an input selector are connected with the output end of the different data bus and input terminal；The number
It selects to connect with a wherein data/address bus by the outlet selector according to processing core, carries out information forwarding output or described
Data processing core is connect by input selector selection with a wherein data/address bus, and bus message is received.
Optionally, the data processing core include bus control logic and corresponding data buffering, non-volatile memory and
Model Matching logic.
Optionally, the bus marco core include ARM controller, volatile dynamic data storage, non-volatile code storage,
Data buffering and bus control logic.
Optionally, the working method of the bus marco core in the multi-core array area includes:
Whether the active data processing core of all output ends has information defeated on the poll data/address bus in order
Out, if there is information output, start reading information timing and read information；
The active data processing core of all input terminals on the data/address bus is traversed in order, and prediction timing is read in starting
Read the active data processing core of each input terminal data process core active to the output end on the data/address bus
The predictive information of heart output information after integrated forecasting information, is evaluated predictive information, and starts and write evaluation timing and will evaluate
As a result it is sent to the active data processing core of each input terminal of data/address bus.
Optionally, the output interface of the data processing core and the working method of input interface include:
It is total from the data when information timing is read in the data/address bus starting that the input interface of the data processing core connects
Information is read on line, after sender's label in detection information screens, obtains the one or more that the node is currently paid close attention to
Information is compared and is matched with existing variation model by learning algorithm by the output information of sender, will be immediate
Model and relevant parameter form cognitive information, and are temporarily stored in the output interface of the data processing core, while according to the model
The variation in input information future is predicted, prediction result is temporarily stored in the input interface of the data processing core；
When the data/address bus that the input interface of the data processing core connects traverses notebook data processing core, and start
When reading prediction timing, the prediction result is sent out into the upper data/address bus, is read for the bus marco core；
When the data/address bus that the output interface of the data processing core connects traverses notebook data processing core, and start
When writing evaluation timing, evaluation information is read from data/address bus, the target sender label in detection information screens, and obtains
Currently to the evaluation result of sender's output information prediction, cognitive algorithm is adjusted using the result.
Optionally, the input module obtains data from the chip input pin, and is converted to unified information format
It is temporarily stored in the output interface of the input module, sends information to the data when input layer bus is polled to the module
Bus.
Optionally, the output module is when the output layer bus enters reading information timing, from the data/address bus
Information is read, and is forwarded to the chip output pin.
Optionally, the function of the control module includes:
With the bus marco core communication, each active output end output information on the data/address bus is obtained
Comprehensive assessment as a result, be dynamically determined the data processing core distributed on each data/address bus according to the comprehensive assessment result,
And the data processing core output end and input terminal for notifying the bus marco core active；
It is communicated with the input selector, the input that the active input terminal accesses the data processing core is connect
Mouthful, other inactive input terminals are isolated with connected data/address bus；
It is communicated with the outlet selector, the output that the active output end accesses the data processing core is connect
Mouthful, other inactive output ends are isolated with connected data/address bus.
The present invention also provides a kind of operation method of multi-core sensing data processing chip, the multi-core sensor numbers
Chip is handled using the multi-core sensing data as described in above-mentioned any one according to processing chip, the operation method includes:
Data information inputs the multi-core data processing chip by the input module；
The control module generates corresponding control signal according to the data/address bus output information to configure each number
According to the connection relationship of processing core and each data/address bus；
The data processing core is adapted to number using different Matching Models according to the data information in conjoint data bus
According to variation model and export predictive information；
The predictive information of data processing core output on the bus marco core readout data bus, carries out comprehensive
Evaluation is closed, comprehensive evaluation result is obtained；
The bus marco core notifies the control module to adjust the data processing according to the comprehensive evaluation result
Configuration of the core between different data bus；It controls the data processing core and carries out further Matching Model, until obtaining
Obtain optimal matching result；Send the matching result to the output module of the chip.
Detailed description of the invention
Fig. 1 is shown as the schematic diagram of multi-core sensing data processing chip interior core array interconnection of the invention.
Fig. 2 is shown as the design example schematic of data processing core core of the invention.
Fig. 3 is shown as the design example schematic of bus marco core of the invention.
Fig. 4 is shown as a simplified example structural schematic diagram of the invention.
Fig. 5 is shown as core of the invention connection logical schematic.
Fig. 6 is shown as a more flexible exemplary construction schematic diagram of the invention.
Fig. 7 is shown as the core connection logical schematic of cognitive function first step configuration of the invention.
Fig. 8 is shown as the core connection logical schematic of cognitive function second step configuration of the invention.
Fig. 9 is shown as the core connection logical schematic of cognitive function third step configuration of the invention.
Figure 10 is shown as the core connection logical schematic of the 4th step of cognitive function configuration of the invention.
Component label instructions
1 multi-core sensing data handles chip
2 data processing cores
3 bus marco cores
4 output modules
5 input modules
6 chip output pins
7 chip input pins
8 data/address bus
9 data processing core output interfaces
10 data processing core input interfaces
11 are articulated to the output line of each data/address bus
12 are articulated to the input line of each data/address bus
13 outlet selectors
14 input selectors
15 control modules
16 control modules connect the control line of other modules
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Fig. 5.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
The present invention provides a kind of multi-core sensing data processing chip, referring to Fig. 1, being shown as the multi-core sensing
The interconnection schematic diagram of device data processing chip 1, including M bus marco core 3, N number of data processing core 2, each total line traffic control
Core processed connects a data/address bus 8, and each data processing core has an output interface 9, selected by outlet selector 13
It is logical, and line 11 is mounted by bus and connects each data/address bus；Likewise, also there is each data processing core an input to connect
Mouth 10 mounts line 12 by 14 gate bus of input selector and connects each data/address bus.
Output module 4 has an input interface and an output interface, wherein input interface fixation is articulated to a number
According to bus, which is referred to as output layer bus；Output interface is drawn by the output interface 6 of chip, defeated with other chips
Incoming interface is connected.
Input module 5 has an input interface and an output interface, wherein output interface fixation is articulated to one not
It is same as another data/address bus of input layer bus；Input interface is drawn by the input interface 7 of chip, defeated with other chips
Outgoing interface is connected.
Control module 15 connects all bus marco cores 3 in chip, data processing core 2, defeated by control line 16
Module 4 and input module 5 out.
Relative positional relationship between each core and each line for ease of description, certainly by the bus marco core
B is successively named as under above1、B2、……、BM, the data processing core is successively named as P from left to right1、P2、……、
PN, wherein 1~M, 1~N are number.
It is defeated by actively being inputted to bus marco core configuration after control module 15 determines the connection topology of data processor
Outgoing interface, input selector and outlet selector realize that data processor connects between different data bus, total from a data
Data are obtained on line, and send cognition result on another data/address bus, realize hierarchical structure.
Specifically, each data processing core needs to carry out Model Matching, therefore, a simple data processing to data
Nuclear structure is as shown in Figure 2.The data processing core is equipped with two sets of bus control logics and corresponding data buffering, for completing
Volatile memory embedded SRAM can be used in bus operation, data buffering；It is equipped with non-volatile memory and is used for storage change model, it can
To use nonvolatile storage built-in EEPROM or embedded FLASH；All matching process, can be with due to logic and uncomplicated
A Model Matching logic module is realized with synchronous digital logic.
Specifically, each bus marco core needs to assess data, and provides control information for control module, tool
There is certain complex logic function, but logarithm is solely of less demanding, therefore simple bus marco nuclear structure such as Fig. 3 institute
Show, it can be non-volatile with ARM controller, the volatile dynamic data storage of embedded SRAM, built-in EEPROM or embedded FLASH
Code storage composition minimum of computation system, and the access by data buffering and bus control logic realization to data/address bus.
Other structures are common features module, can be readily available a variety of solutions using existing knowledge.
As an example, the multi-core array area includes M bus marco core 3, M data/address bus 8, every number are connected
N number of output mounting line 11 is mounted according to bus and N respectively inputs mounting line 12, passes through outlet selector 13 and input selector 14 respectively
Access N number of data processing core 2.
In addition, the connected bus of bus marco core B1 is output layer bus, it is fixedly attached to output module 4, bus marco
Core BMConnected bus is input layer bus, is fixedly attached to input module 5.Other data/address bus can be described as hidden layer bus.
To indicate this process, a simplified practical example is provided, structure is as shown in Figure 4.In the figure, bus marco core
3 quantity of the heart is selected as minimum value 3, number B1、B2、B3, 2 quantity of data processing core is selected as 3, number P1、P2、P3.It is logical
Control module 15 is crossed with postponing, the selection of input selector and outlet selector is shown with arrow in figure, while in order to intuitive, will
Non-selected mounting line does not indicate in figure.Selected mounting line is being the mounting of active interface on the data bus
Line.
Under this connection configuration, logic connecting relation is as shown in Figure 5.It will be seen that under this configuration, at data
Reason device node constitutes two layers of structure, wherein P1 connects input layer bus and hidden layer bus with P2, and P3 connection hidden layer is total
Line and output layer bus.
Under this connection relationship, a kind of application method is: P1 and P2 obtains data from input layer bus respectively, according to
Two different modes handle data, for example, P1 realizes data to the frequency changing rule after frequency-domain transform, P2 is realized
The mean variation rule of data, each data processing core is according to both different mode adaptation data variation models and provides
Prediction, P1 according to the situation of change of average value predict next data come when possible values, and the mean variation that will match to
Model and relevant parameter are sent on data/address bus B2 as output；Likewise, P2 becomes according to frequency domain variation model matched data
Change model, makes prediction, and model and parameter are also sent on data/address bus B2.P3 obtains these matching knots from B2 bus
Fruit finds the changing rule of these models and parameter as input again, further Matching Model, and by matching result from output
Port output.By this process, data have just obtained chromatographic analysis and Model Matching, and data are every to be matched by primary, due to
Output is changing rule model, so data volume is greatly reduced, is also just able to carry out more complicated, higher level rule
Rule matching.The number of plies is more, and matched model can be increasingly complex, and obtained cognition result is just closer true, and data volume
Then significantly reduced.
However this connection relationship easily can reconfigure modification by control module, dynamic modification connection is closed
System more can flexibly configure resource.
A kind of relative complex implementation method can be to show in chip shown in Fig. 6.Wherein, bus marco core amounts and
It is 4 that data processing core quantity, which all increases, and make is similar with foregoing teachings, thus, input layer bus is B4, and output layer is total
Line is B1, and hidden layer bus is B2, B3 two.
When original date inputs chip, since chip is not aware that the changing rule of sensing data, control module configuration
Whole data processing cores is configured between input layer bus B 4 and hidden layer B3 by connection relationship, and is divided into automatically each
Different function carries out Model Matching to data simultaneously, and annexation figure is as shown in Figure 7 at this time.
Through Matching and modification after a period of time, bus marco core B3 discovery P2 and P4 has been able to be compared data
Good Model Matching, but recognize result and still can change, then notify control module by P1 and P3 from the two data/address bus it
Between remove, be configured between output layer bus B 1 and hidden layer B3, such as Fig. 8.P1 and P3 function differentiation is right in different ways
The matched cognition results change rule of P2 and P4 carries out Model Matching.
Through Matching and modification after a period of time, bus marco core B1 discovery P1 can complete the model of this layer
Match, notice control module removes P3, idle as standby resources.As shown in Figure 9.
Afterwards because actual conditions change, the changing rule of data changes, and increases new factor, at this time B1 bus marco
Core finds that final cognition result is inaccurate, and notifies control module that P3 is configured to hidden layer bus B 2 and output layer bus
Between B1, and the output of P1 is connected in hidden layer bus B 2, this variation increases one layer of processing, can support more multiple
Miscellaneous data variation model through Matching and modification after a period of time, obtains optimal cognition result as shown in Figure 10.
In this embodiment, the connection structure of the chip multi-core array, which can be realized, dynamically adjusts, autonomous real
The function differentiation of existing data processing core；When Model Matching result changes, entire Model Matching process can be traced, adjust
Matching Model and parameter, to further improve the flexibility that chip completes cognitive function to the data of variation.Of the invention
Multi-core sensing data, which handles chip, can carry out dynamic layered processing to input pickup data, improve the spirit of cognitive function
Activity and trackability.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of multi-core sensing data handles chip, which is characterized in that the chip includes multi-core array area, input mould
Block, output module, control module and chip input pin, chip output pin and chip controls pin, in which:
The multi-core array area includes M bus marco core, N number of data processing core and M data bus, and wherein M is
Integer greater than 2, N are the integer greater than 1；All bus marco cores are connected with data processing core by data/address bus, often
One bus marco core is connected by data bus with N number of data processing core；Each data processing core, by different
Data/address bus realizes that the data processing core is connected from different bus marco cores；It is each total for each data processing core
An output end and an output end is arranged in line, connects for corresponding data processing core；
The input module have an input interface and an output interface, the input module input interface connection described in
Chip input pin, the output interface of the input module connect at least one in the data/address bus, and referred to as input layer is total
Line；
The output module have an input interface and an output interface, the output module output interface connection described in
Chip output pin, the input interface of the output module connect at least one in the data/address bus, and referred to as output layer is total
Line；
The control module connects the data processing core, bus marco core, input module and output module, according to described
The output information of data/address bus generates corresponding control signal and exports to the data processing core, bus marco core, input
Module or output module.
2. multi-core sensing data according to claim 1 handles chip, it is characterised in that: each data processing
Core has an output interface and an input interface, passes through an outlet selector and an input selector and institute respectively
The output end for stating different data bus is connected with input terminal；The data processing core is selected by the outlet selector
It is connect with a wherein data/address bus, carries out information forwarding output or the data processing core is selected by the input selector
It selects and is connect with a wherein data/address bus, receive bus message.
3. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the data processing core
Including bus control logic and corresponding data buffering, non-volatile memory and Model Matching logic.
4. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the bus marco core
Including ARM controller, volatile dynamic data storage, non-volatile code storage, data buffering and bus control logic.
5. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the multi-core array area
In the working method of the bus marco core include:
Whether the active data processing core of all output ends has information output on the poll data/address bus in order, if
There is information output, then starts reading information timing and read information；
The active data processing core of all input terminals on the data/address bus is traversed in order, and starting is read prediction timing and read
The active data processing core of each input terminal is defeated to the data processing core that the output end on the data/address bus is active
The predictive information of information out after integrated forecasting information, is evaluated predictive information, and starts and write evaluation timing for evaluation result
It is sent to the active data processing core of each input terminal of data/address bus.
6. multi-core sensing data according to claim 2 handles chip, it is characterised in that: the data processing core
Output interface and the working method of input interface include:
When information timing is read in the data/address bus starting that the input interface of the data processing core connects, from the data/address bus
Information is read, after sender's label in detection information screens, obtains one or more transmissions that the node is currently paid close attention to
Information is compared and is matched with existing variation model by learning algorithm, by immediate model by the output information of person
And relevant parameter forms cognitive information, and is temporarily stored in the output interface of the data processing core, while according to the model to defeated
The variation for entering information future is predicted, prediction result is temporarily stored in the input interface of the data processing core；
When the data/address bus that the input interface of the data processing core connects traverses notebook data processing core, and it is pre- to start reading
When surveying timing, the prediction result is sent out into the upper data/address bus, is read for the bus marco core；
When the data/address bus that the output interface of the data processing core connects traverses notebook data processing core, and starts to write and comment
When valence timing, evaluation information is read from data/address bus, the target sender label in detection information screens, and obtains current
To the evaluation result of sender's output information prediction, cognitive algorithm is adjusted using the result.
7. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the input module is from institute
It states chip input pin and obtains data, and be converted to the output interface that unified information format is temporarily stored in the input module, to
The input layer bus sends information to the data/address bus when being polled to the module.
8. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the output module is in institute
It states output layer bus to enter when reading information timing, information is read from the data/address bus, and be forwarded to chip output and draw
Foot.
9. multi-core sensing data according to claim 1 handles chip, it is characterised in that: the function of the control module
Can include:
With the bus marco core communication, the synthesis of each active output end output information on the data/address bus is obtained
Assessment result is dynamically determined the data processing core distributed on each data/address bus according to the comprehensive assessment result, and leads to
Know the bus marco core active data processing core output end and input terminal；
It is communicated with the input selector, the active input terminal is accessed to the input interface of the data processing core,
Its inactive input terminal is isolated with connected data/address bus；
It is communicated with the outlet selector, the active output end is accessed to the output interface of the data processing core,
Its inactive output end is isolated with connected data/address bus.
10. a kind of operation method of multi-core sensing data processing chip, the multi-core sensing data processing chip are adopted
Chip is handled with the multi-core sensing data as described in any one of claim 1-10, special medical treatment is: the operation
Method includes:
Data information inputs the multi-core data processing chip by the input module；
The control module generates corresponding control signal according to the data/address bus output information to configure at each data
Manage the connection relationship of core and each data/address bus；
The data processing core is become according to the data information in conjoint data bus using different Matching Model adaptation datas
Change model and exports predictive information；
The predictive information of data processing core output on the bus marco core readout data bus, carries out synthesis and comments
Valence obtains comprehensive evaluation result；
The bus marco core notifies the control module to adjust the data processing core according to the comprehensive evaluation result
Configuration between different data bus；It controls the data processing core and carries out further Matching Model, until obtaining most
Excellent matching result；Send the matching result to the output module of the chip.
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