CN102710890A - Video processing on-chip system of double AHB (Advanced High Performance Bus) buses - Google Patents
Video processing on-chip system of double AHB (Advanced High Performance Bus) buses Download PDFInfo
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Abstract
The invention discloses a video processing on-chip system of double AHBs (advanced high performance buses), which improves the system reliability and the data transmission speed. The video processing on-chip system comprises two sets of AHBs which are used as inner high-speed data channels, and one set of AHB; one set of AHB is connected with a processor, a common internal memory controller, an Ethernet MAC, a debugging supporting unit and a video coder-decoder; the common internal memory controller is connected with an external storage and the external storage is used as an internal memory for operating the processor and is also used as a display buffer memory of an OSD (on-screen display) image and the video coder-decoder; the other AHB is connected with a video input processing unit, a video debugging unit and an SDRAM (synchronous dynamic random access memory) controller; the SDRAM controller is connected with an external SDRAM; the SDRAM is used as a display buffer memory of a video input channel and a PIP (picture-in-picture) video; an APB (advanced peripheral bus) is connected to the AHB through an AHB/APB bridge; the APB is connected to a slow-speed IO (input/output) equipment controller and an access module register; and a video output processing unit is connected between the two sets of the AHBs, and the video output processing unit utilizes a direct internal memory accessing manner to read data of the two sets of the AHBs.
Description
Technical field
The present invention relates to a kind of Video processing SOC(system on a chip), specifically, relate to a kind of Video processing SOC(system on a chip) that improves two ahb bus of system reliability and message transmission rate.
Background technology
Ahb bus is a kind of industrial bus standard that ARM company formulates, and is mainly used in the SOC(system on a chip) to connect between the high-performance module, and it comprises following characteristics: the operation of single clock edge; The implementation of non-three-state; Support burst transfer; Support segment transmissions; Support a plurality of master controllers; Configurable 32～128 highway widths; Support the transmission of byte, nibble and word.The AHB system is by primary module, form from module and foundation structure (Infrastructure) three parts; Transmission on the whole ahb bus is all sent by primary module; And by being responsible for response from module, foundation structure then by moderator (arbiter), primary module to from the Port Multiplier of module, from the module to the primary module Port Multiplier, decoder (decoder), virtually form from module (dummy Slave) and virtual primary module (dummy Master).
Develop rapidly along with microelectric technique; The design of integrated circuit special module has changed the design of reusable IP kernel gradually into; An important feature of the design of reusable IP kernel will be followed standardization exactly; Connecting interface with standard is so that design I P nuclear energy enough is conveniently used in other system.What traditional Video processing SoC system adopted is the mode of single cover bus; Processor, DSP, memory interface all directly hang on the bus; Because the exclusivity of bus operation; But main equipment occupies bus when operating, and other main equipment can only wait for, this mode of operation makes the inefficiency of system; In the improved strategy of another kind, use double bus system, and link to each other through bus bridge, the operation two cover buses in same bus are independent respectively; But concurrent working; But when striding bus operation, like the slave unit on the main equipment access bus 2 on the bus 1, bus 2 is monopolized equally so; Can not carry out other operation, this can have influence on the performance of system equally.
Summary of the invention
To above deficiency, the invention provides a kind of Video processing SOC(system on a chip) that improves two ahb bus of system reliability and message transmission rate, it adopts the bus of the complete independent operation of two covers, and carries out data at output and integrate.
The Video processing SOC(system on a chip) of of the present invention pair of ahb bus comprises the ahb bus of two covers as the inner high speed data channel; And two ahb bus controllers of controlling two cover ahb bus respectively; Wherein a cover ahb bus connects general high-performance treatments unit; Another set of ahb bus connects the video performance units, and the video output processing module is connected between the two cover ahb bus, and the video output processing module adopts the mode of direct memory access to read the data on the two cover ahb bus.
Said general high-performance treatments unit comprises processor, universal memory controller, ethernet mac controller and video coder-decoder.
Said general high-performance treatments unit also comprises debug support unit.
Said universal memory controller connects external memory storage, and external memory storage is as the internal memory of processor operation, simultaneously also as the display buffer of OSD image and coding and decoding video.
Said external memory storage is Flash and SRAM, and Flash is as solid-state storage, and SRAM is as the internal memory of processor operation.
Said external memory storage is Flash and SDRAM, and Flash is as solid-state storage, and SDRAM is as the internal memory of processor operation.
Said video performance units comprises video input processing unit and sdram controller, and sdram controller connects outside SDRAM, and this SDRAM is as video channel input and PIP video displaying buffer memory.
Be connected with IO device controller and access modules register at a slow speed on the ahb bus that general high-performance treatments unit links to each other.
Said IO device controller is connected the APB bus with the access modules register, and the APB bus is connected to ahb bus through the AHB/APB bridging.
Said IO device controller comprises serial ports controller, I2C master controller, universal I, SPI controller, timer and terminal control unit.
Beneficial effect of the present invention: the Video processing SOC(system on a chip) of of the present invention pair of ahb bus comprises the ahb bus of two covers as the inner high speed data channel, and wherein a cover ahb bus connects general high-performance treatments unit, and another set of ahb bus connects the video performance units; The video output processing module is connected between the two cover ahb bus; The mode of direct memory access that adopts the video output processing module reads the data on the two cover ahb bus, and two cover ahb bus are separate, do not have principal and subordinate's bus; Do not link to each other through bus bridge yet; Two-part read operation is independent of each other, and can carry out simultaneously, improves the treatment effeciency of system; In addition, the present invention adopts standard A MBA interface standard, and the high-performance module adopts ahb bus to carry out transfer of data, and slow devices controller and register interface adopt the APB bus to carry out transfer of data, and framework has the flexibility of height.
Description of drawings
Fig. 1 is the system framework figure of the Video processing SOC(system on a chip) of of the present invention pair of ahb bus;
Fig. 2 is the annexation sketch map of external memory storage of the present invention;
Fig. 3 is that memory contents of the present invention is divided sketch map;
Fig. 4 is that osd function of the present invention is realized schematic diagram;
Fig. 5 is that book article input processing unit of the present invention is realized schematic diagram.
Embodiment
Below in conjunction with accompanying drawing the present invention is further set forth.
As shown in Figure 1; The Video processing SOC(system on a chip) (SoC) of of the present invention pair of ahb bus has ahb bus and the cover APB bus of two covers as the inner high speed data channel; Two cover ahb bus connect ahb bus controller separately respectively; Connecting general high-performance treatments unit such as processor, ethernet mac controller, debug support unit, universal memory controller and Video Codec on the ahb bus 1, and the AHB/APB bridge, what this cover bus was paid attention to is the general purpose control function; What connect on the ahb bus 2 is video performance units such as video input processing unit, sdram controller and video debugging unit, the Video processing of the high speed that this cover bus is paid attention to.In addition, two cover ahb bus all connect video output processing unit, and this is that this framework video converges interface point.When ahb bus 1 carried out operate as normal, as drawing the OSD image, it did not take any clock cycle of ahb bus 2; It is same when ahb bus 2 carries out operate as normal; When input is gathered like video, also be complete operation on ahb bus 2 fully, do not take ahb bus 1.At output, the video output processing unit initiatively external memory storage on two cover ahb bus obtains data, and two-part read operation is independent of each other, and can carry out simultaneously, therefore improves the treatment effeciency of system.
SoC of the present invention has connected two parts memory; As shown in Figure 2, wherein connecting the universal memory controller on the ahb bus 1, the universal memory controller can connect external memory storages such as Flash, SRAM and SDRAM; Wherein Flash is as solid-state storage; The information of stored program firmware and preservation, optional SRAM of internal memory or SDRAM are as main memory and the video memory of OSD image and the video memory of coding and decoding video of running software in the system.On ahb bus 1, connecting sdram controller, sdram controller connects outside SDRAM chip, as the video memory of video main channel and the video memory of PIP passage.As shown in Figure 3; The space that each several part is stored on the memory is independently; Nonoverlapping; And confirm the address space that each main equipment can be visited, can visit whole external memory storage on the ahb bus 1, and video output processing unit can only be visited OSD video memory and coding and decoding video video memory on the ahb bus 1 like processor.
The OSD view data of framework of the present invention is drawn by processor and is formed, and it is write in the OSD video memory, reads conversion output by video output unit at last; As shown in Figure 4, processor is responsible for the OSD view data and is generated, and this accomplishes through the OSD application program of moving on the processor is auxiliary; The OSD applications specify variation of OSD graph image, which type of osd data decision produces, the OSD application program is after confirming to produce data; To data be write in the OSD video memory through Memory Controller Hub, the OSD video memory is one section memory space that is used to preserve the OSD picture opening up among the RAM, in the OSD application program; The OSD video memory is mapped as the space, a part of address of bus address; If the use (SuSE) Linux OS can be mapped in the virtual frames buffer memory of Linux in this section OSD video memory, with the frame buffer of (SuSE) Linux OS as the OSD picture that shows; On the other hand, video output processing unit is connected to the universal memory controller through ahb bus 1, the data read in the OSD video memory is taken out, and carry out correct output through after the extension process.
Video processing passage and OSD treatment channel are similar, and different is that the OSD treatment channel is on ahb bus 1, to accomplish, and produces osd data by processor; And the Video processing passage is accomplished on ahb bus 2 buses, is produced by the video input processing unit, and the video input is handled to produce and comprised two parts; A part is main Video processing passage, and another part is the PIP treatment channel, after the video input is handled and is created in the reception data; Be kept among the inner FIFO, then with packing data, using fixedly, burst transfer is transferred to sdram controller with data through ahb bus 2; Write data in the video memory by sdram controller again; Also be through the AHB interface video data to be read out at last, and after processing, show, with reference to shown in Figure 5 by video output unit.
The present invention adopts the interface of AHB as the high-performance module; Adopt the access interface of APB as slow-side module; The AHB/APB bridging is connected on the AHB1 bus, to make things convenient for processor the APB bus is conducted interviews, and on the APB bus, hangs IO device controller at a slow speed; Like serial ports controller, I2C controller, universal I controller, SPI controller, timer and interrupt control unit etc.; In addition, the register of high-speed module also conducts interviews through the APB interface, and promptly the access modules register also can be connected to the APB bus; High-speed module such as video input processing module, video output processing module, sdram controller and ethernet controller etc. pass through register configuration; Make it change working method, each module on the APB bus all is mapped as space, a part of address on AHB, and the operation of APB bus upper module is actually the operation to this address space.
The above is merely preferred embodiments of the present invention; The present invention is not limited to above-mentioned execution mode; In implementation process, possibly there is local small structural modification; If various changes of the present invention or modification are not broken away from the spirit and scope of the present invention, and belong within claim of the present invention and the equivalent technologies scope, then the present invention also is intended to comprise these changes and modification.
Claims (10)
1. the Video processing SOC(system on a chip) of two ahb bus; It is characterized in that; It comprises the ahb bus of two covers as the inner high speed data channel; And two ahb bus controllers of controlling two cover ahb bus respectively, wherein a cover ahb bus connects general high-performance treatments unit, and another set of ahb bus connects the video performance units; The video output processing module is connected between the two cover ahb bus, and the video output processing module adopts the mode of direct memory access to read the data on the two cover ahb bus.
2. the Video processing SOC(system on a chip) of pair ahb bus according to claim 1 is characterized in that, said general high-performance treatments unit comprises processor, universal memory controller, ethernet mac controller and video coder-decoder.
3. the Video processing SOC(system on a chip) of pair ahb bus according to claim 1 is characterized in that, said general high-performance treatments unit also comprises debug support unit.
4. the Video processing SOC(system on a chip) of pair ahb bus according to claim 2; It is characterized in that; Said universal memory controller connects external memory storage, and external memory storage is as the internal memory of processor operation, simultaneously also as the display buffer of OSD image and coding and decoding video.
5. the Video processing SOC(system on a chip) of pair ahb bus according to claim 4 is characterized in that, said external memory storage is Flash and SRAM, and Flash is as solid-state storage, and SRAM is as the internal memory of processor operation.
6. the Video processing SOC(system on a chip) of pair ahb bus according to claim 4 is characterized in that, said external memory storage is Flash and SDRAM, and Flash is as solid-state storage, and SDRAM is as the internal memory of processor operation.
7. the Video processing SOC(system on a chip) of pair ahb bus according to claim 1; It is characterized in that; Said video performance units comprises video input processing unit, video debugging unit and sdram controller; Sdram controller connects outside SDRAM, and this SDRAM is as video channel input and PIP video displaying buffer memory.
8. the Video processing SOC(system on a chip) of pair ahb bus according to claim 1 is characterized in that, and is connected with IO device controller and access modules register at a slow speed on the ahb bus that general high-performance treatments unit links to each other.
9. the Video processing SOC(system on a chip) of pair ahb bus according to claim 8 is characterized in that, said IO device controller is connected the APB bus with the access modules register, and the APB bus is connected to ahb bus through the AHB/APB bridging.
10. the Video processing SOC(system on a chip) of pair ahb bus according to claim 8 is characterized in that, said IO device controller comprises serial ports controller, I2C master controller, universal I, SPI controller, timer and terminal control unit.
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| CN103279776A (en) * | 2013-05-06 | 2013-09-04 | 中山大学 | Chip structure applicable to two-dimensional bar code decoding chip |
| CN104021104A (en) * | 2014-06-12 | 2014-09-03 | 国家电网公司 | Collaborative system based on dual-bus structure and communication method thereof |
| CN104750425A (en) * | 2013-12-30 | 2015-07-01 | 国民技术股份有限公司 | Storage system and control method for nonvolatile memory of storage system |
| CN105320637A (en) * | 2015-10-23 | 2016-02-10 | 西安中科晶像光电科技有限公司 | FLASH data read circuit |
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| CN109656477A (en) * | 2018-12-11 | 2019-04-19 | 华中科技大学 | A kind of contact type intelligent card SoC based on STT-MRAM |
| CN112035398A (en) * | 2020-08-25 | 2020-12-04 | 青岛信芯微电子科技股份有限公司 | System-level chip SoC and data processing method applicable to SoC |
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| CN102063396A (en) * | 2009-11-18 | 2011-05-18 | 意法-爱立信公司 | Method and device for transmitting data between master blocks on chip and SOC (System on a Chip) |
| CN103279776A (en) * | 2013-05-06 | 2013-09-04 | 中山大学 | Chip structure applicable to two-dimensional bar code decoding chip |
| CN103279776B (en) * | 2013-05-06 | 2016-06-22 | 中山大学 | A kind of chip architecture suitable in two-dimensional bar code decoding chip |
| CN104750425A (en) * | 2013-12-30 | 2015-07-01 | 国民技术股份有限公司 | Storage system and control method for nonvolatile memory of storage system |
| CN104750425B (en) * | 2013-12-30 | 2018-12-18 | 国民技术股份有限公司 | A kind of control method of storage system and its nonvolatile memory |
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| CN106303152A (en) * | 2015-05-25 | 2017-01-04 | 聚晶半导体股份有限公司 | Picture processing chip and image processing system |
| CN105320637A (en) * | 2015-10-23 | 2016-02-10 | 西安中科晶像光电科技有限公司 | FLASH data read circuit |
| CN105677609A (en) * | 2016-01-04 | 2016-06-15 | 上海华力创通半导体有限公司 | Bus structure of SoC system |
| CN109656477B (en) * | 2018-12-11 | 2020-05-19 | 华中科技大学 | STT-MRAM-based non-contact smart card SoC |
| CN109656477A (en) * | 2018-12-11 | 2019-04-19 | 华中科技大学 | A kind of contact type intelligent card SoC based on STT-MRAM |
| CN112035398A (en) * | 2020-08-25 | 2020-12-04 | 青岛信芯微电子科技股份有限公司 | System-level chip SoC and data processing method applicable to SoC |
| CN112035398B (en) * | 2020-08-25 | 2023-10-24 | 青岛信芯微电子科技股份有限公司 | System-on-chip (SoC) and data processing method suitable for SoC |
| CN114257717A (en) * | 2020-09-25 | 2022-03-29 | 北京小米移动软件有限公司 | Electronic device |
| CN114257717B (en) * | 2020-09-25 | 2024-05-31 | 北京小米移动软件有限公司 | Electronic equipment |
| CN113296908A (en) * | 2021-04-30 | 2021-08-24 | 重庆紫光华山智安科技有限公司 | Method, device, equipment and medium for improving video image access speed |
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| CN113868070B (en) * | 2021-09-23 | 2023-08-25 | 山东云海国创云计算装备产业创新中心有限公司 | SD card controller debugging method, system, storage medium and device |
| CN114564427A (en) * | 2022-03-01 | 2022-05-31 | 四川创安微电子有限公司 | Bus bridge, system and method from AHB bus to I2C bus |
| CN114564427B (en) * | 2022-03-01 | 2023-06-23 | 四川创安微电子有限公司 | Bus bridge, system and method from AHB bus to I2C bus |
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