CN114564427B

CN114564427B - Bus bridge, system and method from AHB bus to I2C bus

Info

Publication number: CN114564427B
Application number: CN202210199034.2A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Sichuan Chuang'an Microelectronics Co ltd
Current assignee: Sichuan Chuang'an Microelectronics Co ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2023-06-23
Anticipated expiration: 2042-03-01
Also published as: CN114564427A

Abstract

The invention discloses a bus bridge from an AHB bus to an I2C bus, a system and a method thereof, wherein the bus bridge comprises an AHB slave module, a register module, a data cache module, a security configuration module, a transmission control module, an I2C host module, an abnormality detection module and an interrupt control module; the AHB bus protocol is mapped to an I2C bus protocol by the bus bridge. The bus bridge system comprises an AHB host, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, wherein the AHB host is connected with the bus bridge through AHB bus communication, and the bus bridge is connected with the plurality of I2C slaves through I2C bus communication. The invention processes the transmission communication of the cross-bus protocol through the bus bridge based on the SoC chip needing to use various multiplexing IP; the transition from the quick transmission rate of the AHB to the low transmission rate of the I2C is realized; the invention realizes the address width configuration function of the internal register of the I2C slave.

Description

Bus bridge, system and method from AHB bus to I2C bus

Technical Field

The invention relates to the technical field of buses, in particular to a bus bridge from an AHB bus to an I2C bus, a system and a method.

Background

With the increasing maturity of deep submicron process technologies, the scale of integrated circuit chips is increasing. Digital ICs have evolved from a design method based on timing driving to a design method based on IP (Intellectual Property) multiplexing, and have been widely used in System-on-chip (SoC) design. In SoC designs based on IP multiplexing, on-chip bus design is the most critical issue, for which many on-chip bus standards are emerging in the industry. Among them, AMBA on-chip buses introduced by ARM corporation are favored by IP developers and SoC system integrators, and have become a popular industry standard on-chip architecture. The AMBA specification mainly includes an AHB system bus and an APB system bus. In the fields of industrial control, consumer electronics, digital video, communication equipment and the like, soC chips occupy a large share by the design of AMBA bus architecture. I2C (Inter-Intergrated Circut) is one of the most commonly used serial communication buses, implemented and applied on more than 100 different ICs. Numerous devices with I2C interfaces are also being introduced by large semiconductor companies, such as RAM, EEPROM, flash ROM, A/D, D/A conversion, LED/LCD drive, real time clock, etc.

As chip complexity/functionality/scalability increases, more and more IP devices with I2C bus interfaces need to be integrated in SoC chips of AMBA architecture. However, the use of devices with I2C bus interfaces in these socs is limited because AMBA buses do not have I2C bus interfaces. In order for a processor to access an IP with an I2C interface over an AHB bus interface, the IP interface needs to be modified to be compatible with the state of the AHB bus protocol. Such modifications are very disadvantageous for multiplexing of IP.

In addition, different I2C slave devices can design different I2C transmission formats according to their own characteristics, which causes great difficulty when the I2C devices are integrated into the same system.

The AHB bus is a system module for high performance, high clock frequency, while the I2C bus is a system module for low clock frequency, and simple protocol conversion may cause the AHB bus to be occupied for a long period of time.

Disclosure of Invention

The invention aims to solve the technical problem of providing a bus bridge, a system and a method from an AHB bus to an I2C bus, which mainly realize conversion from the AHB protocol to the I2C protocol and achieve the purposes of effective transmission of different bus data and forwarding processing of control signals on different buses.

In addition, the bus bridge is compatible with communication between I2C devices having different I2C transmission formats; the data transmission format is configurable (different sizes of I2C slave internal register addresses, single transmission data size) according to different slave device types connected to the I2C bus, and portability and reusability of the IP with the I2C interface are improved. Furthermore, the bus bridge has a security configuration function, which can secure important data (core code/important parameters/data marking user identity) in the memory unit of a specific slave. In addition, in the bus bridge system, the AHB host can be released after the command transmission to the I2C slave machine is completed, so that the problem that the low-speed I2C bus occupies the high-speed AHB bus for a long time is avoided, the burden of the AHB host is reduced, and the working efficiency of the AHB host is improved.

The invention is realized by the following technical scheme:

in a first aspect, the present invention provides a bus bridge from an AHB bus to an I2C bus, mapping an AHB bus protocol to an I2C bus protocol through the bus bridge; the bus bridge is used as a host of an I2C bus and is also used as a slave of an AHB advanced system bus; and receiving a transmission instruction from the AHB host through the AHB bus, analyzing the transmission instruction, converting the transmission instruction into a transmission instruction conforming to an I2C protocol, and sending out the I2C transmission instruction through the I2C bus to communicate with the I2C slave. For a write transfer instruction, the bus bridge sends data to the corresponding I2C slave via the I2C bus after receiving the target address, transfer data, and necessary control information from the AHB host. For a read transmission instruction, after receiving a target address and necessary control information from the AHB host, the bus bridge reads data from a corresponding I2C slave through an I2C bus and caches the data, and after I2C transmission is completed, the AHB host is informed to read cached read data.

The bus bridge structure: the bus bridge comprises an AHB slave module, a register module, a data cache module, a transmission control module and an I2C host module;

the AHB slave module is used as an interface of an AHB bus, receives an access request from an AHB bus host, and realizes read-write access to a register module in a bus bridge through the AHB bus to realize data information exchange between the register module and the AHB bus; the data storage module is used for storing data into the data cache module during writing transmission and reading read data from the data cache module when reading transmission is completed;

The register module is a cluster of registers and is used for storing a transmission instruction from an AHB bus to an I2C bus, wherein the transmission instruction comprises a transmitted target address, necessary control information and a bus bridge state;

the data buffer module is used for temporarily storing transmission data in a read-write working state, and comprises write transmission data stored in an AHB host and read transmission data received from an I2C slave;

the transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and realizing the trigger mark judging function of the transmission instruction; the address forwarding from the register module to the I2C host module, the write data forwarding from the data cache module to the I2C host module and the read data forwarding from the I2C host module to the data cache module are realized; and realizing a state feedback function to the register module; and implementing an address width configuration function from the register module to the I2C host module;

the I2C host module is used for controlling the SCL line/SDA line to generate I2C transmission according to the transmission command transmitted from the transmission control module.

Further, the transmission control module is configured to implement an address forwarding function from the register module to the I2C host module, and includes:

According to the data forwarding request sent by the I2C host module, the I2C slave address and the I2C slave internal register address are taken out from the register module and sent to the I2C host module through a data writing channel;

the transmission control module is used for writing data forwarding functions from the data caching module to the I2C host module; comprising the following steps:

according to the I2C host module, sending a write data forwarding request, taking out write data from the data cache module, and sending the write data to the I2C host module through a write data channel;

the transmission control module is used for reading data forwarding function from the I2C host module to the data caching module; comprising the following steps:

and sending a read data forwarding request according to the I2C host module, acquiring read data from the read data channel, and storing the read data into the data caching module.

Further, in order to be able to correspond to different types of I2C slave devices, a configurable data transmission format (I2C slave device internal register addresses with different sizes, continuous transmission sizes) is added, and system communication based on different formats of the I2C bus is compatible. The transmission control module realizes the address width configuration function from the register module to the I2C host module, so that the bus bridge supports the setting of the address width range of 1-7 bytes, and is suitable for I2C slaves of different types.

The CR1 register of the register module is responsible for coordinating the address width during I2C transmission; aiming at different I2C slaves, the AHB master configures parameters of a CR1 register, and a transmission control module acquires an I2C slave internal register address with a corresponding width (1-7) byte from a CR4 register according to a value of the CR1 register (3 bit).

The transmission control module realizes the address width configuration function from the register module to the I2C host module, and the specific implementation process comprises the following steps:

waiting for a data forwarding request of the I2C host module;

according to the data forwarding request of the I2C host module, the address of an internal register of the I2C slave is taken out from the CR4 register and is sent to the I2C host module through a data writing channel, and the register address is added with 1 by a written-section counter;

the value representing the address width is taken out from the CR1 register, compared with the value of the written section counter of the register address, if the value is consistent, the completion of the register address transmission is represented, and the next step is carried out to judge the transmission direction according to the value of the CR3 register; otherwise, entering a data forwarding request waiting for the I2C host module, and continuing to send the rest I2C slave internal register addresses.

Further, considering the security requirement in SoC design, the bus bridge of the present invention has a security configuration function, and can perform security protection on important data (core code/important parameter/data marking user identity) in the memory unit of a specific slave.

The bus bridge further comprises a security configuration module; the security configuration module is used for identifying the transmission of the set I2C slave or the set address inside the I2C slave and informing the transmission control module, so as to realize the security protection of (core codes/important parameters/data marking the user identity).

Further, the security protection mechanism of the security configuration module comprises a global protection unit and a local protection unit;

the global protection unit is used for protecting the whole I2C slave, and the address of the I2C slave needing to be protected is pre-stored in the global protection unit;

the local protection unit is used for protecting the I2C slave machine internal set storage unit, and the I2C slave machine address and the corresponding register address which need to be protected are pre-stored in the local protection unit.

Further, the security configuration module sends a transmission permission state/a transmission prohibition state to the transmission control module through a transmission enabling signal, wherein the transmission enabling signal comprises two states of 1:transmission permission and 0:transmission prohibition, and the specific judging modes of the transmission permission and the transmission prohibition are as follows:

the method comprises the steps that an I2C slave address and a register address of a transmission object are obtained from a register module;

performing permission judgment of the global protection unit, namely comparing the I2C slave address of the transmission object obtained from the register module with the slave address of the pre-stored global protection unit, and judging whether the I2C slave address is consistent with the slave address of the pre-stored global protection unit; if the transmission is consistent, transmission is forbidden; if the local protection unit is inconsistent, entering permission judgment of the local protection unit, namely comparing the I2C slave address of the transmission object obtained from the register module with the slave address pre-stored in the local protection unit, and judging whether the local protection unit is consistent; if not, transmitting permission; if yes, continuing to judge whether the register address of the transmission object is obtained from the register module in the protection range, namely comparing the register address with the corresponding register address pre-stored in the local protection unit, and judging whether the register address is consistent; if the transmission is consistent, transmission is forbidden, otherwise, transmission permission is considered.

Further, the bus bridge further comprises an abnormality detection module and an interrupt control module;

the abnormality detection module is used for detecting the action of the I2C host module and sending the detection result to the interrupt control module for processing;

the interrupt control module is used for controlling the generation of interrupt signals according to the transmission completion state, the transmission prohibition state and the detection result of the abnormality detection module of the transmission control module.

Further, the I2C host module comprises SCL generation logic, SDA generation logic and a state machine;

the SCL generation logic and the SDA generation logic generate an SCL/SDA bus conforming to an I2C protocol according to data from a transmission control module;

and the state machine controls the generation and transmission states of the data forwarding request, the starting condition, the repeated starting condition, the stopping condition and the ACK/NACK to be returned to the abnormality detection module.

Further, the data caching module comprises a control unit and a data storage unit;

the control unit is used for receiving control signals and data signals from the transmission control module and the AHB slave module, wherein the control signals are used as enabling signals for controlling the data storage unit to read or write; the data signal is used as a data transmission channel for transmitting written or read data;

The data storage unit is used for being composed of readable and writable register units and assembled into an 8-bit (width) multiplied by 255 (depth) storage unit; storing write data from the AHB bus setting during write transfer and storing read data from the transfer control module during read transfer;

when the AHB host writes data to the I2C slave, the write data from the AHB host is stored in the data storage unit, and the data written by the AHB host are sequentially read out under the control of the transmission control module; when the AHB host reads data from the I2C slave, the data read back by the I2C host module is stored in the data storage unit; after the completion of the storing, the data from the I2C slave is read out from the data caching module by the AHB host to the AHB bus.

In a second aspect, the present invention further provides a bus bridge system from an AHB bus to an I2C bus, the bus bridge system including an AHB host, an AHB bus, a bus bridge, an I2C bus, and a plurality of I2C slaves, the AHB host being communicatively connected to the bus bridge through the AHB bus, the bus bridge being communicatively connected to the plurality of I2C slaves through the I2C bus;

wherein the bus bridge employs an AHB bus to I2C bus bridge.

In a third aspect, the present invention further provides a bus bridge control method from an AHB bus to an I2C bus, where the control method is applied to the bus bridge from the AHB bus to the I2C bus, and the control method includes:

Step A, acquiring a write data forwarding request of an AHB host to an internal register of an I2C slave, and waiting for the completion of AHB host setting;

step B, enabling a data transmission start signal, taking out a slave address from a CR0 register, splicing the transmission direction W at the tail to form data of one byte (namely 7 bits of the slave address and 1bit writing), and transmitting the data to an I2C host module through a data writing channel;

step C, waiting for a data forwarding request of the I2C host module, if the data forwarding request exists, taking out an internal register address of the I2C slave from the CR4 register, and sending the internal register address to the I2C host module through a data writing channel, wherein a written-section counter of the register address is increased by 1; if the data forwarding request does not exist, waiting for the data forwarding request of the I2C host module all the time;

step D, judging whether the register address is sent out, if yes, judging the transmission direction according to the value of the CR3 register, and if yes, entering step E; if not, executing a data read forwarding request; if the register address is not sent, waiting for a data forwarding request of the I2C host module, and continuing to send the remaining register addresses in the I2C slave;

e, waiting for a data forwarding request of the I2C host module, if the data forwarding request exists, taking out one byte of data from the data cache module, sending the data to the I2C host module through a data writing channel, and adding 1 to a written byte counter of the data writing; if the data forwarding request does not exist, waiting for the data forwarding request of the I2C host module all the time;

Step F, judging whether the data transmission is completed or not, if the data transmission is completed, waiting for a data forwarding request of the I2C host module; if the data is not sent, waiting for the data forwarding request of the I2C host module to continuously send the rest write data;

and G, enabling a data transmission ending signal, and ending.

Further, the executing the data read forwarding request specifically includes:

step H, enabling a data transmission start signal, taking out a slave address from a CR0 register, splicing the transmission direction R at the tail to form data of one byte (namely 7 bits of the slave address and 1bit of reading), and transmitting the data to an I2C host module through a data writing channel;

step I, waiting for a data forwarding request of an I2C host module, and initializing a read data receiving byte counter to be 1;

step J, if a data forwarding request exists, acquiring a value representing the transmission size from a CR2 register, comparing the value with a value of a read data receiving byte counter, judging whether the values are consistent, if so, driving a write data channel to be 1, notifying an I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to be 0, and notifying the I2C host to generate ACK in the next response pulse period; if no data forwarding request exists, waiting for the data forwarding request of the I2C host module all the time;

Step K, waiting for a data forwarding request of the I2C host module, receiving read data from a read data channel, storing the read data into a data caching module, and adding 1 to a read data receiving byte counter;

and step L, acquiring a value representing the transmission size from the CR2 register, comparing the value with the value of the read data receiving byte counter, if the value of the counter minus 1 is equal to the value of the CR2 register, representing that the read data transmission is completed and entering step H, otherwise, entering step J.

Further, in the step D, the judgment criterion for judging whether the register address is sent is: fetching a value representing the address width from the CR1 register, comparing the value with the value of the register address written section counter, and if the value is consistent, representing that the register address transmission is completed; otherwise, the register address is not sent to be completed;

and F, judging whether the data transmission is finished or not according to the following criteria: acquiring a value representing the transmission size from a CR2 register, comparing the value with the value of a written section counter of written data, and if the value is consistent, representing that the data transmission is completed; otherwise, the data is not sent completely.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the invention processes the transmission communication of the cross-bus protocol through the bus bridge based on the SoC chip needing to use various multiplexing IP; the transition from the fast transmission rate of the AHB to the low transmission rate of the I2C is achieved.

2. According to the invention, the continuous AHB transmission can be buffered, and continuous read transmission or continuous write transmission of 255Byte data is supported at maximum;

3. the invention reduces the requirement of transmitting the subsequent time sequence, avoids frequent bus operation and reduces the burden of an AHB host;

4. according to the invention, the AHB host does not need to occupy the bus for a long time to wait for the feedback of the I2C slave, so that the working efficiency of the AHB host is improved;

5. the invention has the function of safety configuration, can protect core data and improves the safety between systems;

6. the invention realizes the address width configuration and the continuous transmission size configuration of the internal register of the I2C slave, namely the I2C transmission format is configurable, has high compatibility and can communicate with different I2C devices based on different formats of the I2C bus.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:

FIG. 1 is a schematic diagram of an AHB to I2C bus bridge configuration according to the present invention;

FIG. 2 is a schematic diagram of connection of an AHB slave module according to the present invention;

FIG. 3 is a schematic diagram illustrating a structure of a data buffer module according to the present invention;

FIG. 4 is a flow chart of the security configuration module of the present invention;

FIG. 5 is a counter counting flow chart of the present invention;

FIG. 6 is a comparison flow chart of the comparator of the present invention;

FIG. 7 is a block diagram illustrating a configuration of an I2C host module according to the present invention;

FIG. 8 is a timing diagram of I2C read/write transmissions according to the present invention;

FIG. 9 is a flowchart illustrating operation of the bus bridge of the present invention;

FIG. 10 is a flow chart of READ WRITE/WRITE READ of the registers in the slave I2C to the AHB master according to the present invention.

Detailed Description

For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.

Example 1

As shown in fig. 1 to 8, a bus bridge of an AHB bus to an I2C bus of the present invention maps an AHB bus protocol to an I2C bus protocol through the bus bridge; the bus bridge is used as a host of an I2C bus and is also used as a slave of an AHB advanced system bus; and receiving a transmission instruction from the AHB host through the AHB bus, analyzing the transmission instruction, converting the transmission instruction into a transmission instruction conforming to an I2C protocol, and sending out the I2C transmission instruction through the I2C bus to communicate with the I2C slave. For a write transfer instruction, the bus bridge sends data to the corresponding I2C slave via the I2C bus after receiving the target address, transfer data, and necessary control information from the AHB host. For a read transmission instruction, after receiving a target address and necessary control information from the AHB host, the bus bridge reads data from a corresponding I2C slave through an I2C bus and caches the data, and after I2C transmission is completed, the AHB host is informed to read cached read data.

The bus bridge also has a safety configuration function, and can carry out safety protection on important data (core codes/important parameters/data marking user identity) in the storage unit of the specific slave.

Meanwhile, in order to be capable of corresponding to different types of I2C slave machine parts, the configurable data transmission formats (I2C slave machine internal register addresses with different sizes and continuous transmission sizes) are added, and the system communication based on different formats of I2C buses is compatible.

As shown in fig. 1, the bus bridge has the following structure: the bus bridge comprises an AHB slave module, a register module, a data cache module, a security configuration module, a transmission control module, an I2C host module, an abnormality detection module and an interrupt control module.

the security configuration module is used for identifying the transmission of a specific I2C slave or a specific address inside the I2C slave and notifying the transmission control module, so as to realize the security protection of transmission data (core codes/important parameters/data marking user identity).

The transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and realizing the trigger mark judging function of the transmission instruction; the address forwarding from the register module to the I2C host module, the write data forwarding from the data cache module to the I2C host module and the read data forwarding from the I2C host module to the data cache module are realized; and realizing a state feedback function to the register module; and implementing an address width configuration function from the register module to the I2C host module; specifically:

the transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and sending trigger marks of the I2C starting condition, the repeated starting condition and the ending condition to the I2C host module; according to the data forwarding request sent by the I2C host module, the slave address required by I2C transmission, the internal register address of the I2C slave and the like are taken out from the data buffer module during writing transmission, writing data are sent to the I2C host module for processing through a writing data channel, reading transmission data received by the reading data channel are buffered to the data buffer module during reading the data, and after transmission is completed, a transmission completion state is sent to the interrupt control module for processing; and receiving a transmission enabling signal (high: transmission permission, low: transmission prohibition) from the security configuration module, and if transmission permission is indicated, letting the I2C host module enter an operating state; if transmission prohibition is indicated, the I2C host module is not allowed to enter a working state, and the current AHB-to-I2C protocol conversion is directly ended. And sending the transmission completion state to the interrupt control module for processing.

The I2C host module is used for controlling the SCL line/SDA line to generate I2C transmission according to the transmission command transmitted from the transmission control module. Specifically:

the I2C host module is used for controlling the SCL/SDA line to generate I2C transmission according to the information such as the I2C starting condition, the repeated starting condition, the triggering sign of the ending condition, the slave address, the internal register address of the I2C slave or the data and the like from the transmission control module. Read data is driven into the read data channel during an I2C read transfer. The transmission status (busy/idle) is returned to the register module and the abnormality detection module. And returning the starting condition, the repeated starting condition, the stopping condition and the ACK/NACK to the abnormality detection module.

The working principle of each module in the bus bridge is as follows:

1. AHB slave machine module

The AHB slave module is used as an interface of an AHB bus, receives address, data information and the like from the AHB bus, can perform information transmission with the register module, drives read-write control signals of a corresponding register, and realizes read-write operation of the register. The data can be stored in the data buffer module during writing transmission, and the read data can be read out from the data buffer module when reading transmission is completed. As shown in fig. 2, fig. 2 is a schematic connection diagram of an AHB slave module.

2. Register module

The partial registers contained in the register modules are listed in table 1 below.

Table 1 register list

Register name	Bit width	Description of the invention
			CR0	7	I2C slave address setting
CR1	3	I2C slave internal register address width (3 'b000-2' b111:0 bytes-7 bytes)
			CR2	8	Setting of continuous transmission size (8 'h 00-8' hff:0 bytes-255 bytes)
CR3	1	Transmission direction setting (1 'b0: write transmission; 1' b1: read transmission)
			CR4	32	I2C slave internal register address
CR5	3	Interrupt clearing
			CR6	3	Interrupt masking
CR7	1	AHB setting completion register (AHB host after sending instruction and data)
			DR0	n	Timeout comparison register (threshold setting)
SR0 (read-only)	1	I2C bus status (high: busy; low: idle)
			SR1 (read-only)	1	Abnormal state of transmission (high: ERROR; low: OK)
SR2 (read-only)	1	Transmission complete status (high: complete; low: incomplete)
			SR3 (read-only)	2	Abnormality flag register (indicating which abnormality has occurred)

3. Data caching module

FIG. 3 is a schematic diagram of a data buffer module structure shown in FIG. 3; the data caching module comprises a control unit and a data storage unit;

the main functions of the data caching module are as follows:

4. Security configuration module

The bus bridge has a safety configuration function in consideration of the safety requirement in SoC design, and can carry out safety protection on important data (core codes/important parameters/data marking user identity) in a storage unit of a specific slave. Thus, the present invention contemplates a security configuration module.

The security protection mechanism of the security configuration module comprises a global protection unit and a local protection unit;

the local protection unit is used for protecting some specific storage units in the I2C slave, and the I2C slave address to be protected and the corresponding register address are pre-stored in the local protection unit.

For security protection of data (core code/important parameters/data marking user identity). It is emphasized here that unlike the data mask (DQM) technique, the data mask: when read, the masked data is still transferred out of the memory bank, but is masked at the control I/O port. The safety configuration module saves part of time and reduces electric quantity consumption.

The security configuration module transmits a transmission permission state/a transmission prohibition state to the transmission control module through transmission enabling signals (1: transmission permission and 0: transmission prohibition); as shown in fig. 4, the specific determination manners of transmission permission and transmission prohibition are:

firstly, carrying out permission judgment of a global protection unit, namely comparing an I2C slave address of a transmission object obtained from a register module with a slave address pre-stored in the global protection unit, and judging whether the addresses are consistent; if the transmission is consistent, transmission is forbidden; if the local protection unit is inconsistent, entering permission judgment of the local protection unit, namely comparing the I2C slave address of the transmission object obtained from the register module with the slave address pre-stored in the local protection unit, and judging whether the local protection unit is consistent; if not, transmitting permission; if yes, continuing to judge whether the register address of the transmission object is obtained from the register module in the protection range, namely comparing the register address with the corresponding register address pre-stored in the local protection unit, and judging whether the register address is consistent; if the transmission is consistent, transmission is forbidden, otherwise, transmission permission is considered.

5. Abnormality detection module

The abnormality detection module may correspond to an abnormality including:

(1) the Timeout of the I2C slave, which is not responded for a long time, is abnormal, and the abnormality can cause that the I2C master module cannot respond for a long time after initiating transmission.

(2) When the non-existent I2C slave is accessed, the access abnormality can cause that the I2C host can not respond after initiating a slave address.

Aiming at the abnormality of the (1), a specific embodiment provided by the invention is as follows:

in the anomaly detection module, a Timer counter is designed. The counting flow is shown in fig. 5.

The counter counts when the I2C host is performing an I2C transfer, and stops counting when the I2C host is not performing an I2C transfer.

In order to acquire whether the I2C host is performing an I2C transmission, the I2C host module is required to transmit a flag signal, such as busy signal, indicating whether the I2C is transmitting.

The timer counter initiates at the I2C transmission: starting condition, repeating the starting condition, responding to the pulse, and resetting when stopping the condition.

And a Timeout comparison register is designed in the register module, and the Timeout comparison register can be configured by the AHB host. The compare register workflow is shown in fig. 6.

Comparing the sizes of the timer counter and the Timeout comparison register, when the value of the timer counter is larger than the value of the Timeout comparison register, it indicates that the I2C does not obtain a response for a long time in the transmission process, and a Timeout flag signal is generated.

The timeout mark signal is output to the transmission control module, so that the transmission control module can initiate a data transmission stop signal to stop the transmission of the current I2C.

And transmitting the timeout flag signal to the interrupt control module so as to enable the interrupt control module to inform the AHB host that the current transmission is not completed.

Aiming at the abnormality of the (2), a specific embodiment provided by the invention is as follows:

in the anomaly detection module, after the I2C master module initiates the I2C transmission start/restart signal, it is detected whether the address response bit has a slave response (during the 9 th SCL pull-up period), and if there is no slave response, an access anomaly flag signal is generated.

And feeding the access abnormality flag signal back to the transmission control module, so that the transmission control module initiates a stop signal to stop the current transmission.

And transmitting the access exception flag signal to the interrupt control module to enable the interrupt control module to inform the AHB host that the current transmission is not completed. For (1) and (2), an exception flag register may be designed in the register module to indicate whether or not an exception has occurred and what kind of exception has occurred.

6. Interrupt control module

Aiming at the interrupt control module, a specific implementation scheme provided by the invention is as follows:

and summarizing the abnormal mark signals input by the abnormal detection module and the transmission completion signals input by the transmission control module to generate a unified interrupt signal, and outputting the unified interrupt signal to the AHB host.

And an interrupt clearing register is designed in the register module and is used for clearing interrupt signals. An interrupt mask register is designed for masking interrupt signals.

The interrupt signal is cleared in the interrupt control module according to the value of the interrupt clearing register. For example, the AHB host may configure the register to clear the interrupt after having received the interrupt.

Masking of interrupt signals is controlled in an interrupt control module according to the value of an interrupt mask register. This register may be configured to mask interrupts, for example, when interrupts are not desired to be used in the system.

7. I2C host module

As shown in fig. 7, the I2C host module includes an SCL generating logic, SDA generating logic and state machine;

As shown in fig. 8, fig. 8 is a timing diagram of a transmit mode (WRITE) and a receive mode (READ) when the bus bridge is hosting, and it can be found that the connection between data is through a data forwarding request. And controlling the SCL/SDA to generate a starting condition and a stopping condition according to the data transmission starting signal and the data transmission ending signal sent by the transmission control module. And giving a data forwarding request during a response pulse (ACK/NACK), and sending the data forwarding request to a transmission control module to request for preparation for data forwarding. After the data forwarding request is sent, the data is sent out through the SDA according to the data which is driven to the data writing channel by the transmission control module. During a read transfer, the I2C host module generates a response or no response during a response pulse depending on the value of the write data channel. When the value of the write data channel is 0, the next data byte is required to be received, and ACK (response) is generated; when the value of the write data channel is 1, it indicates that all data bytes are received, and NACK (non-response) is generated, notifying the slave transmitter of the end of data. And confirming the transmission state of the I2C bus according to the starting condition and the stopping condition, and sending the transmission state to the register module and the abnormality detection module.

8. Transmission control module

The transmission control module mainly has the following functions:

(1) Trigger mark judgment (transmission control module→i2C host module)

A data transmission start signal and a data transmission end signal are given.

(2) Address forwarding (register module- & gttransmission control module- & gtI 2C host module)

The I2C host module sends out a data forwarding request, and an I2C slave address and an I2C slave internal register address are taken out of a register according to the data request and sent to the I2C host module through a data writing channel.

(3) Write data forwarding (data buffer module- & gttransmission control module- & gtI 2C host module)

The I2C host module sends out a data forwarding request, write data is taken out from the data caching module according to the data forwarding request, and the write data is sent to the I2C host module through the write data channel.

(4) Read data forwarding (I2C host module- & gt transmission control module- & gt data buffer module)

And the I2C host module sends out a data forwarding request, acquires read data from the read data channel according to the data forwarding request, and stores the read data into the data caching module.

(5) Status feedback (transmission control module→register module)

When the read data are all cached in the data caching module, the state is fed back to a state register of the register module and is used as information to be sent to the interrupt control module, and the AHB host is marked to start to acquire the read data from the data caching module.

(6) Abnormality correspondence (abnormality detection module→transmission control module→i2c host module)

When an abnormality flag signal of the abnormality detection module is received, the data transmission end signal is directly enabled, so that the I2C host module generates an I2C stop condition, and current transmission is stopped.

(7) Safety protection process (abnormality detection module- & gttransmission control module- & gtI 2C host module)

Receiving a transmission enabling signal (the generation of which refers to fig. 4) of the security configuration module, and when the enabling signal is high (transmission permission), performing the conversion from AHB to I2C protocol normally; when the enable signal is low (transmission disabled), the data transmission start signal is not enabled, the I2C host module is not enabled to enter a working state, at the moment, the I2C bus state register is kept in an idle state, the current AHB-to-I2C protocol conversion is directly ended, and meanwhile, the transmission completion state is input to the interrupt control module for processing. The AHB host is notified that the transfer is complete and if it is the case for a read transfer, the read data returns a value of zero.

(8) I2C slave internal register address width configuration function (register module→transmission control module→I2C host module)

The function is a main design point of a transmission control module, and is to be capable of corresponding to different types of I2C slave machine parts, add the configurable data transmission formats (I2C slave machine internal register addresses with different sizes and continuous transmission sizes) and be compatible with system communication with different formats based on an I2C bus. The transmission control module realizes the address width configuration function from the register module to the I2C host module, so that the bus bridge supports the setting of the address width range of 1-7 bytes, is used for adapting to different types of I2C slaves, and has configurable data transmission format.

The address width of the I2C slave internal registers varies depending on the device type. For example, the internal address width of the EEPROM memory (AT 24C 04) is one byte, and the internal address width of the EEPROM memory (AT 24C 64) is two bytes. Specifically, the number of bytes, the address field may be one byte, two bytes long, etc., depending on the number of memory cells of the device. In view of this, the bus bridge of the present invention supports setting of address width (1-7 bytes range) to accommodate different I2C slaves. The CR1 register of the register module is responsible for coordinating the address width at I2C transmission. Aiming at different I2C slaves, the AHB master configures parameters of a CR1 register, and a transmission control module acquires an I2C slave internal register address with a corresponding width (1-7) byte from a CR4 register according to a value of the CR1 register (3 bit).

The transmission control module realizes the address width configuration function from the register module to the I2C host module, and comprises the following components:

waiting for a data forwarding request of the I2C host module;

The value representing the address width is taken out from the CR1 register, compared with the value of the written section counter of the register address, if the value is consistent, the completion of the register address transmission is represented, and the transmission direction is judged according to the value of the CR3 register; otherwise, entering a data forwarding request waiting for the I2C host module, and continuing to send the rest I2C slave internal register addresses.

(9) Transmission size configuration (register Module→Transmission control Module→I2C host Module)

In order to improve transmission efficiency, for continuous address access of the AHB host to the I2C slave, the bus bridge supports setting of single I2C transmission data size (1-255 bytes) so as to adapt to more application scenes. The CR2 register of the register module is responsible for coordinating the data size of the I2C transmissions. The AHB host configures parameters of a CR2 register, a transmission control module continuously writes write data into an internal register of the I2C slave according to a value of the register CR2 (8 bit), if the write transmission is performed, the read data is continuously received from the I2C slave, and if the read transmission is performed, the transmitted data is equal to a size set by the CR2 register, the I2C read-write transmission is ended. Write transfers refer to control flow steps 9-13 of embodiment 3 and read transfers refer to control flow steps 17-21 of embodiment 3.

With more and more IP integration into SoC designs, the AHB bus alone has failed to meet the communication needs. Based on SoC chips needing to use various multiplexing IP, the transmission communication of the cross-bus protocol is processed through the bus bridge of the invention; the transition from the fast transmission rate of the AHB to the low transmission rate of the I2C is achieved.

1. The continuous read transmission or the continuous write transmission of 255Byte data can be supported maximally by caching the continuous AHB transmission;

2. the requirement of transmitting the subsequent time sequence is reduced, frequent bus operation is avoided, and the burden of an AHB host is reduced;

3. the AHB host does not need to occupy a bus for a long time to wait for the feedback of the I2C slave, so that the working efficiency of the AHB host is improved;

4. the system has a safety configuration function, can protect core data and improves the safety between systems;

5. the method realizes the address width configuration and the continuous transmission size configuration of the internal register of the I2C slave, namely the I2C transmission format is configurable, has high compatibility and can communicate with different I2C devices based on different formats of I2C buses.

Example 2

As shown in fig. 1 to 8, the present embodiment differs from embodiment 1 in that it provides a bus bridge system from an AHB bus to an I2C bus, the bus bridge system including an AHB host, an AHB bus, a bus bridge, an I2C bus, and a plurality of I2C slaves, the AHB host being communicatively connected to the bus bridge through the AHB bus, the bus bridge being communicatively connected to the plurality of I2C slaves through the I2C bus;

Wherein the bus bridge employs an AHB bus to I2C bus bridge of embodiment 1.

Example 3

As shown in fig. 9 and 10, the difference between the present embodiment and embodiment 1 is that the present embodiment provides a bus bridge control method from an AHB bus to an I2C bus, which is applied to a bus bridge from an AHB bus to an I2C bus described in embodiment 1, and the control method includes:

step D, judging whether the register address is sent out, if yes, judging the transmission direction according to the value of the CR3 register, and if yes, entering step E; if not, executing a data read forwarding request; if the register address is not sent, waiting for a data forwarding request of the I2C host module, and continuing to send the remaining register addresses in the I2C slave; the judgment basis for judging whether the register address is sent out is as follows: fetching a value representing the address width from the CR1 register, comparing the value with the value of the register address written section counter, and if the value is consistent, representing that the register address transmission is completed; otherwise, the register address is not sent to be completed;

step F, judging whether the data transmission is completed or not, if the data transmission is completed, waiting for a data forwarding request of the I2C host module; if the data is not sent, waiting for the data forwarding request of the I2C host module to continuously send the rest write data; the basis for judging whether the data transmission is completed is as follows: acquiring a value representing the transmission size from a CR2 register, comparing the value with the value of a written section counter of written data, and if the value is consistent, representing that the data transmission is completed; otherwise, the data is not sent completely;

and G, enabling a data transmission ending signal, and ending.

Specifically, the executing the data read forwarding request specifically includes:

In specific implementation, according to the READ WRITE/WRITE READ flow of the AHB host to the internal register of the I2C slave, the bus bridge executes the following control flow, as shown in fig. 9, and fig. 9 is a working flow chart of the bus bridge. The specific control flow comprises the following steps:

1. Starting;

2. waiting for the AHB host to complete the setting;

3. a data transmission start signal enable;

4. the slave address is taken out from the CR0 register, the transmission direction (W) is spliced at the tail end to form data of one byte, and the data is sent to the I2C host module through a data writing channel;

5. waiting for a data forwarding request of the I2C host module;

6. the method comprises the steps of taking out an internal register address of an I2C slave from a CR4 register, sending the internal register address to an I2C host module through a write data channel, and adding 1 to a written section counter of the register address;

7. taking out the value representing the address width from the CR1 register, comparing with the value of the written section counter of the register address, if the value is consistent, representing that the register address is sent completely, and entering the step 8, otherwise, entering the step 5 to continue sending the remaining I2C slave machine internal register address;

8. judging the transmission direction according to the value of the CR3 register, if the transmission is writing, entering a step 9, otherwise, entering a step 15;

9. waiting for a data forwarding request of the I2C host module;

10. taking out one byte of data from the data cache module, sending the data to the I2C host module through a data writing channel, and adding 1 to a written byte counter of the data writing;

11. acquiring a value representing the transmission size from a CR2 register, comparing the value with the value of a written-data written-section counter, if so, representing whether the data transmission is completed or not, and entering a step 12, otherwise, entering a step 9 to continue transmitting the rest of the written data;

12. Waiting for a data forwarding request of the I2C host module;

13. a data transmission end signal enable;

14. ending;

15. a data transmission start signal enable;

16. the slave address is taken out from the CR0 register, the transmission direction (R) is spliced at the tail end to form data of one byte, and the data is sent to the I2C host module through a data writing channel;

17. waiting for a data forwarding request of the I2C host module, and initializing a read data receiving byte counter to be 1;

18. acquiring a value representing the transmission size from a CR2 register, comparing the value with a value of a read data receiving byte counter, judging whether the values are consistent, driving a write data channel to be 1 if the values are consistent, informing an I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to be 0, and informing the I2C host to generate ACK in the next response pulse period;

19. waiting for a data forwarding request of the I2C host module;

20. receiving read data from the read data channel, storing the read data into the data buffer module, and adding 1 to the read data receiving byte counter;

21. a value representing the transfer size is obtained from the CR2 register, compared to the value of the read data receive byte counter, if the value of the counter minus 1 equals the value of the CR2 register, indicating that the read data transfer is complete and proceeding to step 13, otherwise proceeding to step 18.

As shown in fig. 10, fig. 10 is a flow chart of READ WRITE/WRITE READ of the internal registers of the I2C slave by the AHB master.

A basic transfer information from the AHB host includes the following information:

1) I2C slave address

2) Sub-addresses (indexes) pointing to registers within the slave

3) Direction of transmission (read/write)

4) Sub-address (index) bit width of slave internal registers

The present bus bridge supports a setting of a range of 1 to 7 bytes for the sub-address bit widths of the slave internal registers, so that the AHB master needs to include information indicating the sub-address (index) bit width of the slave internal registers when transmitting transmission control information.

5) Transmission size

When the data bytes for continuous access are different, the present bus bridge supports the setting of the continuous transmission data size (1-255 bytes), so the AHB host needs to include information indicating the transmission size when sending the transmission control information.

6) Writing data

Case 1: WRITE of the AHB master to the I2C slave internal registers

1. Starting;

the AHB host confirms that the bus bridge is idle;

3. setting the slave address to a CR0 register;

4. setting a transmission direction to a CR3 register;

5. setting the address width of the slave internal register to a CR1 register;

6. Setting the internal register address of the transmitted I2C slave to a CR4 register;

7. setting a transmission data size to a CR2 register;

8. setting write data to be transmitted to a data caching module;

9. setting a CR7 register and informing the bus bridge AHB host of finishing setting;

10. and (5) ending.

Case 2: [ AHB Master READs the internal registers of the I2C Slave ]

1. Starting;

the AHB host confirms that the bus bridge is idle;

3. setting the slave address to a CR0 register;

4. setting a transmission direction to a CR3 register;

5. setting the address width of the slave internal register to a CR1 register;

7. setting a transmission data size to a CR2 register;

8. setting a CR7 register and informing the bus bridge AHB host of finishing setting;

9. interrupt generation, namely confirming that the transmission of the SR2 register is completed, if so, entering a step 10, otherwise, carrying out exception handling;

10. reading out read data from the data caching module;

11. and (5) ending.

The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A bus bridge from an AHB bus to an I2C bus, which is characterized by comprising an AHB slave module, a register module, a data cache module, a transmission control module and an I2C host module; mapping an AHB bus protocol into an I2C bus protocol through a bus bridge;

the AHB slave module is used for receiving an access request of the AHB host, realizing read-write access to the register module through an AHB bus and realizing a data information exchange function of the register module and the AHB bus;

the register module is used for storing transmission instructions from the AHB bus to the I2C bus;

the transmission control module is used for realizing the trigger mark judging function of the transmission instruction; the address forwarding from the register module to the I2C host module, the write data forwarding from the data cache module to the I2C host module and the read data forwarding from the I2C host module to the data cache module are realized; and realizing a state feedback function to the register module; and implementing an address width configuration function from the register module to the I2C host module;

And an I2C host module for controlling the SCL line/SDA line according to the information transmitted from the transmission control module to generate an I2C transmission.

2. The AHB-to-I2C bus bridge of claim 1, wherein the transfer control module is configured to implement an address forwarding function from the register module to the I2C host module, comprising:

3. The AHB bus-to-I2C bus bridge of claim 1 or 2, wherein the transfer control module implements an address width configuration function from the register module to the I2C host module, so that the bus bridge supports setting of an address width in a range of 1-7 bytes for adapting to different types of I2C slaves, and the data transfer format is configurable; the transmission control module realizes the address width configuration function from the register module to the I2C host module, and comprises the following components:

Waiting for a data forwarding request of the I2C host module;

4. The AHB-to-I2C bus bridge of claim 1, wherein the bus bridge further comprises a security configuration module;

the security configuration module is used for identifying the transmission of the set I2C slave or the set address inside the I2C slave and notifying the transmission control module to realize the security protection of the transmission data.

5. The AHB-to-I2C bus bridge of claim 4, wherein the security configuration module comprises a global protection unit and a local protection unit;

6. The AHB-to-I2C bus bridge of claim 5, wherein the security configuration module communicates a transmission permission status/transmission prohibition status to the transmission control module via a transmission enable signal, the transmission enable signal including a transmission permission and a transmission prohibition; the specific judging modes of transmission permission and transmission prohibition are as follows:

7. The bus bridge of an AHB bus to I2C bus of claim 1, further comprising an anomaly detection module, an interrupt control module;

8. The AHB-to-I2C bus bridge of claim 7, wherein the I2C host module comprises SCL generation logic, SDA generation logic, and a state machine;

the state machine controls the generation of the data forwarding request and returns the transmission state, the starting condition, the repeated starting condition, the stopping condition and the ACK/NACK to the abnormality detection module.

9. The AHB-to-I2C bus bridge of claim 1, wherein the data cache module comprises a control unit and a data storage unit;

the data storage unit is used for being composed of readable and writable register units and assembled into 8bit multiplied by 255 storage units; storing write data from the AHB bus setting during write transfer and storing read data from the transfer control module during read transfer;

10. The bus bridge system from the AHB to the I2C is characterized by comprising an AHB host, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, wherein the AHB host is connected with the bus bridge through AHB bus communication, and the bus bridge is connected with the plurality of I2C slaves through I2C bus communication;

Wherein the bus bridge employs an AHB bus to I2C bus bridge according to any of claims 1 to 9.

11. A bus bridge control method of an AHB bus to an I2C bus, the control method being applied to a bus bridge of an AHB bus to an I2C bus as set forth in any one of claims 1 to 9, the control method comprising:

step B, enabling a data transmission start signal, taking out a slave address from a CR0 register, splicing the transmission direction W at the tail to form data of one byte, and transmitting the data to an I2C host module through a data writing channel;

and G, enabling a data transmission ending signal, and ending.

12. The bus bridge control method as set forth in claim 11, wherein said executing a data read forwarding request comprises:

step H, enabling a data transmission start signal, taking out a slave address from a CR0 register, splicing a transmission direction R at the tail to form data of one byte, and transmitting the data to an I2C host module through a data writing channel;

Step J, acquiring a value representing the transmission size from a CR2 register, comparing the value with a value of a read data receiving byte counter, judging whether the values are consistent, driving a write data channel to be 1 if the values are consistent, notifying an I2C host to generate NACK in the next response pulse period, otherwise driving the write data channel to be 0, and notifying the I2C host to generate ACK in the next response pulse period;

13. The bus bridge control method from an AHB bus to an I2C bus according to claim 11, wherein the determination in step D is based on whether the register address is sent out: fetching a value representing the address width from the CR1 register, comparing the value with the value of the register address written section counter, and if the value is consistent, representing that the register address transmission is completed; otherwise, the register address is not sent to be completed;