CN114564427A

CN114564427A - Bus bridge, system and method from AHB bus to I2C bus

Info

Publication number: CN114564427A
Application number: CN202210199034.2A
Authority: CN
Inventors: 不公告发明人
Original assignee: Sichuan Chuang'an Microelectronics Co ltd
Current assignee: Sichuan Chuang'an Microelectronics Co ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-05-31
Anticipated expiration: 2042-03-01
Also published as: CN114564427B

Abstract

The invention discloses a bus bridge, a system and a method from an AHB bus to an I2C bus, wherein the bus bridge comprises an AHB slave module, a register module, a data cache module, a safety configuration module, a transmission control module, an I2C host module, an abnormity detection module and an interrupt control module; the AHB bus protocol is mapped to the I2C bus protocol through the bus bridge. The bus bridge system comprises an AHB host, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, wherein the AHB host is in communication connection with the bus bridge through the AHB bus, and the bus bridge is in communication connection with the I2C slaves through the I2C bus. The invention processes transmission communication of a cross-bus protocol through the bus bridge of the invention based on the SoC chip which needs to use various multiplex IPs; the transition from the fast transmission rate of the AHB to the low transmission rate of I2C is realized; the invention realizes the address width configuration function of the I2C slave internal register.

Description

Bus bridge, system and method from AHB bus to I2C bus

Technical Field

The invention relates to the technical field of buses, in particular to a bus bridge, a system and a method from an AHB bus to an I2C bus.

Background

As deep sub-micron process technology matures, integrated circuit chips are scaled larger and larger. Digital ICs have been developed from a design method based on timing driving to a design method based on ip (intelligent performance) multiplexing, and have been widely used in System-on-chip (SoC) design. In SoC designs based on IP multiplexing, on-chip bus design is the most critical issue, and for this reason, many on-chip bus standards are emerging in the industry. Among them, the AMBA on-chip bus proposed by ARM corporation is favored by wide IP developers and SoC system integrators, and has become a popular industry standard on-chip structure. The AMBA specification mainly includes an AHB system bus and an APB system bus. In SoC chips in the fields of industrial control, consumer electronics, digital video, communication equipment, etc., the design of AMBA bus architecture occupies a large share. I2C (Inter-interleaved Circut) is implemented and applied on over 100 different ICs as one of the most commonly used serial communication buses. A large number of devices with I2C interfaces such as RAM, EEPROM, Flash ROM, A/D, D/A converter, LED/LCD driver, real time clock, etc. are also being introduced by large semiconductor companies.

As chip complexity/functionality/scalability increases, more and more IP devices with I2C bus interfaces need to be integrated in the SoC chip of the AMBA architecture. But since AMBA bus does not have an I2C bus interface, the use of devices with an I2C bus interface in these socs is limited. In order for a processor to access an IP with an I2C interface through the AHB bus interface, the interface of the IP needs to be modified to a state compatible with the AHB bus protocol. Such a modification is very disadvantageous for multiplexing of IP.

In addition, different I2C slave devices can design different I2C transmission formats according to their own characteristics, which causes great difficulty when these I2C devices are integrated into the same system.

The AHB bus is a system module for high performance and high clock frequency, and the I2C bus is a system module for low clock frequency, and simple protocol conversion causes the AHB bus to be occupied for a long time.

Disclosure of Invention

The technical problem to be solved by the present invention is to provide a bus bridge, a system and a method for converting an AHB bus to an I2C bus, wherein the bus bridge mainly realizes the conversion from an AHB protocol to an I2C protocol, and achieves the purpose of effective transmission of different bus data and forwarding processing of control signals on different buses.

In addition, the bus bridge is compatible with communication between I2C devices with different I2C transmission formats; according to the type of the slave devices connected to the I2C bus, the data transmission format is configurable (I2C slave internal register addresses with different sizes and the size of single-transmission data), and the portability and reusability of the IP with the I2C interface are improved. Furthermore, the bus bridge has a safety configuration function, and can perform safety protection on important data (core codes/important parameters/data for marking user identities) in the storage unit of a specific slave. In addition, in the bus bridge system, the AHB host can be released after the command transmission to the I2C slave device is completed, so that the problem that the low-speed I2C bus occupies the high-speed AHB bus for a long time is avoided, the burden of the AHB host is reduced, and the working efficiency of the AHB host is improved.

The invention is realized by the following technical scheme:

in a first aspect, the present invention provides a bus bridge from an AHB bus to an I2C bus, through which an AHB bus protocol is mapped to an I2C bus protocol; the bus bridge is used as a master of an I2C bus and is also used as a slave of an AHB advanced system bus; the transmission command from the AHB host is received through the AHB bus, the transmission command is analyzed and converted into the transmission command conforming to the I2C protocol, and the I2C transmission command is sent out through the I2C bus to be communicated with the I2C slave. For a write transfer command, the bus bridge sends data to the corresponding I2C slave via the I2C bus after receiving the target address, transfer data, and necessary control information from the AHB master. For the read transmission instruction, the bus bridge reads and buffers data from the corresponding I2C slave through the I2C bus after receiving the target address and necessary control information from the AHB host, and notifies the AHB host to read the buffered read data after completing the I2C transmission.

The bus bridge has the structure that: the bus bridge comprises an AHB slave module, a register module, a data cache module, a transmission control module and an I2C host module;

the AHB slave module is used as an interface of an AHB bus, receives an access request from an AHB bus host, realizes read-write access to a register module in the bus bridge through the AHB bus, and realizes data information exchange between the register module and the AHB bus; the data cache module is used for storing data into the data cache module during write transmission and reading read data out of the data cache module when read transmission is finished;

the register module is a cluster of registers and is used for storing a transmission instruction from an AHB bus to an I2C bus, wherein the transmission instruction comprises a transmission target address, necessary control information and a bus bridge state;

the data cache module is used for temporarily storing transmission data in a read-write working state, wherein the transmission data comprise write transmission data stored from an AHB host and read transmission data received from an I2C slave;

the transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and realizing the trigger mark judgment function of the transmission instruction; and address forwarding from the register module to the I2C host module, write data forwarding from the data cache module to the I2C host module, and read data forwarding from the I2C host module to the data cache module; and implementing a state feedback function to the register module; and to implement address width configuration functions from the register module to the I2C host module;

the I2C host module is used for controlling the SCL line/SDA line to generate I2C transmission according to the transmission instruction transmitted from the transmission control module.

Further, the transmission control module is configured to implement an address forwarding function from the register module to the I2C host module, and includes:

according to the data forwarding request sent by the I2C host module, the I2C slave address and the I2C slave internal register address are taken out of the register module and sent to the I2C host module through the write data channel;

the transmission control module is used for writing data forwarding function from the data cache module to the I2C host module; the method comprises the following steps:

according to the fact that the I2C host module sends out a write data forwarding request, write data are taken out of the data cache module and sent to the I2C host module through a write data channel;

the transmission control module is used for reading data forwarding function from the I2C host module to the data cache module; the method comprises the following steps:

according to the I2C, the host module sends out a read data forwarding request, obtains read data from the read data channel and stores the read data into the data buffer module.

Furthermore, in order to correspond to different types of I2C slave devices, the configurability of data transmission formats (I2C slave internal register addresses with different sizes, continuous transmission sizes) is added, and system communication with different formats based on the I2C bus is compatible. The transmission control module realizes the address width configuration function from the register module to the I2C host module, so that the bus bridge supports the setting of the address width within the range of 1-7 bytes, and can be adapted to different types of I2C slaves.

The CR1 register of the register module is responsible for coordinating the address width for I2C transmission; aiming at different I2C slaves, the AHB host configures parameters of a CR1 register, and a transmission control module acquires an I2C slave internal register address corresponding to 1-7 bytes in width from a CR4 register according to the value of a CR1 register (3 bit).

The transmission control module realizes the address width configuration function from the register module to the I2C host module, and the specific implementation process comprises the following steps:

waiting for a data forwarding request of the I2C host module;

according to a data forwarding request of the I2C host module, an I2C slave internal register address is taken out from a CR4 register and sent to the I2C host module through a write data channel, and a written byte counter of the register address is increased by 1;

taking out the value representing the address width from the CR1 register, comparing the value with the value of the register address written byte counter, if the value is consistent, representing that the register address is sent completely, and proceeding to the next step to judge the transmission direction according to the value of the CR3 register; otherwise, the data forwarding request of the host module of the I2C is waited, and the rest I2C slave internal register addresses are sent continuously.

Further, in consideration of the requirement of security in SoC design, the bus bridge of the present invention has a security configuration function, and can perform security protection on important data (core code/important parameter/data for marking user identity) in the memory unit of a specific slave.

The bus bridge also comprises a safety configuration module; the safety configuration module is used for identifying the transmission of the set address in the I2C slave machine or the I2C slave machine and informing the transmission control module to realize the safety protection of (core code/important parameter/data marking the user identity).

Further, the security protection mechanism of the security configuration module comprises a global protection unit and a local protection unit;

the global protection unit is used for protecting the whole I2C slave, and the address of the I2C slave needing protection is prestored in the global protection unit;

the local protection unit is used for protecting the I2C slave internal setting storage unit, and the I2C slave address to be protected and the corresponding register address are pre-stored in the local protection unit.

Further, the security configuration module sends a transmission permission state/a transmission prohibition state to the transmission control module through a transmission enabling signal, where the transmission enabling signal includes two states of transmission permission 1: and transmission prohibition 0: and the specific determination manner of transmission permission and transmission prohibition is:

acquiring an I2C slave machine address and a register address of a transmission object from a register module;

carrying out permission judgment of the global protection unit, namely comparing the address of the I2C slave machine of the transmission object obtained from the register module with the address of the slave machine prestored in the global protection unit, and judging whether the addresses are consistent; if the two are consistent, transmission is prohibited; if the addresses are inconsistent, entering permission judgment of the local protection unit, namely comparing the address of the I2C slave machine of the transmission object obtained from the register module with the address of the slave machine prestored in the local protection unit, and judging whether the addresses are consistent; if not, transmitting the permission; if the register addresses are consistent, whether the register addresses of the transmission objects acquired from the register module are in the protection range is continuously judged, namely the register addresses are compared with the corresponding register addresses prestored in the local protection unit, and whether the register addresses are consistent is judged; if so, transmission is prohibited, otherwise transmission is permitted.

Furthermore, the bus bridge also comprises an abnormality detection module and an interrupt control module;

the abnormality detection module is used for detecting the action of the I2C host module and sending the detection result to the interrupt control module for processing;

and the interrupt control module is used for controlling the generation of an interrupt signal according to the transmission completion state and the transmission prohibition state of the transmission control module and the detection result of the abnormality detection module.

Further, the I2C host module includes an SCL generation logic, SDA generation logic, and a state machine;

the SCL generation logic and the SDA generation logic generate an SCL/SDA bus conforming to an I2C protocol according to data from the transmission control module;

the state machine controls the generation and transmission state of the data forwarding request, the starting condition, the repeated starting condition, the stopping condition and the ACK/NACK to be returned to the abnormity detection module.

Further, the data caching module comprises a control unit and a data storage unit;

the control unit is used for receiving control signals and data signals from the transmission control module and the AHB slave module, wherein the control signals are used as enabling signals for controlling the data storage unit to read or write; the data signal is used as a data transmission channel and is used for transmitting written or read data;

the data storage unit is composed of a readable and writable register unit and assembled into a storage unit of 8bit (width) multiplied by 255 (depth); storing write data from the AHB bus setting during write transfer and storing read data from the transfer control module during read transfer;

when the AHB host writes data to the I2C slave, the write data from the AHB host is stored in the data storage unit, and the data written by the AHB host is read out in sequence under the control of the transmission control module; when the AHB host reads data from the I2C slave, the data read back by the I2C host module is stored into the data storage unit; after the logging is completed, the AHB master reads data from the I2C slave to the AHB bus from the data cache module.

In a second aspect, the present invention further provides a bus bridge system from an AHB bus to an I2C bus, where the bus bridge system includes an AHB host, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, the AHB host is connected to the bus bridge through the AHB bus in a communication manner, and the bus bridge is connected to the plurality of I2C slaves through the I2C bus in a communication manner;

wherein, the bus bridge adopts a bus bridge from AHB bus to I2C bus.

In a third aspect, the present invention further provides a method for controlling a bus bridge from an AHB bus to an I2C bus, where the method is applied to the bus bridge from the AHB bus to the I2C bus, and the method includes:

step A, acquiring a write data forwarding request of an AHB host to an I2C slave internal register, and waiting for the AHB host to complete setting;

step B, enabling a data transmission starting signal, taking out a slave address from a CR0 register, splicing the tail of the slave address in a transmission direction W to form data of one byte (namely the slave address is 7bit + write 1bit), and sending the data to the I2C host module through a data writing channel;

step C, waiting for a data forwarding request of the I2C host module, if the data forwarding request exists, taking out an I2C slave internal register address from the CR4 register, sending the address to the I2C host module through a data writing channel, and adding 1 to a written byte counter of the register address; if the data forwarding request does not exist, the data forwarding request of the I2C host module is waited for all the time;

step D, judging whether the register address is sent completely, if the register address is sent completely, judging the transmission direction according to the value of the CR3 register, and if the register address is write-transmission, entering the step E; if not, executing data read forwarding request; if the register address is not sent completely, waiting for a data forwarding request of the I2C host module, and continuously sending the residual I2C slave internal register addresses;

step E, waiting for a data forwarding request of the I2C host module, if the data forwarding request exists, taking out data of one byte from the data cache module, sending the data to the I2C host module through a data writing channel, and adding 1 to a written data byte counter; if the data forwarding request does not exist, the data forwarding request of the I2C host module is always waited;

step F, judging whether the data transmission is finished or not, and if the data transmission is finished, waiting for a data forwarding request of the I2C host module; if the data is not sent completely, waiting for the data forwarding request of the I2C host module to continue sending the rest write data;

and G, enabling a data transmission end signal, and ending.

Further, the executing data read forwarding request specifically includes:

step H, enabling a data transmission starting signal, taking out a slave address from the CR0 register, splicing the slave address at the tail of the slave address in the transmission direction R to form data of one byte (namely slave address 7bit + read 1bit), and sending the data to the I2C host module through a data writing channel;

step I, waiting for a data forwarding request of the host module I2C, and initializing a read data receiving byte counter to be 1;

step J, if a data forwarding request exists, acquiring a value representing transmission size from a CR2 register, comparing the value with a value of a read data receiving byte counter, judging whether the values are consistent, if so, driving a write data channel to be 1, informing the I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to be 0, and informing the I2C host to generate ACK in the next response pulse period; if no data forwarding request exists, the data forwarding request of the I2C host module is waited for all the time;

step K, waiting for a data forwarding request of the I2C host module, receiving read data from the read data channel, storing the read data into the data cache module, and adding 1 to a read data receiving byte counter;

and step L, acquiring a value representing the transmission size from the CR2 register, comparing the value with the value of the read data receiving byte counter, if the value of the counter minus 1 is equal to the value of the CR2 register, representing that the read data transmission is finished, and entering step H, otherwise, entering step J.

Further, the judgment basis for whether the register address is sent in step D is as follows: taking out the value representing the address width from the CR1 register, comparing the value with the value of the register address written byte counter, and if the values are consistent, representing that the register address is sent out completely; otherwise, the register address is not sent to be completed;

the judgment basis for whether the data transmission is completed in the step F is as follows: obtaining a value representing the transmission size from a CR2 register, comparing the value with the value of a written byte counter of the write data, and if the values are consistent, representing that the data transmission is finished; otherwise, it indicates that the data transmission is not completed.

Compared with the prior art, the invention has the following advantages and beneficial effects:

1. the invention processes transmission communication of a cross-bus protocol through the bus bridge of the invention based on the SoC chip which needs to use various multiplex IPs; the transition from the fast transmission rate of the AHB to the low transmission rate of I2C is achieved.

2. The invention can buffer the AHB continuous transmission and support the 255Byte data continuous read transmission or continuous write transmission to the maximum;

3. the invention reduces the requirement of transmitting the subsequent time sequence, avoids frequent bus operation and lightens the burden of the AHB host;

4. the AHB host does not need to occupy the bus for a long time to wait for the feedback of the I2C slave machines, so that the working efficiency of the AHB host is improved;

5. the invention has the function of safe configuration, can protect the core data and improve the safety among systems;

6. the invention realizes the I2C slave internal register address width configuration and the continuous transmission size configuration, namely the I2C transmission format is configurable, has high compatibility, and can communicate with different I2C devices with different formats based on an I2C bus.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:

FIG. 1 is a schematic diagram of a bus bridge from an AHB bus to an I2C bus according to the present invention;

FIG. 2 is a schematic diagram of the connection of an AHB slave module of the present invention;

FIG. 3 is a schematic structural diagram of a data cache module according to the present invention;

FIG. 4 is a flow chart of the operation of the security configuration module of the present invention;

FIG. 5 is a flow chart of counter counting according to the present invention;

FIG. 6 is a comparison flow chart of the comparator according to the present invention;

FIG. 7 is a block diagram of the host module I2C according to the present invention;

FIG. 8 is a timing diagram illustrating I2C read/write transmission according to the present invention;

FIG. 9 is a flow chart of the operation of the bus bridge of the present invention;

FIG. 10 is a flow chart of the AHB host reading WRITE/writing READ from the I2C slave internal register according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

As shown in fig. 1 to 8, the present invention provides a bus bridge from an AHB bus to an I2C bus, through which the AHB bus protocol is mapped into an I2C bus protocol; the bus bridge is used as a master of an I2C bus and is also used as a slave of an AHB advanced system bus; the transmission command from the AHB host is received through the AHB bus, the transmission command is analyzed and converted into the transmission command conforming to the I2C protocol, and the I2C transmission command is sent out through the I2C bus to be communicated with the I2C slave. For a write transfer command, the bus bridge sends data to the corresponding I2C slave via the I2C bus after receiving the target address, transfer data, and necessary control information from the AHB master. For the read transmission instruction, the bus bridge reads and buffers data from the corresponding I2C slave through the I2C bus after receiving the target address and necessary control information from the AHB host, and notifies the AHB host to read the buffered read data after completing the I2C transmission.

The bus bridge also has a safety configuration function, and can perform safety protection on important data (core codes/important parameters/data for marking user identities) in the storage unit of a specific slave.

Meanwhile, in order to correspond to different types of I2C slave devices, the configurable data transmission formats (I2C slave internal register addresses and continuous transmission sizes with different sizes) are added, and the system communication based on the I2C bus with different formats is compatible.

As shown in fig. 1, the bus bridge has the following structure: the bus bridge comprises an AHB slave module, a register module, a data cache module, a safety configuration module, a transmission control module, an I2C host module, an abnormity detection module and an interrupt control module.

the security configuration module is used for identifying the transmission of specific addresses in the specific I2C slave machines or I2C slave machines and informing the transmission control module to realize the security protection of transmission data (core codes/important parameters/data marking user identities).

The transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and realizing the trigger mark judgment function of the transmission instruction; and address forwarding from the register module to the I2C host module, write data forwarding from the data cache module to the I2C host module, and read data forwarding from the I2C host module to the data cache module; and implementing a state feedback function to the register module; and to implement address width configuration functions from the register module to the I2C host module; specifically, the method comprises the following steps:

the transmission control module is used for extracting the transmission instruction stored by the register module, analyzing the transmission instruction and sending the triggering marks of the I2C starting condition, the repeated starting condition and the ending condition to the I2C host module; according to a data forwarding request sent by the I2C host module, taking out a slave address required by I2C transmission, an I2C slave internal register address and the like from the register module and writing data from the data cache module during write transmission, sending the writing data to the I2C host module for processing through a writing data channel, caching read transmission data received by a reading data channel to the data cache module during reading data, and sending a transmission completion state to the interrupt control module for processing after transmission is completed; and receiving a transmission enable signal (high: transmission permission, low: transmission prohibition) from the security configuration module, and if the transmission permission is indicated, making the I2C host module enter an operating state; if the transmission inhibition is indicated, the I2C host module is not allowed to enter the working state, and the current AHB to I2C protocol conversion is directly ended. And sending the transmission completion state to an interrupt control module for processing.

The I2C host module is used for controlling the SCL line/SDA line to generate I2C transmission according to the transmission instruction transmitted from the transmission control module. Specifically, the method comprises the following steps:

the I2C host module is used for controlling SCL/SDA line to generate I2C transmission according to the I2C start condition, repeat start condition, trigger flag of end condition, slave address, I2C slave internal register address or data and other information from the transmission control module. Read data is driven to the read data channel during an I2C read transfer. The status of the transmission (busy/idle) is returned to the register module and the anomaly detection module. And returning the starting condition, the repeated starting condition, the stopping condition and the ACK/NACK to the abnormity detection module.

and the interrupt control module is used for controlling the generation of interrupt signals according to the transmission completion state and the transmission prohibition state of the transmission control module and the detection result of the abnormality detection module.

The working principle of each module in the bus bridge is as follows:

1. AHB slave module

The AHB slave module is used as an interface of the AHB bus, receives address and data information and the like from the AHB bus, can transmit information with the register module, drives a read-write control signal of a corresponding register, and realizes the read-write operation of the register. Or the data can be stored into the data buffer module during write transmission, and the read data can be read out from the data buffer module when read transmission is completed. As shown in fig. 2, fig. 2 is a schematic connection diagram of the AHB slave module.

2. Register module

The partial registers included in the register module are listed in table 1 below.

TABLE 1 register List

Name of register	Bit width	Description of the invention
			CR0	7	I2C slave address setting
CR1	3	I2C Slave internal register Address Width (3 'b 000 ~ 2' b 111: 0 bytes ~ 7 bytes)
			CR2	8	Setting of continuous transmission size (8 'h 00 ~ 8' hff:0 bytes ~ 255 bytes)
CR3	1	Transmission direction setting (1 'b 0: write transmission; 1' b1: read transmission)
			CR4	32	I2C Slave internal register Address
CR5	3	Interrupt zero clearing
			CR6	3	Interrupt masking
CR7	1	AHB setup completion register (AHB host sending instruction and data finish)
			DR0	n	Timeout compare register (threshold setting)
SR0 (read only)	1	The status of the I2C bus (high: busy;low: idle)
			SR1 (read only)	1	Abnormal state of transmission (high: ERROR; low: OK)
SR2 (read only)	1	Transmission complete status (high: complete; low: incomplete)
			SR3 (read only)	2	Exception flag register (indicating which exception occurred)

3. Data caching module

As shown in fig. 3, fig. 3 is a schematic structural diagram of a data cache module; the data cache module comprises a control unit and a data storage unit;

the data storage unit is composed of a readable and writable register unit and assembled into a storage unit of 8bit (width) multiplied by 255 (depth); storing write data from the AHB bus setting during write transmission and storing read data from the transmission control module during read transmission;

the main functions of the data caching module are as follows:

when the AHB host writes data to the I2C slave computer, the write data from the AHB host computer is stored into the data storage unit, and the data written by the AHB host computer is read out in sequence under the control of the transmission control module; when the AHB host reads data from the I2C slave, the data read back by the I2C host module is stored in the data storage unit; after the logging is completed, the AHB master reads data from the I2C slave to the AHB bus from the data cache module.

4. Security configuration module

The bus bridge has a safety configuration function, and can perform safety protection on important data (core codes/important parameters/data for marking user identities) in the storage unit of a specific slave in consideration of the safety requirement in SoC design. The invention therefore envisages a secure configuration module.

The safety protection mechanism of the safety configuration module comprises a global protection unit and a local protection unit;

the local protection unit is used for protecting some specific storage units in the I2C slave, and I2C slave addresses needing protection and corresponding register addresses are prestored in the local protection unit.

In order to secure the data (core code/important parameters/data marking the identity of the user). It is emphasized here that, unlike data masking (DQM) techniques, data masking: on a read, the masked data is still transferred out of the memory bank, just masked at the control I/O port. The safety configuration module saves part of time and reduces the power consumption.

The security configuration module transmits a transmission permission state/a transmission prohibition state to the transmission control module through transmission enable signals (1: transmission permission and 0: transmission prohibition); as shown in fig. 4, the specific determination method of transmission permission and transmission prohibition is as follows:

acquiring the I2C slave machine address and the register address of the transmission object from the register module;

firstly, the permission judgment of the global protection unit is carried out, namely the address of the I2C slave machine of the transmission object obtained from the register module is compared with the address of the slave machine prestored in the global protection unit to judge whether the addresses are consistent; if the two are consistent, transmission is prohibited; if the addresses are inconsistent, entering permission judgment of the local protection unit, namely comparing the address of the I2C slave machine of the transmission object obtained from the register module with the address of the slave machine prestored in the local protection unit, and judging whether the addresses are consistent; if not, transmitting the permission; if the register addresses are consistent, whether the register addresses of the transmission objects acquired from the register module are in the protection range is continuously judged, namely the register addresses are compared with the corresponding register addresses prestored in the local protection unit, and whether the register addresses are consistent is judged; if so, transmission is prohibited, otherwise transmission is permitted.

5. Anomaly detection module

The anomaly detection module may correspond to anomalies including:

I2C is abnormal in Timeout of the slave which is not responding for a long time, and this abnormality may cause the I2C host module to not get a response for a long time after initiating transmission.

Access exception of the I2C slave machine which does not exist is caused by the exception, and the exception can cause that the response cannot be obtained after the I2C host machine initiates the slave address.

Aiming at the abnormity of the first point, the invention provides a specific implementation scheme as follows:

in the abnormality detection module, a Timer counter is designed. The counting process is shown in fig. 5.

The counter counts when the I2C host is performing I2C transfers, and stops counting when the I2C host is not performing I2C transfers.

In order to obtain whether the I2C host is performing I2C transmission, it is necessary that the I2C host module transmits a flag signal indicating whether the I2C is transmitting, such as busy signal.

The timing counter initiates at I2C transmission: and starting conditions, repeating the starting conditions, responding to the pulse, and resetting when the conditions are stopped.

And a Timeout compare register is designed in the register module, and the Timeout compare register can be configured through the AHB host. The compare register workflow is shown in figure 6.

Comparing the sizes of the timing counter and the Timeout comparison register, when the value of the timing counter is greater than that of the Timeout comparison register, indicating that I2C has not obtained response for a long time in the transmission process, and generating a Timeout flag signal.

Outputting the timeout flag signal to the transmission control module may enable the transmission control module to initiate a data transmission stop signal to stop the current transmission of I2C.

And transmitting the timeout flag signal to the interrupt control module, so that the AHB host can be informed that the current transmission is not completed.

For the second point of abnormality, a specific embodiment provided by the present invention is as follows:

in the abnormal detection module, after the host module initiates an I2C transmission start/restart signal according to I2C, whether the address response bit has a slave response (during the 9 th SCL is pulled up) is detected, and if no slave response exists, an access abnormal flag signal is generated.

And feeding back the access abnormal mark signal to the transmission control module, so that the transmission control module initiates a stop signal to stop the current transmission.

And transmitting the access exception flag signal to the interrupt control module, so that the AHB host can be informed that the current transmission is not completed. For the exception, an exception flag register can be designed in the register module to indicate whether the exception occurs or not and what kind of exception occurs.

6. Interrupt control module

For the interrupt control module, a specific embodiment provided by the present invention is as follows:

and summarizing the abnormal mark signal input by the abnormal detection module and the transmission completion signal input by the transmission control module to generate a uniform interrupt signal and output the uniform interrupt signal to the AHB host.

And an interrupt clear register is designed in the register module and is used for clearing the interrupt signal. An interrupt mask register is designed for masking interrupt signals.

The clearing of the interrupt signal is controlled in the interrupt control module according to the value of the interrupt clear register. For example, the AHB host may configure the register for clearing interrupts after the interrupt has been received.

The interrupt signal is masked in the interrupt control module according to the value of the interrupt mask register. This register may be configured to mask interrupts, for example, when interrupts are not desired to be used in the system.

7. I2C host module

As shown in fig. 7, the I2C host module includes an SCL generation logic, an SDA generation logic, and a state machine;

As shown in fig. 8, fig. 8 is a timing diagram of a transmission mode (WRITE) and a reception mode (READ) when the bus bridge is used as a host, and it can be seen that the data connection is performed by a data forwarding request. And controlling the SCL/SDA to generate a starting condition and a stopping condition according to the data transmission starting signal and the data transmission ending signal sent by the transmission control module. And giving a data forwarding request in a response pulse period (ACK/NACK), sending the data forwarding request to a transmission control module, and requesting to prepare for data forwarding. And after the data forwarding request is sent, sending the data out through the SDA according to the data driven to the data writing channel by the transmission control module. During a read transfer, the I2C host module generates a response or no response during the response pulse based on the value of the write data channel. When the value of the write data channel is 0, it indicates that the next data byte needs to be received, and an ACK (response) is generated; when the value of the write data channel is 1, it indicates that all data bytes have been received, and a NACK (no response) is generated to notify the slave transmitter of the end of data. The transmission status of the I2C bus is confirmed according to the start condition and the stop condition, and the transmission status is sent to the register module and the abnormality detection module.

8. Transmission control module

The transmission control module has the following main functions:

(1) trigger mark judgment (transmission control module → I2C host module)

A data transmission start signal and a data transmission end signal are given.

(2) Address forwarding (register module → transmission control module → I2C host module)

The I2C host module sends out data transfer request, according to the data request, the I2C slave address and I2C slave internal register address are taken out from the register and sent to the I2C host module through [ write data channel ]

(3) Write data forwarding (data buffer module → transmission control module → I2C host module)

The I2C host module sends out a data forwarding request, takes out the write data from the data cache module according to the data forwarding request, and sends the write data to the I2C host module through a [ write data channel ].

(4) Read data forwarding (I2C host module → transmission control module → data buffer module)

The I2C host module sends out a data forwarding request, obtains read data from the data reading channel according to the data forwarding request, and stores the read data in the data cache module.

(5) State feedback (Transmission control Module → register Module)

When the read data is completely cached in the data cache module, the state is fed back to the state register of the register module and is sent to the interrupt control module as information, which marks that the AHB host can start to acquire the read data from the data cache module.

(6) Exception mapping (Exception detection Module → Transmission control Module → I2C host Module)

When receiving the abnormal flag signal of the abnormal detection module, the data transmission end signal is enabled directly, so that the I2C host module generates an I2C stop condition, and stops the current transmission.

(7) Security protection process (anomaly detection module → transmission control module → I2C host module)

Receiving a transmission enable signal of the security configuration module (generation of the signal is described with reference to fig. 4), and when the enable signal is high (transmission permission), performing AHB to I2C protocol conversion normally; when the enable signal is low (transmission disabled), the data transmission start signal is not enabled, the I2C host module is not enabled, the I2C bus status register is kept in an idle state, the current AHB to I2C protocol conversion is directly ended, and the transmission completion status is input to the interrupt control module for processing. The AHB host is notified that the transfer is complete and if it is a read transfer, the read data returns a value of zero.

(8) I2C function for configuring address width of slave internal register (register module → transmission control module → I2C host module)

The function is a main design point of the transmission control module, which is to be capable of corresponding to different types of I2C slave devices, add configurability of data transmission formats (I2C slave internal register addresses and continuous transmission sizes with different sizes), and be compatible with system communication with different formats based on an I2C bus. The transmission control module realizes the address width configuration function from the register module to the I2C host module, so that the bus bridge supports the setting of the address width in the range of 1-7 bytes, the bus bridge is suitable for different types of I2C slaves, and the data transmission format is configurable.

The address width of I2C from the internal registers varies depending on the device type. For example, the internal address width of the EEPROM memory (AT24C04) is one byte, and the internal address width of the EEPROM memory (AT24C64) is two bytes. Specifically, the number of bytes is related to the number of memory cells of the device, and the address field may be one byte, two bytes long, etc. In view of the above, the bus bridge of the present invention supports setting of address width (range of 1-7 bytes) to accommodate different I2C slaves. The CR1 register of the register module is responsible for coordinating address width for I2C transfers. Aiming at different I2C slaves, the AHB host configures parameters of a CR1 register, and a transmission control module acquires an I2C slave internal register address corresponding to 1-7 bytes in width from a CR4 register according to the value of a CR1 register (3 bit).

The transmission control module realizes the address width configuration function from the register module to the I2C host module, and comprises the following steps:

waiting for a data forwarding request of the I2C host module;

taking out the value representing the address width from the CR1 register, comparing the value with the value of the register address written byte counter, if the value is consistent, representing that the register address is sent completely and judging the transmission direction according to the value of the CR3 register; otherwise, the data forwarding request of the host module of the I2C is waited, and the rest I2C slave internal register addresses are sent continuously.

(9) Transfer size configuration (register Module → transfer control Module → I2C host Module)

In order to improve the transmission efficiency, for the continuous address access of the AHB host to the I2C slave, the bus bridge supports the setting of single I2C transmission data size (1-255 bytes) so as to adapt to more application scenes. The CR2 register of the register module is responsible for coordinating the data size of I2C transfers. The AHB host configures parameters of a CR2 register, and the transmission control module continuously writes write data into an internal register of an I2C slave machine according to the value of a register CR2(8bit) if the write transmission is performed, and continuously receives read data from an I2C slave machine if the read transmission is performed, wherein the transmitted data is equal to the size set by a CR2 register, and the I2C read-write transmission is ended. The write transfer refers to control flow steps 9-13 of embodiment 3 and the read transfer refers to control flow steps 17-21 of embodiment 3.

With more and more IP integrated into SoC designs, a separate AHB bus has not been able to meet the communication requirements. Based on the SoC chip needing various multiplex IPs, the transmission communication of the cross-bus protocol is processed through the bus bridge; the transition from the fast transmission rate of the AHB to the low transmission rate of I2C is achieved.

1. The AHB continuous transmission can be buffered, and continuous read transmission or continuous write transmission of 255Byte data is supported to the maximum extent;

2. the requirement of subsequent time sequence transmission is reduced, frequent bus operation is avoided, and the burden of an AHB host is reduced;

3. the AHB host does not occupy a bus for a long time to wait for the feedback of the I2C slave machines, so that the working efficiency of the AHB host is improved;

4. the system has a safety configuration function, can protect core data and improve the safety among systems;

5. the I2C slave internal register address width configuration and the continuous transmission size configuration are realized, namely the I2C transmission format is configurable, high compatibility is achieved, and communication can be carried out with different I2C devices with different formats based on an I2C bus.

Example 2

As shown in fig. 1 to 8, the present embodiment is different from embodiment 1 in that the present embodiment provides a bus bridge system from an AHB bus to an I2C bus, where the bus bridge system includes an AHB master, an AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, the AHB master is communicatively connected to the bus bridge through the AHB bus, and the bus bridge is communicatively connected to the plurality of I2C slaves through the I2C bus;

the bus bridge adopts a bus bridge from AHB bus to I2C bus described in embodiment 1.

Example 3

As shown in fig. 9 and 10, the present embodiment is different from embodiment 1 in that the present embodiment provides a method for controlling a bus bridge from an AHB bus to an I2C bus, and the method is applied to a bus bridge from an AHB bus to an I2C bus described in embodiment 1, and the method includes:

step D, judging whether the register address is sent completely, if the register address is sent completely, judging the transmission direction according to the value of the CR3 register, and if the register address is write-transmission, entering the step E; if the data is not the write transmission, executing a data read forwarding request; if the register address is not sent completely, waiting for a data forwarding request of the I2C host module, and continuously sending the residual I2C slave computer internal register addresses; the judgment basis for whether the register address is sent is as follows: taking out the value representing the address width from the CR1 register, comparing the value with the value of the register address written byte counter, and if the values are consistent, representing that the register address is sent out completely; otherwise, the register address is not sent to be completed;

step E, waiting for a data forwarding request of the I2C host module, if the data forwarding request exists, taking out data of one byte from the data cache module, sending the data to the I2C host module through a data writing channel, and adding 1 to a written data byte counter; if the data forwarding request does not exist, the data forwarding request of the I2C host module is waited for all the time;

step F, judging whether the data is sent or not, and if the data is sent, waiting for a data forwarding request of the I2C host module; if the data is not sent completely, waiting for the data forwarding request of the I2C host module to continue sending the rest write data; the judgment basis for finishing the data transmission is as follows: obtaining a value representing the transmission size from a CR2 register, comparing the value with the value of a written byte counter of the write data, and if the values are consistent, representing that the data transmission is finished; otherwise, the data is not sent completely;

and G, enabling a data transmission end signal, and ending.

Specifically, the executing data read forwarding request specifically includes:

step J, if a data forwarding request exists, acquiring a value representing transmission size from a CR2 register, comparing the value with a value of a read data receiving byte counter, judging whether the values are consistent, if so, driving a write data channel to be 1, informing the I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to be 0, and informing the I2C host to generate ACK in the next response pulse period; if the data forwarding request does not exist, the data forwarding request of the I2C host module is always waited;

In specific implementation, according to the READ/WRITE process of the AHB host to the I2C slave internal register, the bus bridge executes the following control process, as shown in fig. 9, where fig. 9 is a flowchart of the bus bridge. The specific control flow comprises the following steps:

1. starting;

2. waiting for the AHB host to be set;

3. enabling a data transmission starting signal;

4. taking out the slave address from the CR0 register, splicing the tail of the slave address with the transmission direction (W) to form data of one byte, and sending the data to the I2C host module through a data writing channel;

5. waiting for a data forwarding request of the I2C host module;

6. the I2C register address in the slave is taken out from the CR4 register and is sent to the I2C host module through a write data channel, and the written byte counter of the register address is increased by 1;

7. taking out the value representing the address width from the CR1 register, comparing the value with the value of the written byte counter of the register address, if the value is consistent, representing that the transmission of the register address is completed and entering a step 8, otherwise entering a step 5 to continue transmitting the residual I2C slave internal register addresses;

8. judging the transmission direction according to the value of the CR3 register, if the transmission is write transmission, entering the step 9, otherwise, entering the step 15;

9. waiting for a data forwarding request of the I2C host module;

10. taking out data of one byte from the data cache module, sending the data to the I2C host module through a write data channel, and adding 1 to a write data written byte counter;

11. acquiring a value representing the transmission size from a CR2 register, comparing the value with the value of a written byte counter of the write data, if the value is consistent, representing whether the data transmission is finished or not and entering a step 12, otherwise entering a step 9 to continue sending the rest of the write data;

12. waiting for a data forwarding request of the I2C host module;

13. enabling a data transmission end signal;

14. ending;

15. enabling a data transmission starting signal;

16. taking out the slave address from the CR0 register, splicing the tail end and uploading the transmission direction (R) to form data of one byte, and sending the data to the I2C host module through a data writing channel;

17. waiting for a data forwarding request of the I2C host module, and initializing a read data receiving byte counter to be 1;

18. obtaining the value representing the transmission size from the CR2 register, comparing the value with the value of the read data receiving byte counter, judging whether the values are consistent, if so, driving the write data channel to 1, informing the I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to 0, informing the I2C host to generate ACK in the next response pulse period

19. Waiting for a data forwarding request of the I2C host module;

20. receiving read data from a read data channel, storing the read data in a data cache module, and adding 1 to a read data receiving byte counter;

21. a value representing the size of the transfer is obtained from the CR2 register and compared to the value of the read data receive byte counter, indicating that the read data transfer is complete if the value of the counter minus 1 equals the value of the CR2 register, and step 13 is entered otherwise.

As shown in fig. 10, fig. 10 is a flow chart of the AHB master reading WRITE/writing READ from the I2C slave internal register.

A basic transfer message from the AHB host includes the following:

1) I2C slave address

2) Subaddress (index) pointing to internal register of slave

3) Transmission direction (read/write)

4) Sub-address (index) bit width of a slave internal register

Aiming at the problem that the sub-address bit widths of the internal registers of the slave machines are different, the bus bridge supports the setting with the width ranging from 1 byte to 7byte, so that the AHB host needs to include information indicating the sub-address (index) bit width of the internal registers of the slave machines when the AHB host sends transmission control information.

5) Transfer size

Aiming at the condition that the data bytes accessed continuously are different, the bus bridge supports the setting of the continuous transmission data size (1-255 bytes), so that the AHB host needs to include information representing the transmission size when transmitting the transmission control information.

6) Writing data

Case 1: [ AHB Master WRITE WRITE to I2C Slave internal register ]

1. Starting;

the AHB host confirms that the bus bridge is idle;

3. set the slave address to the CR0 register;

4. set the transfer direction to the CR3 register;

5. setting the slave internal register address width to the CR1 register;

6. setting the internal register address of the slave of the transmitted I2C to the CR4 register;

7. set the transfer data size to the CR2 register;

8. setting the write data to be transmitted to a data caching module;

9. setting a CR7 register, and informing the bus bridge AHB host that the setting is finished;

10. and (6) ending.

Case 2: [ AHB Master READ of I2C Slave internal register ]

1. Starting;

the AHB host confirms that the bus bridge is idle;

3. set the slave address to the CR0 register;

4. set the transfer direction to the CR3 register;

5. setting the slave internal register address width to the CR1 register;

6. setting the internal register address of the transmitted I2C slave to the CR4 register;

7. set the transfer data size to the CR2 register;

8. setting a CR7 register, and informing the bus bridge AHB host that the setting is finished;

9. generating an interrupt, confirming that the transmission of the SR2 register is completed, if the transmission is completed, entering the step 10, and otherwise, performing exception handling;

10. reading data from the data cache module;

11. and (6) ending.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A bus bridge from an AHB bus to an I2C bus is characterized in that the bus bridge comprises an AHB slave module, a register module, a data cache module, a transmission control module and an I2C host module; mapping the AHB bus protocol into an I2C bus protocol through a bus bridge;

the AHB slave module is used for receiving an access request of the AHB host, realizing read-write access to the register module through an AHB bus and realizing the data information exchange function of the register module and the AHB bus;

the register module is used for storing a transmission instruction from an AHB bus to an I2C bus;

the transmission control module is used for realizing the function of judging the trigger mark of the transmission instruction; and address forwarding from the register module to the I2C host module, write data forwarding from the data cache module to the I2C host module, and read data forwarding from the I2C host module to the data cache module; and implementing a state feedback function to the register module; and to implement address width configuration functions from the register module to the I2C host module;

an I2C host module for controlling the SCL line/SDA line to generate I2C transmission according to the information transmitted from the transmission control module.

2. The bus bridge from AHB bus to I2C bus of claim 1, wherein said transfer control module, for implementing address forwarding function from register module to I2C host module, comprises:

3. The bus bridge from AHB bus to I2C bus as claimed in claim 1 or 2, wherein said transmission control module implements address width configuration function from register module to I2C host module, making said bus bridge support setting of address width range from 1-7 bytes for adapting to different types of I2C slave machines, and data transmission format is configurable; the transmission control module realizes the address width configuration function from the register module to the I2C host module, and comprises the following steps:

waiting for a data forwarding request of the I2C host module;

4. The AHB to I2C bus bridge of claim 1, further comprising a security configuration module;

the safety configuration module is used for identifying the transmission of the set address in the I2C slave machine or the I2C slave machine and informing the transmission control module to realize the safety protection of the transmission data.

5. The AHB to I2C bus bridge of claim 4, wherein said security configuration module comprises a global protection unit and a local protection unit;

6. The AHB to I2C bus bridge of claim 5, wherein said security configuration module is further configured to send a transmit enabled/disable status to said transmit control module via a transmit enable signal, said transmit enable signal comprising a transmit enable and a transmit disable; the specific determination method of transmission permission and transmission prohibition is as follows:

7. The AHB to I2C bus bridge of claim 1, further comprising an anomaly detection module, an interrupt control module;

8. The AHB to I2C bus bridge of claim 7, wherein said I2C host module comprises SCL generation logic, SDA generation logic, and a state machine;

9. The AHB to I2C bus bridge of claim 1, wherein said data cache module comprises a control unit and a data storage unit;

the data storage unit is composed of a readable and writable register unit and assembled into a storage unit of 8bit multiplied by 255; storing write data from the AHB bus setting during write transmission and storing read data from the transmission control module during read transmission;

when the AHB host writes data to the I2C slave, the write data from the AHB host is stored in the data storage unit, and the data written by the AHB host is read out in sequence under the control of the transmission control module; when the AHB host reads data from the I2C slave, the data read back by the I2C host module is stored in the data storage unit; after the logging is completed, the AHB master reads data from the I2C slave to the AHB bus from the data cache module.

10. A bus bridge system from an AHB bus to an I2C bus is characterized by comprising an AHB host, the AHB bus, a bus bridge, an I2C bus and a plurality of I2C slaves, wherein the AHB host is in communication connection with the bus bridge through the AHB bus, and the bus bridge is in communication connection with the I2C slaves through the I2C bus;

wherein the bus bridge is an AHB to I2C bus as claimed in any one of claims 1 to 9.

11. A bus bridge control method of an AHB bus to an I2C bus, which is applied to the bus bridge of the AHB bus to the I2C bus as claimed in any one of claims 1 to 9, the control method comprising:

step B, enabling a data transmission starting signal, taking out a slave address from the CR0 register, splicing the tail of the slave address in the transmission direction W to form data of one byte, and sending the data to the I2C host module through a data writing channel;

step D, judging whether the register address is sent completely, if the register address is sent completely, judging the transmission direction according to the value of the CR3 register, and if the register address is write-transmission, entering the step E; if the data is not the write transmission, executing a data read forwarding request; if the register address is not sent completely, waiting for a data forwarding request of the I2C host module, and continuously sending the residual I2C slave computer internal register addresses;

step F, judging whether the data is sent or not, and if the data is sent, waiting for a data forwarding request of the I2C host module; if the data is not sent completely, waiting for the data forwarding request of the I2C host module to continue sending the rest write data;

and G, enabling a data transmission end signal, and ending.

12. The method as claimed in claim 11, wherein said performing a data read forward request comprises:

step H, enabling a data transmission starting signal, taking out a slave address from the CR0 register, splicing the tail of the slave address in a transmission direction R to form data of one byte, and sending the data to the I2C host module through a data writing channel;

step J, obtaining a value representing the transmission size from a CR2 register, comparing the value with the value of a read data receiving byte counter, judging whether the values are consistent, if so, driving a write data channel to be 1, informing the I2C host to generate NACK in the next response pulse period, otherwise, driving the write data channel to be 0, and informing the I2C host to generate ACK in the next response pulse period;

13. The method as claimed in claim 11, wherein the determination of whether the register address is sent in step D is based on: taking out the value representing the address width from the CR1 register, comparing the value with the value of the register address written byte counter, and if the values are consistent, representing that the register address is sent out completely; otherwise, the register address is not sent to be completed;