KR20070070680A - Device and system for debugging device using control bus - Google Patents

Abstract

A device and a system for debugging a slave are provided to debug an error of I2C(Inter IC) device even if the I2C device including an I2C bus includes no UART, and debug the I2C device and a baseband part at the same time even if a host computer performing debugging includes only one UART port. The host computer(260) generates control signals and debugs the slave. A master(230) is connected to the host computer through the UART and is connected to the slave through the I2C bus. The slave(200) performs the control signal received from the host computer through the master and transmits a performance result to the host computer through the master. The host computer debugs the slave by using the performance result. The control signal received from the host computer includes a flag transmitting the control signal to the slave from the master.

Description

Device and system for debugging device using control bus

1 is a diagram illustrating a configuration of a debugging system connected to a device including a conventional I2C bus.

2 is a diagram illustrating a configuration of a debugging system connected to a device including an I2C bus according to a preferred embodiment of the present invention.

3 is a diagram illustrating the configuration of an I2C slave register map of a device including an I2C bus in accordance with one preferred embodiment of the present invention.

The present invention relates to a method for debugging a slave. More particularly, the present invention relates to a method for debugging a normal operation or an error even when a device using a control bus does not include a UART. will be.

The control bus refers to a bus for transmitting and receiving a control signal (eg, a command, etc.), and the control bus may be, for example, an I2C bus or a similar bus. The following description is based on the most common I2C bus among control buses.

The I2C bus, also called Inter-IC, is a two-wire, bidirectional serial bus that provides a communication link between integrated circuits. Commonly referred to as I2C, it is now widely used as a de facto standard for implementing an embedded system that includes the internal computing capabilities of digital devices.

In the present specification, a slave is a slave module connected to a master through a control bus and controlled by a control signal received through the control bus, and particularly, a device included in a digital device to communicate with other components. It may also be called a slave, but other control buses other than the I2C bus may be used, and may be implemented as chips, preferably not in the form of devices or devices.

The slave is also called an I2C device when communicating using the I2C bus.

The master is the central part of the digital processing device, usually referred to as baseband, and can be implemented in particular as a device or chip connected to the slave via a control bus. In the following description, a description will be made using a generally referred to baseband name.

Debugging, particularly in the computer field, refers to the process of finding and fixing bugs in a computer program or hardware device, such as bugs, or avoiding errors.

In general, in order to eliminate a defect in a program or hardware device, it is necessary to isolate the problem and fix it. Most computer programs and programmed parts of hardware consist of a lot of code, so many products contain a certain amount of errors. The process of finding these faults is usually called debugging.

In particular, since firmware included in a digital device such as a computer is most necessary for the basic operation of the digital processing device, a debugging process for correcting a normal operation or an error must be performed.

Firmware refers to a program that is stored in memory and becomes part of a digital device permanently. If the hardware implements all the basic functions of the digital device, the structure is complicated and the cost increases.

UART is an abbreviation of Universal Asynchronous Receiver / Transmitter (hereinafter referred to as UART). It is a microchip or device that contains a program that controls an interface to a serial device attached to a computer.

The UART provides a computer with an RS-232C DTE interface, a data terminal device in the standard protocol for serial data communication, to communicate with or send data to a modem or other serial device.

The basic function of the UART is to convert the bytes received through the parallel circuit from the computer into a single serial bit stream for external transmission and, when transmitted internally, convert the serial bit stream into bytes for the computer to process. .

It also adds a parity bit for external transmission, checks the parity of received bytes, and removes the parity bit. When exporting data, add start and stop bits, remove them from incoming data, and handle interrupts from the keyboard or mouse.

It can also manage other types of interrupt processing and devices that require the computer's operating speed to be equal to the device's speed. Recently, the UART provides some amount of data buffering to ensure that the data streams of the computer and the serial devices are comparable. Match it.

A conventional method for performing debugging of a device (hereinafter, referred to as an I2C device) to communicate using the I2C bus will be described with reference to FIG. 1.

1 is a diagram illustrating a configuration of a debugging system for performing debugging on a firmware of a conventional I2C device.

As shown in FIG. 1, a system for debugging the firmware of an I2C device includes an I2C device 100, a baseband unit 140, and a host computer 160.

The I2C device 100 and the baseband unit 140 are connected to the host computer 160 by a UART cable, respectively, and the I2C device 100 and the baseband unit 160 are connected to each other via an I2C bus.

The I2C device 100 and the baseband unit 140 include a UART port therein and are connected by a UART cable, and the I2C device 100 and the baseband unit 140 are connected to the I2C slave 110 and the I2C master 145. Are connected to each other.

The contents of debugging performed by this method include information such as a command being performed by the I2C device 100 and a response to the execution.

The system for debugging the conventional I2C device 100 having such a configuration will be described based on the function of each component.

First, the conventional I2C device 100 includes an I2C slave register map 105, an I2C slave 110, a processor 115, a memory 120, a UART controller 125a, and a UART port 130a.

The I2C slave register map 105 is a buffer for communication between the I2C master 145 and the I2C slave 110. The I2C slave register map 105 is a space for storing contents to be delivered or intended to be transmitted from the I2C master 145.

When the I2C master 145 transmits a command to the I2C slave 110, the I2C master 145 transmits data to be delivered and address information to store the data. The transmitted address information and data are stored in the I2C slave register map 105.

Even when the I2C master 145 reads data from the I2C slave 110, the I2C slave 110 may pass address information on the I2C slave 110 to read data from the address information.

The I2C slave 110 uses the I2C bus as a path for communication with the baseband unit 140.

Accordingly, the I2C master 145 exists in the baseband unit 140 and the I2C slave 110 exists in the I2C device 100, so that the baseband unit 140 and the I2C device 100 are connected to each other.

The processor 115 is a logic circuit for processing and reacting basic instructions for the operation of the I2C device 100.

The memory 120 can be largely divided into two areas, an area where an instruction is executed and an area used while the instruction is executed. The memory of the area where the instruction is executed is mainly used in the form of flash, and the memory in the form of synchronous dynamic random access memory (SRAM) is also used. The memory area used when the command is executed mainly uses SRAM type memory.

The UART controller 125a is used for debugging in the development of a specific digital device, and obtains information about checking of environmental information of the I2C device 100 currently being performed and what functions are being performed.

It is mainly implemented in the form of a shell (DOS command prompt), and it is possible to input a command through a terminal program provided in the host computer 160 and to check the result of the executed command.

The UART port 130b is connected to an external device, in particular, a host computer 160 so that the information obtained by the UART controller 125a is output by being connected to the UART controller 125a.

Looking at the configuration of the baseband unit 140 connected to the I2C device 100, the baseband unit 140 is the I2C master 145, baseband processor 150, memory 155, UART controller 125b, UART port 130b.

The I2C master 145 is for other devices or components to communicate with the I2C device 100 and both read / write commands are made by the I2C master 145.

The baseband processor 150 is a logic circuit for processing and reacting basic instructions for the operation of the baseband unit 140.

The memory 155 may be roughly divided into two areas, which are commands that are executed in the baseband 140 and areas that are used while the commands are executed, and are areas in which these commands are stored.

The UART controller 125b and the UART port 130b are used for debugging during the development of digital devices, such as in the I2C device 100, and check the information of the environment and the functions of the currently running system. It is used to obtain the UART port 130b is connected to the UART controller 125b and is connected to an external device so that the information obtained from the UART controller 125b is output.

The host computer 160 is a computer for performing firmware development, download, and debugging.

In order to perform debugging for the development of the conventional digital device, the baseband unit 140 is connected to the host computer 160 through the UART port 130b of the baseband unit 140.

In addition, in the case of the I2C device 100, the I2C device 100 should be connected to the host computer 160 through the UART port 125a of the I2C device 100 to perform debugging of the I2C device 100.

Therefore, debugging in an I2C device must include a UART that includes a UART controller and a UART port.

There is a problem. Therefore, when the UART is not included in the I2C device, only the I2C device can not be debugged.

In addition, most of the computers produced recently have only one UART port. In this case, the host computer that performs debugging cannot debug the I2C device and the baseband at the same time.

In addition, since debugging of I2C device can be performed after the UART controller is initialized, there is a problem that cannot be debugged until the UART controller operates stably.

In order to solve the conventional problems as described above, the present invention proposes a debugging method that can correct the error of the I2C device even if the U2 is not included in the I2C device that is a device including the I2C bus.

In addition, even if the host computer performing debugging includes only one UART port, the present invention proposes a method for debugging the I2C device and the baseband unit together.

In addition, the present invention proposes a method for debugging the entire process of operating the I2C device by eliminating the need for including the UART in the I2C device.

Still other objects of the present invention will be readily understood through the following description of the embodiments.

In order to achieve the above object, according to an aspect of the present invention there is provided a method for debugging a slave.

According to a preferred embodiment of the present invention, in a method of debugging a slave communicating with a master and a control bus, the master transmits a control signal transmitted from a host computer connected by the master and a universal asynchronous transceiver (UART). Receiving an input through (a); Performing the received control signal (b); And (c) transmitting the execution result to the host computer through the master, wherein the host computer performs debugging to fix the bug by using the execution result. do.

According to another aspect of the present invention, there is provided a recording medium recording a program for implementing a method for debugging a slave.

According to a preferred embodiment of the present invention, a program of instructions that can be executed by a slave to perform a method of debugging a slave communicating with a master and a control bus is tangibly implemented and read by the slave. A recording medium recording a program, comprising: receiving a control signal transmitted from a host computer connected by the master and a universal asynchronous transceiver (UART) through the master (a); Performing the received control signal (b); And (c) transmitting the execution result to the host computer through the master, wherein the host computer uses the execution result to debug the slave to fix the bug. Is provided.

According to another aspect of the present invention, a debugging system of a slave is provided.

According to one preferred embodiment of the present invention, there is provided a debugging system of a slave, comprising: a host computer for generating control signals and performing debugging to fix a bug of the slave; A master coupled with the host computer to a general purpose asynchronous transceiver and coupled with the slave through a control bus; And a slave receiving the control signal transmitted from the host computer through the master, performing the received control signal, and transmitting the result of the execution to the host computer through the master, wherein the host computer performs the performing. A debugging system of a slave is provided, wherein the debugging is performed to correct a bug of the slave by using the result.

According to another aspect of the invention, there is provided a slave capable of debugging without including a general purpose asynchronous transceiver.

According to a preferred embodiment of the present invention, in a slave capable of debugging without including a general-purpose asynchronous transceiver, it is connected to a master transceiver of a master that receives a control signal from a host computer to receive the control signal from the master transceiver. A slave transceiver receiving unit; A processor unit which performs a process corresponding to the control signal received by the slave transceiver unit; And a register map in which a control signal received by the slave transceiver unit is stored and a result processed by the controller unit is stored.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

2 is a diagram illustrating a configuration of a debugging system connected to a device including an I2C bus according to an exemplary embodiment of the present invention. A system for debugging an I2C device according to the present invention will be described based on the difference from the system for debugging the conventional I2C device of FIG. 1.

As shown in FIG. 2, a debugging system connected to a device including an I2C bus according to an exemplary embodiment of the present invention includes an I2C device 200, a baseband unit 230, and a host computer 260. It may include.

The baseband unit 230 is connected to the host computer 260, and unlike the prior art, the I2C device 200 is connected only to the baseband unit 230.

The baseband unit 230 is connected to the host computer 260 through the UART port 255 provided therein, and the I2C device 200 and the baseband unit 230 are connected to the I2C slave 210 and the I2C master 235. Are connected to each other.

A system for debugging an I2C device according to an exemplary embodiment of the present invention having such a configuration will be described based on the function of each component.

First, the I2C device 200 may include an I2C slave register map 205, an I2C slave 210, a processor 215, and a memory 220. Unlike the related art, the UART controller and the UART port are not included.

The I2C slave register map 205 is a buffer for communication between the I2C master 235 and the I2C slave 210. The I2C slave register map 205 is a space for storing contents to be delivered or delivered from the I2C master 235.

When the I2C master 235 transmits a command to the I2C slave 210, the I2C master 210 transmits the data to be delivered together with the address information to store the data, and the address information and the data are stored in the I2C slave register map 205.

Even when the I2C master 235 reads data from the I2C slave 210, the I2C slave 210 may transmit address information for the I2C slave 210 to read data from the address information.

In addition, in the present invention, unlike the prior art, a debugging area is further included in the I2C slave register map 205.

The debugging area included in the I2C slave register map 205 receives the control signal through the baseband unit 230 without performing a direct connection with the host computer 260, performs an operation, and stores the result of the baseband unit 230. To send). The result of performing the control signal transmitted to the baseband unit 230 is transmitted to the host computer 260 and debugging is performed to check whether the I2C device 200 is error in the host computer 260. Detailed configuration and function of the I2C slave register map 205 to which such a configuration and function are added will be described in more detail with reference to FIG. 3.

The I2C slave 210 uses the I2C bus as a path for communication with the baseband unit 230, the I2C master 235 is present in the baseband unit 230, and the I2C slave 210 is present in the I2C device 200. The baseband unit 230 and the I2C device 200 are connected to each other.

The processor 215 is a logic circuit for processing and reacting basic instructions for the operation of the I2C device 200.

The memory 220 may be largely divided into two areas, an area where an instruction is executed and an area used while the instruction is executed.

The memory of the area where the instruction is executed is mainly used in the form of flash, and the memory in the form of synchronous dynamic random access memory (SRAM) is also used. The memory area used when the command is executed mainly uses SRAM type memory.

Looking at the configuration of the baseband unit 230 connected to the I2C device 200, the baseband unit 230 is an I2C master (235), a baseband processor (240), a memory (memory) 245, a UART controller 250, and a UART port 255.

The I2C master 235 is for communication with the I2C device 200, and a read / write command is made by the I2C master 235.

The baseband processor 240 is a logic circuit for processing and reacting basic instructions for the operation of the baseband unit 230.

The memory 245 may be broadly divided into two areas, which are commands that are executed by the baseband unit 230 and areas that are used while the commands are executed, and are areas in which these commands are stored.

The UART controller 250 and the UART port 255 are used for debugging the I2C device 200 included in a specific digital device during the development of a specific digital device, and check the environmental information of the system currently being performed and perform certain functions. The UART port 255 is connected to the UART controller 250 and is connected to an external device so that the information obtained from the UART controller 250 is output.

The host computer 260 is a computer for performing firmware development, download, and debugging.

Referring to FIG. 3, a configuration of an I2C slave register map that enables debugging without an I2C device including a UART in a debugging system connected to a device including an I2C bus according to an embodiment of the present invention having such a configuration is shown in FIG. 3. Take a look.

3 is a diagram illustrating the configuration of an I2C slave register map 205 of a device including an I2C bus according to a preferred embodiment of the present invention.

As shown in FIG. 3, the I2C slave register map 205 of the device including the I2C bus according to the preferred embodiment of the present invention has a debugging area in which received instructions are stored and a result of performing the instructions is stored. area 300 may be further included.

The debugging area 300 may be divided into a Rx debugging area 310 in which received commands are stored and a Tx debugging area 320 in which a result of executing the commands is stored.

The reception debugging area 310 is an area in which instructions are stored when a command input through the host computer 260 is transmitted to the I2C device 200 through the I2C bus through the baseband 230.

The transmission debugging area 320 is an area where the results of the command performed by the I2C device 200 are stored by the received commands.

The debugging area 300 of the I2C slave register map 205 enables the reception of the command and the transmission of the result of the command without directly connecting the I2C device 200 with the host computer 260. Therefore, by including the debugging area 300 in the I2C slave register map 205, the I2C device 200 can be debugged without directly connecting the I2C device 200 with the host computer 260.

Since the I2C device 200 and the baseband unit 230 are connected through the I2C bus, the I2C device 200 and the baseband unit 230 may receive commands through the baseband unit 230 and transmit the results to the host computer 260 through the baseband unit 230. .

Instructions transmitted in this process and a result of the execution of the instructions are stored in the debugging area 300 included in the I2C slave register map 205.

By referring to the debugging system and the configuration of the I2C slave register map 205 of the I2C device 200 by inputting the command for performing debugging in the terminal program of the host computer 260 to operate in the I2C device 200. Look at the order of the steps.

First, when a command is input from the host computer 260, a UART port 255 of the baseband unit 230 connected to the baseband unit 230 through a UART port (not shown) and a UART cable (not shown) of the host computer 260. Send commands)

Commands received through the UART port 255 of the baseband unit 230 are transmitted to the UART controller 250 via the UART port 255.

Instructions include flags, which are predefined bits that are used to leave signals promised to other programs.

The transmitted command first operates a shell program connected to the UART controller 250 of the baseband unit 230. As the shell program operates, the shell program transmits an instruction to the reception debugging area 310 of the debugging area 300 included in the I2C slave register map 205 through the I2C master 235.

The I2C device 200 that receives the command in the reception debugging area 310 operates an I2C slave interrupt processing routine.

The I2C slave interrupt processing routine operates the shell program of the I2C device 200 and the shell program of the I2C device 200 executes the command received from the baseband unit 230 to operate the I2C device 200.

The order in which the output information by the command execution of the I2C device 200 operated by performing such a process is transmitted to the host computer 260 will be described.

First, the baseband unit 230 uses the I2C master 235 to debug whether there is content to be output in a polling manner in the transmission debugging area 320 included in the I2C slave register map 205.

Polling is a transmission control method that continuously debugs what other programs or devices are in the device.

 If there is content to be output, information of the content to be transmitted is transmitted to a UART driver (not shown), and the UART driver outputs the output information through the UART controller 250. The output information is transferred to the host computer 260 through the URAT port 255 and output on the terminal program of the host computer 260.

Through the delivery of these commands and the output of the execution results of the commands, debugging is performed to correct the errors of the I2C device by inputting a command to correct the I2C device and if there is an error in the host computer.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the method of debugging a device including an I2C bus according to the present invention and a recording medium recording a program for implementing the same, the device including the I2C bus does not include a UART controller and a UART port. This also has the advantage of being able to debug to correct errors on devices containing the I2C bus.

In addition, even if the host computer for debugging includes only one UART, the I2C device and the baseband unit can be debugged together.

And since the UART controller and the UART port do not need to be included in the I2C device, it is possible to debug the entire process of operating the I2C device.

In addition, when implementing the I2C device as a chip, separate Rx / Tx pins can be removed to perform debugging, thereby reducing the number of pins or using the two pins for other purposes.

Claims (18)

In a method of debugging a slave communicating with a master and a control bus, (A) receiving a control signal transmitted from a host computer connected to the master by a universal asynchronous transceiver (UART) through the master; Performing the received control signal (b); And And transmitting (c) the execution result to a host computer through a master, wherein the host computer performs debugging to fix a bug of the slave using the execution result. The method of claim 1, And wherein said control bus is an I2C bus. The method of claim 1, And a control signal received in step (a) is a control signal including a flag for transmitting a control signal from the master to the slave. The method of claim 1, And a control signal transmitted through the master transmits an address of a place where the control signal is stored in the master, and the transmitted control signal is stored in the address. The method of claim 1, The execution result transmitted through the master receives the address for storing the execution result from the master, and debugging the slave, characterized in that for storing the execution result in the received address. In the recording medium on which a program of instructions that can be executed by a slave is implemented to perform a method for debugging a slave communicating with a master and a control bus. (A) receiving a control signal transmitted from a host computer connected by the master and a universal asynchronous transceiver (UART) through the master; Performing the received control signal (b); And And transmitting (c) the result of execution to a host computer through a master, wherein the host computer performs debugging to correct a bug of a slave using the result of execution. The method of claim 6, The control bus is a recording medium recording a program for debugging a slave, characterized in that the I2C bus. The method of claim 6, And a control signal received in the step (a) is a control signal including a flag for transmitting a control signal from the master to the slave. The method of claim 6, The control signal received through the master transmits the address where the master stores the control signal together, and the transmitted control signal is stored in the address. . The method of claim 6, The execution result transmitted through the master is a recording medium recording a debugging program of the slave, characterized in that for receiving the address storing the execution result from the master, and storing the execution result in the received address. In the debugging system of the slave, A host computer for generating control signals and performing debugging to fix bugs in the slave; A master coupled with the host computer to a general purpose asynchronous transceiver and coupled with the slave through a control bus; And A slave receiving the control signal transmitted from the host computer through the master to perform the received control signal and transmitting the result of the execution to the host computer through the master; And the host computer performs debugging for correcting a bug of the slave by using the execution result. The method of claim 11, And the control bus is an I2C bus. The method of claim 11, And a control signal received from the host computer is a control signal including a flag for transmitting a control signal from the master to the slave. The method of claim 11, And a control signal transmitted through the master transmits an address of a place where the control signal is stored in the master, and the transmitted control signal is stored in the address. The method of claim 11, The execution result transmitted through the master receives the address storing the execution result from the master, the debugging system of the slave, characterized in that for storing the execution result in the received address. In a slave that can be debugged without including a general purpose asynchronous transceiver, A slave transceiver which is connected to a master transceiver of a master that receives a control signal from a host computer and receives the control signal from the master transceiver; A processor unit which performs a process corresponding to the control signal received by the slave transceiver unit; And And a register map storing a control signal received by the slave transceiver and a result processed by the controller. The method of claim 16, And the register map is divided into an area in which the received control signal is stored and an area in which a result of performing the control signal is stored. The method of claim 16, The slave transceiver receives an address of an area in which the control signal is stored and an area in which a result of the control signal is stored from the master transceiver, and the register map performs the received control signal and the control signal. And storing a result in an area according to the address.

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