CN116049081A - SMBus slave digital module design method and device - Google Patents
SMBus slave digital module design method and device Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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Abstract
The application discloses a design method and a device of an SMBus slave digital module, wherein the SMBus slave digital module firstly receives a device address, a read-write address and read data sent by master devices, converts the read-write address and the read data into AHB bus information, then accesses a plurality of intra-chip modules in a chip according to the AHB bus information, and finally receives feedback data returned by the plurality of intra-chip modules. The SMBus slave digital module enables the master device outside the chip to access the content of the SMBus slave digital module and the registers in each on-chip module, and the content is not required to pass through JTAG or SWD interfaces. The SMBus slave digital module can also support multiple access formats, and the master device outside the chip can determine whether to access 1 or multiple words by issuing different command codes, so that the access efficiency of the SMBus read-write register is effectively improved.
Description
Technical Field
The application relates to the technical field of chip data transmission, in particular to a design method and device of an SMBus slave digital module.
Background
SMBus is a low rate communication that is used in mobile PC or desktop PC systems. It is mainly to control devices on the motherboard and collect corresponding information via an inexpensive and powerful bus (consisting of two wires). The SMBus provides a control bus for such tasks as system and power management, and the system using the SMBus can save the pin count of the device by using the SMBus to send and receive messages between the devices instead of using separate control lines.
The current asec chip design commonly realizes an SMBus module with an AMBA APB slave interface, which is generated by Synopsys Design Ware, and is an SMBus master relative to other SMBus devices. The SMBus module is realized by the design of an asic chip, but the supported access format is simpler, the read-write efficiency is lower, the AHB interface of the AMBA 2.0 standard is not realized, the data received by the SMBus bus is sent out through the AHB interface, and if other master modules in the chip are also used for accessing registers in the chip, the arbitration of the access can not be carried out by matching with an arbitration module conforming to the AMBA 2.0 standard.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a design method and a device for an SMBus slave digital module, which are used for accessing the content of each register in a chip through an SMBus interface by master equipment, and can support reading and writing of a plurality of words without a JTAG or SWD interface, so that the access efficiency of the SMBus read-write register is effectively improved.
The purpose of the application is realized through the following technical scheme:
in a first aspect, the present application proposes a method for designing an SMBus slave digital module, where the method is applied to an SMBus slave digital module in a chip, the chip is connected to a master device, and the SMBus slave digital module is connected to a plurality of intra-chip modules in the chip, and includes:
the SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
Optionally, the SMBus slave digital module includes an SMBus control component and an ahb_ctrl control component, and the step of converting the read-write address and the read data into AHB bus information by the SMBus slave digital module includes:
the SMBus control part sends the received read-write address to the AHB_CTRL control part through an ADDR bus;
the SMBus control component sends the received read data to the AHB_CTRL control component over a WDATA bus;
the ahb_ctrl control component converts the read-write address and the read data into AHB bus information. Optionally, the AHB bus information complies with AMBA 2.0 timing specification.
Optionally, the step of receiving, by the SMBus slave digital module, the device address, the read-write address and the read data sent by the master device includes:
the master device sends a starting instruction to enable the SMBus slave digital module to be started;
the master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit in the device address is 0, indicating that writing operation is to be performed, the master device sends a command code, and the SMBus slave digital module feeds back an ACK signal;
the master device sends byte count numbers, and the SMBus slave digital module feeds back ACK signals;
the master device sends a read-write address, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit 1 in the equipment address indicates that the read operation is to be performed, the SMBus slave digital module feeds back an ACK signal;
and the AHB_CTRL control component initiates a read request to a plurality of intra-chip modules according to the read-write address sent by the master device to obtain read data.
Optionally, after the master device sends a command code, the SMBus slave digital module further includes:
and if the check bit in the command code is 1, the master device sends out the check code, and the SMBus slave digital module feeds back an ACK signal.
In a second aspect, the present application further provides an SMBus slave digital module design apparatus, where the apparatus is applied to an SMBus slave digital module in a chip, the chip is connected to a master device, and the SMBus slave digital module is connected to a plurality of on-chip modules in the chip, and includes:
the SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
In a third aspect, the present application further proposes a computer device, the computer device comprising a processor and a memory, the memory having stored therein a computer program, the computer program being loaded and executed by the processor to implement the SMBus slave digital module design method according to any of the first aspects.
In a fourth aspect, the present application further proposes a computer readable storage medium, in which a computer program is stored, the computer program being loaded and executed by a processor to implement the SMBus slave digital module design method according to any of the first aspects.
The main scheme and each further option of the application can be freely combined to form a plurality of schemes, which are all schemes that can be adopted and claimed by the application; and the selection(s) of non-conflicting choices and other choices may be freely combined. Numerous combinations will be apparent to those skilled in the art upon review of the present application, and are not intended to be exhaustive or to be construed as limiting the scope of the invention.
The beneficial effects of this application lie in:
the SMBus slave digital module provided in the first embodiment of the present application enables the master device outside the chip to access the SMBus slave digital module and the content of the registers in each on-chip module, and does not need to pass through a JTAG or SWD interface.
The SMBus slave digital module provided by the second embodiment of the present application can support multiple access formats, and the master device outside the chip can determine whether to access 1 or multiple words by issuing different command codes (command codes), so that the access efficiency of the SMBus read-write register is effectively improved.
Thirdly, because of the AHB interface of the AMBA 2.0 specification, data is transmitted through the AHB interface, if other master modules are arranged in the chip, the registers in the chip are accessed, and the arbitration of the access can be carried out by matching with an arbitration module conforming to the AMBA 2.0 specification.
Drawings
Fig. 1 shows the connection relationship of the SMBus module and other modules in the related art.
Fig. 2 shows a schematic diagram of connection between the SMBus slave digital module and the master device according to an embodiment of the present application.
Fig. 3 shows an internal schematic diagram of the SMBus slave digital module provided in the embodiment of the present application.
FIG. 4 shows a master device reading 1 word of registers in the SMBus slave digital module.
Fig. 5 shows an access format diagram of function=011.
Fig. 6 shows an access format diagram of function=100.
Fig. 7 shows an access format diagram of function=101.
Fig. 8 shows an access format diagram of function=110.
Fig. 9 shows an access format diagram of function=111.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 shows a connection relationship between an SMBus module and other modules in the prior art, where an on-chip SMBus in the chip in the prior art is a slave module with respect to an off-chip SMBus device, and an off-chip SMBus device is a slave device with respect to an on-chip SMBus, and the master-slave relationship between the on-chip SMBus and the off-chip SMBus device is that the on-chip SMBus is the master, and then the off-chip SMBus device is the slave, and other modules in the chip configure the SMBus module through an APB bus interface, and then the SMBus actively initiates an access request to other SMBus devices outside the chip. Compared with other SMBus devices, the off-chip SMBus device has the advantages that the supported access format is simpler, and the read-write efficiency is lower. In addition, because the on-chip SMBus uses the APB bus interface to communicate with each on-chip module of the chip, the AMBA 2.0 standard AHB interface cannot be implemented. And sending out the data received by the SMBus bus through an AHB interface, and if other master modules in the chip are also used for accessing registers in the chip, performing access arbitration by matching with an arbitration module conforming to the AMBA 2.0 specification.
Therefore, in order to solve the above-mentioned problem, the present application proposes a design method of an SMBus slave digital module, so that the on-chip Bus module is an SMBus slave digital module with respect to the off-chip SMBus device, and the on-chip Bus module is used as a slave, and is exchanged with the master-slave relationship in the prior art, so that not only multiple access formats are supported, but also the read-write efficiency of the host to other on-chip modules through the SMBus is effectively improved, and the AHB interface of AMBA 2.0 specification is implemented, and then the design method of the SMBus slave digital module is described in detail.
Referring to fig. 2, fig. 2 shows a connection schematic diagram of an SMBus slave digital module and a master device, where the SMBus slave digital module is provided in an embodiment of the present application, and the chip includes an SMBus slave digital module, where the SMBus slave digital module is connected to an SMBus interface of the chip by using a data line and a clock line, and the other end of the interface is connected to the master device, where the master device is another SMBus device, and the on-chip SMBus slave digital module is further connected to a plurality of on-chip modules in the chip through an AHB bus, and the design method of the SMBus slave digital module includes the following steps:
the SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
Referring to fig. 3 with reference to fig. 2, fig. 3 shows an internal schematic diagram of an SMBus slave digital module provided in an embodiment of the present application, where the SMBus slave digital module includes an SMBus control unit and an ahb_ctrl control unit, and the SMBus control unit and the ahb_ctrl control unit are connected through an ADDR bus, a read data bus, and a write data bus. The step of converting the read-write address and the read data into AHB bus information includes:
the SMBus control part sends the received read-write address to the AHB_CTRL control part through an ADDR bus;
the SMBus control unit sends the received read data to the AHB_CTRL control unit through the WDATA bus;
the ahb_ctrl control unit converts read and write addresses and read data into AHB bus information.
The Smaster equipment outside the chip sends read-write address and read data through the data line and the clock line and the SMBus bus interface of the chip, the read-write address and the read data are converted into AHB bus information which accords with the AMBA 2.0 time sequence standard through the AHB_CTRL control component, then the AHB bus information accesses a plurality of intra-chip modules in the chip, the intra-chip modules feed back the read data, and the read data are transmitted to the SMBus bus interface through the SMBus slave digital module until the read data are finally transmitted to the master equipment.
Optionally, the substep of the SMBus slave digital module receiving the device address, the read-write address and the read data sent by the master device includes:
the master device sends a starting instruction to enable the SMBus slave digital module to be started;
the master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit in the device address is 0, indicating that writing operation is to be performed, transmitting a command code by the master device, and feeding back an ACK signal by the SMBus slave digital module;
the master device sends byte counting numbers, and the SMBus slave digital module feeds back an ACK signal;
the master device sends a read-write address, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit 1 in the device address indicates that the read operation is to be performed, the SMBus slave digital module feeds back an ACK signal;
the AHB_CTRL control component initiates read requests to a plurality of intra-chip modules according to read-write addresses sent by the master device to obtain read data.
If the check bit in the command code is 1, the master device sends out the check code, and the SMBus slave digital module feeds back an ACK signal.
It should be noted that, the SMBus slave digital module provided in the embodiment of the present application may support multiple access formats, and the off-chip SMBus device may determine to access 1 word (32 bits), 2 words (64 bits), 4 words (128 bits), or multiple words by issuing different command codes (command codes), please refer to fig. 4, fig. 4 shows a schematic diagram of a master device reading 1 word of a register in the SMBus slave digital module, and in combination with table 1, table 1 shows fields corresponding to command codes (command codes).
TABLE 1
The white background data in fig. 4 is issued by the master device, and the gray background data is fed back to the master device by the SMBus slave digital module. Table 2 shows fields corresponding to another command code (command code):
TABLE 2
Referring to fig. 4, table 1 and table 2, taking next the case of f ction=3' b110, the flow of the access format is as follows:
1. the master device initiates a START starting instruction to START the SMBus slave digital module;
2. the master device feeds back an ACK signal to the master device from a device address slave address (7' h 20) to an SMBus slave digital module;
3. since the read/write bit (W/R bit) is 0, it indicates that a write operation is to be performed, at this time, the master device sends an 8-bit command code (command code), the 0 th END bit of the command code is 0, the 1 st START bit is 1, which indicates the first transaction in the command across multiple transactions, the 2 nd to 4 th bits indicate that the f ction=010 performs a short-format word reading operation, the 7 th PEC check is 1, the master device sends out a check code, and the SMBus slave digital module feeds back an ACK signal;
4. the master device sends an 8-bit byte count number (byte count) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;
5. the master device sends 4 8-bit read-write addresses (offset byte) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal every time the SMBus slave digital module receives 1 8-bit read-write address;
6. because the 7 th PEC in the 8-bit command code is checked to be 1 by the master device, the master device continuously sends the 8-bit PEC check code to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal.
7. The master device sends a STOP instruction.
8. Because the master device sends the 2 nd bit to the 4 th bit of the 8-bit command code to indicate that FUCTION=010 carries out short-format word reading operation, the master device initiates a START starting instruction to START the SMBus slave digital module;
9. the device address slave address (7' h 20) to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal to the master device;
10. a read-write bit (W/R bit) of 0 indicates that a write operation is to be performed, at this time, the master device sends an 8-bit command code (command code), the 0 th END bit of the command code is 1, the 1 st START bit is 0, which indicates the last transaction in the commands that span multiple transactions, the 2 nd to 4 th bits indicate that the fuction=010 performs a short-format read operation, the 7 th PEC check is 1, the master device sends out a check code, and the SMBus slave digital module feeds back an ACK signal;
11. master device initiates a START START instruction to cause SMBus slave digital module to START
12. The master device feeds back an ACK signal to the master device from a device address slave address (7' h 20) to an SMBus slave digital module;
13. if the read-write bit (W/R bit) is 1, the SMBus slave digital module feeds back an ACK signal;
14. the SMBus slave digital module initiates an AHB read request to a plurality of on-chip modules in a chip through an AHB CTRL control component by using 4 8-bit read-write addresses (offset bytes) in the step 5, and obtains and stores corresponding 32-bit read data RDATA;
15. the SMBus slave digital module sends an 8-bit byte count number (byte count) in the 4 th step to a master device, and the master device feeds back an ACK signal;
16. the SMBus slave digital module sends the stored 32-bit read data RDATA to the master device, and the master device can receive a feedback ACK signal every time 1 8-bit read data RDATA is sent.
17. And (4) repeating the step (14), adding 4 to the 32-bit read-write address by the SMBus slave digital module, initiating an AHB read request to a plurality of intra-chip modules in the chip by the AHB CTRL control component, obtaining and storing the corresponding 32-bit read data RDATA, sending the stored 32-bit read data RDATA to a master device by the SMBus slave digital module, and receiving a master device feedback ACK signal after each time the stored 32-bit read data RDATA is sent to 1 8-bit read data RDATA.
18. And (2) repeating the step (14), adding 8 to the 32-bit read-write address by the SMBus slave digital module, initiating an AHB read request to a plurality of intra-chip modules in the chip by the AHB CTRL control component, obtaining and storing the corresponding 32-bit read data RDATA, sending the stored 32-bit read data RDATA to a master device by the SMBus slave digital module, and receiving a master device feedback ACK signal after each time the stored 32-bit read data RDATA is sent to 1 8-bit read data RDATA.
19. And (2) repeating the step (14), adding 12 to the 32-bit read-write address by the SMBus slave digital module, initiating an AHB read request to a plurality of intra-chip modules in the chip by the AHB CTRL control component, obtaining and storing the corresponding 32-bit read data RDATA, sending the stored 32-bit read data RDATA to a master device by the SMBus slave digital module, and receiving a master device feedback ACK signal after each time the stored 32-bit read data RDATA is sent to 1 8-bit read data RDATA.
20. Because the 7 th PEC in the 8-bit command code is checked to be 1 by the master device, the master device continuously sends the 8-bit PEC check code to the SMBussslave digital module, and the SMBussslave digital module feeds back an ACK signal.
21. The master device sends a STOP instruction.
In addition, since the fields of the fusion have different fields, fig. 5 to 9 show access format diagrams under the different fields of the fusion, fig. 5 shows an access format diagram with function=011, and the master device writes 1 word of a register in the SMBus slave digital module; fig. 6 shows an access format diagram with function=100, and the master device continuously reads 2 words of a register in the SMBus slave digital module; fig. 7 shows an access format diagram of function=101, and the master device writes 2 words of registers in the SMBus slave digital module successively; fig. 8 shows an access format diagram with function=110, and the master device continuously reads 4 words of registers in the SMBus slave digital module; fig. 9 shows a schematic diagram of an access format with function=111, where the master device continuously writes 4 words in a register in the SMBus slave digital module, and the flow of the access format is as described above, and will not be described in detail here.
Compared with the prior art, the embodiment of the application has the following beneficial effects:
the SMBus slave digital module provided in the first embodiment of the present application enables the master device outside the chip to access the SMBus slave digital module and the content of the registers in each on-chip module, and does not need to pass through a JTAG or SWD interface.
The SMBus slave digital module provided by the second embodiment of the present application can support multiple access formats, and the master device outside the chip can determine whether to access 1 or multiple words by issuing different command codes (command codes), so that the access efficiency of the SMBus read-write register is effectively improved.
Thirdly, because of the AHB interface of the AMBA 2.0 specification, data is transmitted through the AHB interface, if other master modules are arranged in the chip, the registers in the chip are accessed, and the arbitration of the access can be carried out by matching with an arbitration module conforming to the AMBA 2.0 specification.
In addition, the embodiment of the application also provides an SMBus slave digital module design device which is applied to the SMBus slave digital module in the chip, the chip is connected with the master device, and the SMBus slave digital module is connected with a plurality of on-chip modules in the chip.
The SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
The embodiment of the present application provides a computer device, which can implement the steps in any embodiment of the SMBus slave digital module design method provided in the embodiment of the present application, so that the beneficial effects of the SMBus slave digital module design method provided in the embodiment of the present application can be implemented, which are detailed in the previous embodiments and are not repeated herein.
Those of ordinary skill in the art will appreciate that all or a portion of the steps of the various methods of the above embodiments may be performed by instructions, or by instructions controlling associated hardware, which may be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, embodiments of the present application provide a storage medium having stored therein a plurality of instructions capable of being loaded by a processor to perform the steps of any of the embodiments of the SMBus slave digital module design methods provided by the embodiments of the present application.
Wherein the storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.
Because the instructions stored in the storage medium may perform the steps in any of the embodiments of the SMBus slave digital module design method provided in the embodiments of the present application, the beneficial effects that any of the embodiments of the SMBus slave digital module design method provided in the embodiments of the present application may be achieved, which are detailed in the previous embodiments and are not described herein.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but is intended to cover any and all modifications, equivalents, and alternatives falling within the spirit and principles of the present application.
Claims (8)
1. The SMBus slave digital module design method is characterized in that the method is applied to an SMBus slave digital module in a chip, the chip is connected with master equipment, and the SMBus slave digital module is connected with a plurality of on-chip modules in the chip, and comprises the following steps:
the SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
2. The SMBus slave digital module design method of claim 1, wherein said SMBus slave digital module includes an SMBus control component and an ahb_ctrl control component, said SMBus slave digital module converting said read and write addresses and said read data into AHB bus information comprising:
the SMBus control part sends the received read-write address to the AHB_CTRL control part through an ADDR bus;
the SMBus control component sends the received read data to the AHB_CTRL control component over a WDATA bus;
the ahb_ctrl control component converts the read-write address and the read data into AHB bus information.
3. The SMBus slave digital module design method of claim 2, wherein said AHB bus information complies with AMBA 2.0 timing specification.
4. The SMBus slave digital module design method of claim 2, wherein the step of receiving, by the SMBus slave digital module, a device address, a read-write address, and read data sent by a master device, comprises:
the master device sends a starting instruction to enable the SMBus slave digital module to be started;
the master device sends a device address to the SMBus slave digital module, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit in the device address is 0, indicating that writing operation is to be performed, the master device sends a command code, and the SMBus slave digital module feeds back an ACK signal;
the master device sends byte count numbers, and the SMBus slave digital module feeds back ACK signals;
the master device sends a read-write address, and the SMBus slave digital module feeds back an ACK signal;
if the read-write bit 1 in the equipment address indicates that the read operation is to be performed, the SMBus slave digital module feeds back an ACK signal;
and the AHB_CTRL control component initiates a read request to a plurality of intra-chip modules according to the read-write address sent by the master device to obtain read data.
5. The SMBus slave digital module design method as set forth in claim 4, wherein after said master device transmits a command code, said SMBus slave digital module feedback ACK signal further comprises:
and if the check bit in the command code is 1, the master device sends out the check code, and the SMBus slave digital module feeds back an ACK signal.
6. An SMBus slave digital module design apparatus, wherein the apparatus is applied to an SMBus slave digital module in a chip, the chip is connected to a master device, and the SMBus slave digital module is connected to a plurality of on-chip modules in the chip, and comprises:
the SMBus slave digital module receives the device address, the read-write address and the read data sent by the master device;
the SMBus slave digital module converts the read-write address and the read data into AHB bus information;
the SMBus slave digital module accesses a plurality of intra-chip modules in the chip according to the AHB bus information;
the SMBus slave digital module receives feedback data returned by the plurality of intra-chip modules.
7. A computer device comprising a processor and a memory, wherein the memory has stored therein a computer program that is loaded and executed by the processor to implement the SMBus slave digital module design method of any of claims 1-5.
8. A computer-readable storage medium, wherein a computer program is stored in the storage medium, and the computer program is loaded and executed by a processor to implement the SMBus slave digital module design method of any one of claims 1-5.
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| CN202211726418.1A CN116049081A (en) | 2022-12-30 | 2022-12-30 | SMBus slave digital module design method and device |
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| CN202211726418.1A CN116049081A (en) | 2022-12-30 | 2022-12-30 | SMBus slave digital module design method and device |
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| CN117057286A (en) * | 2023-10-11 | 2023-11-14 | 成都电科星拓科技有限公司 | SMBus module level verification system based on UVM and VIP |
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