CN102447601B - S-bus monobus communicating circuit - Google Patents
S-bus monobus communicating circuit Download PDFInfo
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- CN102447601B CN102447601B CN201110359472.2A CN201110359472A CN102447601B CN 102447601 B CN102447601 B CN 102447601B CN 201110359472 A CN201110359472 A CN 201110359472A CN 102447601 B CN102447601 B CN 102447601B
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- nmos tube
- tristate buffer
- bus
- reverse tristate
- source electrode
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Abstract
The invention discloses s-bus monobus communicating circuit, wherein MCU asserts signal respectively with the connection of the grid of NMOS tube (M1) and the grid of NMOS tube (M2); S-bus monobus is connected with the drain electrode of the drain electrode of NMOS tube (M1), the grid of PMOS (M3), the source electrode of PMOS (M3) and NMOS tube (M2) respectively; The source ground of NMOS tube (M2), the drain electrode of PMOS (M3) is connected with the source electrode of NMOS tube (M2); MCU sends signal and is connected with the first input end of reverse tristate buffer, the source electrode of NMOS tube (M2) is connected with the second input of reverse tristate buffer, MCU transmits control signal and to be connected with the first control end of reverse tristate buffer, second control end ground connection of reverse tristate buffer, first output of reverse tristate buffer is connected with the source electrode of NMOS tube (M2), and MCU Received signal strength (MCUSCI-Rx) is connected with the second output of reverse tristate buffer.The SCI general line system of single-chip microcomputer is passive monobus by the present invention, realizes the communication of asynchronous serial quasi-duplex mode.
Description
Technical field
The present invention relates to electronic circuit field, particularly relate to s-bus monobus communicating circuit.
Background technology
Most of bus is formed all in the same manner, and its difference is only the number of data wire and address wire in bus and the number of control line and function thereof.Different according to connected mode, the bus structures adopted in control system have three basic forms of it: unibus structure, dual-bus structure and multiple bus architecture.
Monobus is applicable to single host system, can control one or more slave devices.Main frame can be microcontroller (MCU), can be single wire bus device also can be from microcontroller from machine, and the exchanges data between them is only by a signal line.When only having a slave devices, system can operate by single node system; When there is a plurality of slave devices, system then presses multi-node system operation.
At present, business Application comparison widely Single Wire Bus Technology is 1-wirebus bus, and hardware designs is integrated in one block of communicating circuit plate.As different in SPI/I2C/SCI/RS485 from current most standard serial data communication mode, it adopts single holding wire, accurate bi-directional transfer of data.1-wirebus bus have save I/O mouth line resource, structure simple, with low cost, be convenient to the plurality of advantages such as bus extension and maintenance.
1-wirebus bus is applied in general industry control system mostly, has certain limitation.First, in some distributed master & slave control systems, need could realize monobus communication at master microprocessor with from there is 1-wirebus function between microprocessor simultaneously.If do not have built-in 1-wirebus function in microprocessor, employing simulation 1-wirebus communication then sequential more complicated not easily realizes.Secondly, under the high and low temperature applied environment that some is special, the hardware being integrated with the military of 1-wirebus function or space flight level is also fewer.
Summary of the invention
For the above-mentioned problems in the prior art, the invention provides s-bus monobus communicating circuit.
The invention provides s-bus monobus communicating circuit, comprise the first NMOS tube M1, the second NMOS tube M2, PMOS M3 and reverse tristate buffer U1; MCU asserts signal (MCURST) respectively with the connection of the grid of the first NMOS tube M1 and the grid of the second NMOS tube M2; S-bus monobus is connected with the drain electrode of the drain electrode of the first NMOS tube M1, the grid of PMOS M3, the source electrode of PMOS M3 and the second NMOS tube M2 respectively; The source ground of the second NMOS tube M2, the drain electrode of PMOS M3 is connected with the source electrode of the second NMOS tube M2; MCU sends signal MCTSCT-Tx and is connected with the first input end of reverse tristate buffer U1, the source electrode of the second NMOS tube M2 is connected with second input of reverse tristate buffer U1, MCU transmits control signal and to be connected with first control end of reverse tristate buffer U1, the second control end ground connection of reverse tristate buffer U1, first output of reverse tristate buffer U1 is connected with the source electrode of the second NMOS tube M2, and MCU Received signal strength MCUSCI-Rx is connected with second output of reverse tristate buffer U1.
In one example, MCU asserts signal MCURST is connected with the grid of the first NMOS tube M1 by resistance R3, and the grid of the first NMOS tube M1 is also through electric capacity C1 ground connection; MCU asserts signal MCURST is connected with the grid of the second NMOS tube M2 by resistance R4, and the grid of the second NMOS tube M2 is also through electric capacity C2 ground connection; Second input of reverse tristate buffer U1, through electric capacity C3 ground connection, is connected with the source electrode of the second NMOS tube M2, and the source electrode of the second NMOS tube M2 is also through resistance R5 ground connection.
In one example, s-bus monobus through resistance R1 respectively with the connection of the grid of the first NMOS tube M1 and the grid of the second NMOS tube M2; The first input end of reverse tristate buffer U1 connects supply voltage through resistance R2.
In one example, reverse tristate buffer U1 is 54HC368 or 74HC368.
In one example, MCU sends signal MCTSCT-Tx and is connected with the first input end D1-D4 of reverse tristate buffer U1, and the second input D5-D6 of reverse tristate buffer U1 is through electric capacity C3 ground connection.
In one example,
The first output Q1 of described reverse tristate buffer U1 is connected with the source electrode of the second NMOS tube M2 through resistance R6, the first output Q2 of reverse tristate buffer U1 is connected with the source electrode of the second NMOS tube M2 through resistance R7, the first output Q3 of reverse tristate buffer U1 is connected with the source electrode of the second NMOS tube M2 through resistance R8, the first output Q4 of reverse tristate buffer U1 is connected with the source electrode of the second NMOS tube M2 through resistance R9, and MCU Received signal strength MCUSCI-Rx is connected with the second output Q5-Q6 of reverse tristate buffer U1.
The SCI general line system of single-chip microcomputer can be passive monobus by the present invention, realizes the communication of asynchronous serial quasi-duplex mode, utilizes speed-sensitive switch field effect transistor, realize Bus isolation defencive function; Components and parts all select surface-mounted device, reduce circuit board size, adopt high temperature printed circuit board simultaneously, so that save space and adapt to high-temperature work environment.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the present invention is described in further detail, wherein:
Fig. 1 is s-bus monobus communicating circuit figure.
Embodiment
The present invention uses six reverse tristate buffer/line drive 74/54HC368, the Tx of microprocessor SCI bus and rx buffering are exported or input, the switching characteristic of recycling high speed metal-oxide-semiconductor field effect transistor realizes Isolation input and the output of s-bus monobus, and bus sending/receiving controls by microprocessor I/O cause for gossip existing.This bus protocol observes RS-232 communications protocol, and bus signals is CMOS level.As shown in Figure 1, the mono-communication bus of s-bus connects the drain electrode of the first NMOS tube M1 and the grid of PMOS M3 through resistance R1 to circuit, and the mono-communication bus of s-bus is also directly connected with the source electrode of PMOS M3 and the drain electrode of the second NMOS tube M2.The source electrode of the second NMOS tube M2 is connected with the drain electrode of PMOS M3, and the grid of the second NMOS tube M2 is through electric capacity C2 ground connection.The grid of the second NMOS tube M2 also connects MCURST signal through resistance R4.The grid of the first NMOS tube M1 through electric capacity C ground connection, and connects MCURST signal through resistance R3.Six reverse tristate buffer U1(54HC368) input D1-D4 link together and meet power supply VCC through resistance R2, MCUSCI-Tx sends the input D1-D4 of signal access six reverse tristate buffer U1, the input D5-D6 of six reverse tristate buffer U1 connects the source electrode of the second NMOS tube M2 through resistance R10, and through electric capacity C3 ground connection; The source electrode of the second NMOS tube M2 is also through resistance R5 ground connection, MCU transmits control signal and meets the control end G1 of six reverse tristate buffer U1, the control end G2 ground connection of six reverse tristate buffer U1, MCUSCI-Rx Received signal strength connects, the output Q5-Q6 of six reverse tristate buffer U1.The output Q1 of six reverse tristate buffer U1 connects the source electrode of the second NMOS tube M2 through resistance R6, the output Q2 of six reverse tristate buffer U1 connects the source electrode of the second NMOS tube M2 through resistance R7, the output Q3 of six reverse tristate buffer U1 connects the source electrode of the second NMOS tube M2 through resistance R8, the output Q4 of six reverse tristate buffer U1 connects the source electrode of the second NMOS tube M2 through resistance R9.
In distributed master and slave control system, host computer is as controller, and main process, from the data of slave computer, sends order to slave computer, and slave computer is used as to measure, control and the order of response host computer.The communication of s-bus monobus completes under each microprocessor-based control in host computer and slave computer.
When host computer microprocessor sends order or slave computer microprocessor sends data, first microprocessor will " send and control " and be set to low level, the input D1-D4 of six reverse tristate buffer U1 opens, the SCI-Tx of microprocessor sends signal, NMOS tube M3 drain electrode is sent to through R6-R9, due to the grid of NMOS tube M3 by the first NMOS tube M1 clamper in low level, therefore PMOS M3 conducting, SCI-Tx sends signal will be passed to s-bus bus.After instruction or data are sent completely, microprocessor will " send and control " and be set to high level, make the output Q1-Q4 of six reverse tristate buffer U1 be in high-impedance state.
When host computer microprocessor receives data or slave computer microprocessor receives order, signal on the mono-communication bus of s-bus is to the drain electrode of the second NMOS tube M2, the MCURST end connect due to the grid of the second NMOS tube M2 is high level, second NMOS tube M2 conducting, the capacitance-resistance filter that signal forms through resistance R10 and electric capacity C3 is to the output D5-D6 of six reverse tristate buffer U1.The control end G2 ground connection of six reverse tristate buffer U1, therefore signal by the output D5-D6 of six reverse tristate buffer U1 to the SCI-Rx receiving terminal of microprocessor.
MCURST controls the first NMOS tube M1 when being used for powering on, the second NMOS tube M2 is in cut-off state, plays isolation s-bus and MCU effect.Bus communication observes RS-232 communications protocol, adopts a point time-division location mechanics of communication for single host computer to avoid bus collision.
The present invention utilizes six reverse tristate buffers/line drive 74HC/54HC368 device to realize the conversion of list-dual bus under control of the microprocessor, strengthen the driving force to signal further simultaneously, thus monobus Communication when solving the combination of branched instrument.
The foregoing is only the preferred embodiment of the present invention, but scope is not limited thereto.Any those skilled in the art, in technical scope disclosed by the invention, all can carry out suitable change or change to it, and this change or change all should be encompassed within protection scope of the present invention.
Claims (5)
1.s-bus monobus communicating circuit, is characterized in that, comprises the first NMOS tube (M1), the second NMOS tube (M2), the 3rd PMOS (M3) and reverse tristate buffer (U1), MCU asserts signal (MCURST) is connected with the grid of the first NMOS tube (M1) and the grid of the second NMOS tube (M2) respectively, control the first NMOS tube (M1) when described MCU asserts signal (MCURST) is for powering on, the second NMOS tube (M2) is in cut-off state, s-bus monobus is connected with the grid of the drain electrode of the first NMOS tube (M1), the 3rd PMOS (M3), the source electrode of the 3rd PMOS (M3) and the drain electrode of the second NMOS tube (M2) respectively, the source ground of the first NMOS tube (M1), the drain electrode of the 3rd PMOS (M3) is connected with the source electrode of the second NMOS tube (M2), MCU sends 2 of the first input end group of signal (MCUSCI-Tx) and reverse tristate buffer (U1), 4, 6, 10 pin connect, 3 of the source electrode of the second NMOS tube (M2) and the second input group of reverse tristate buffer (U1), 5, 7, 9 pin connect, MCU transmits control signal and to be connected with first control end (1 pin) of reverse tristate buffer (U1), second control end (15 pin) ground connection of reverse tristate buffer (U1), 12 of first output group of reverse tristate buffer (U1), 14 pin are connected with the source electrode of the second NMOS tube (M2), 11 of second output group of MCU Received signal strength (MCUSCI-Rx) and reverse tristate buffer (U1), 13 pin connect, MCU asserts signal (MCURST) is connected with the grid of the first NMOS tube (M1) by the 3rd resistance (R3), and the grid of the first NMOS tube (M1) is also through the first electric capacity (C1) ground connection, MCU asserts signal (MCURST) is connected with the grid of the second NMOS tube (M2) by the 4th resistance (R4), and the grid of the second NMOS tube (M2) is also through the second electric capacity (C2) ground connection, 3,5,7,9 pin of the second input group of reverse tristate buffer (U1) are through the 3rd electric capacity (C3) ground connection, be connected with the source electrode of the second NMOS tube (M2), the source electrode of the second NMOS tube (M2) is also through the 5th resistance (R5) ground connection.
2. s-bus monobus communicating circuit as claimed in claim 1, it is characterized in that, s-bus monobus is connected with the grid of the first NMOS tube (M1) and the grid of the second NMOS tube (M2) respectively through the first resistance (R1); 2,4,6,10 pin of the first input end group of reverse tristate buffer (U1) connect supply voltage through the second resistance (R2).
3. s-bus monobus communicating circuit as claimed in claim 2, it is characterized in that, reverse tristate buffer (U1) is 54HC368 or 74HC368.
4. s-bus monobus communicating circuit as claimed in claim 3, it is characterized in that, MCU sends signal (MCUSCI-Tx) and is connected with 2,4,6,10 pin of the first input end group of reverse tristate buffer (U1), and 12,14 pin of the first output group of reverse tristate buffer (U1) are through the 3rd electric capacity (C3) ground connection.
5. s-bus monobus communicating circuit as claimed in claim 4, it is characterized in that, 3 pin of the second input group of reverse tristate buffer (U1) are connected with the source electrode of the second NMOS tube (M2) through the 6th resistance (R6), 5 pin of the second input group of reverse tristate buffer (U1) are connected with the source electrode of the second NMOS tube (M2) through the 7th resistance (R7), 7 pin of the second input group of reverse tristate buffer (U1) are connected with the source electrode of the second NMOS tube (M2) through the 8th resistance (R8), 9 pin of the second input group of reverse tristate buffer (U1) are connected with the source electrode of the second NMOS tube (M2) through the 9th resistance (R9), 11 of second output group of MCU Received signal strength (MCUSCI-Rx) and reverse tristate buffer (U1), 13 pin connect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110359472.2A CN102447601B (en) | 2011-11-14 | 2011-11-14 | S-bus monobus communicating circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110359472.2A CN102447601B (en) | 2011-11-14 | 2011-11-14 | S-bus monobus communicating circuit |
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| CN102447601A CN102447601A (en) | 2012-05-09 |
| CN102447601B true CN102447601B (en) | 2015-12-09 |
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| CN201110359472.2A Active CN102447601B (en) | 2011-11-14 | 2011-11-14 | S-bus monobus communicating circuit |
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| CN102897600B (en) * | 2012-10-17 | 2014-04-02 | 浙江理工大学 | Single-bus automatic air splicing system with pressure signal feedback |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005427A (en) * | 2006-12-22 | 2007-07-25 | 华为技术有限公司 | 485 bus system and method for transmitting data |
| CN201422115Y (en) * | 2009-05-04 | 2010-03-10 | 福建师范大学 | Single bus interface timing analyzer |
| CN101741515A (en) * | 2009-12-31 | 2010-06-16 | 煤炭科学研究总院重庆研究院 | Single-bus two-way communication circuit |
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- 2011-11-14 CN CN201110359472.2A patent/CN102447601B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101005427A (en) * | 2006-12-22 | 2007-07-25 | 华为技术有限公司 | 485 bus system and method for transmitting data |
| CN201422115Y (en) * | 2009-05-04 | 2010-03-10 | 福建师范大学 | Single bus interface timing analyzer |
| CN101741515A (en) * | 2009-12-31 | 2010-06-16 | 煤炭科学研究总院重庆研究院 | Single-bus two-way communication circuit |
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