CN207367195U - A kind of IIC interface expansion boards - Google Patents

Abstract

The utility model discloses a kind of IIC interface expansion boards, the plate body of expansion board is equipped with N bar IIC signal paths；N is integer, N >=2；Each IIC signal paths are equipped with a bidirectional bus buffer.The IIC interface expansion board simple circuits, it is easy to implement, the load capacity of IIC interfaces can be improved.

Description

An IIC interface expansion board

technical field

The utility model relates to an IIC interface expansion board.

Background technique

IIC stands for Integrated Circuit Bus, which is a bidirectional, binary, synchronous serial bus. The bus is a multi-directional control bus. Multiple chips can be connected to the same bus structure, and each chip can be used as a control source for real-time data transmission. The devices hanging on the IIC bus are divided into master and slave. The master is responsible for initializing the data of the IIC bus and generating a clock signal that allows transmission. The slave is a device that has a unique slave address and is addressed by the master. In view of the fact that IIC is easy to use and occupies less interface resources, it is becoming more and more popular in fields such as sensor data acquisition.

In common application scenarios, multiple IIC slave devices are generally directly connected to the bus for communication. However, due to reasons such as the limited drive capability of the bus and the support for capacitive reactance, the devices that can be mounted on the bus and the transmission length of the bus are limited. It cannot meet the requirements of some IIC application scenarios. Therefore, IIC needs to be extended.

For the method of IIC interface expansion, some utility model patents have proposed solutions. For example, CN101324875A proposes a method based on expanding the first-level IIC bus of the master device into multiple second-level IIC buses. This patent includes a clock expansion module, a data control module and a direction control module. The clock expansion module converts the SCL signal of the first-level IIC Expanded into multiple channels, the data control module is used for the selection of the secondary IIC bus, and the direction control module controls the direction of reading and writing. Another example is the expansion mode based on the CPLD OR gate proposed by CN104142905A, a (n+1) data register is set and each input end of the OR gate is divided into a bit of the corresponding data register to realize the expansion of the IIC slave device. Another example is the method based on the clock switch group proposed by CN1599343A. Only the devices connected to the clock switch in the clock switch group can respond to the request of the IIC bus controller. After the corresponding IIC bus read and write operations are completed, the corresponding clock switch is turned off.

The IIC interface expansion method proposed in the current patent mostly uses an external clock expansion module to form a multi-channel clock, and then selects the connected IIC slave device by the gating circuit, or performs a bitwise operation on the address signal of the slave device through the CPLD gate circuit. . These methods are mostly aimed at multiple slave device connection scenarios with the same non-modifiable slave address, but for limited access devices due to insufficient drive of IIC itself, or the bus transmission distance cannot be too far due to limited access capacitance of IIC itself, or Due to hardware limitations, it is impossible to access multiple bus level application scenarios, and no suitable solution is given; moreover, the above-mentioned patents often introduce other devices such as CPLD and FPGA, which increases the complexity of hardware routing and the difficulty of software programming .

Therefore, it is necessary to design an IIC interface expansion board.

Utility model content

The technical problem to be solved by the utility model is to provide an IIC interface expansion board, and the IIC interface expansion board expands the IIC interface through the expansion board, which is easy to implement.

The technical solution of the utility model is as follows:

An IIC interface expansion board, N IIC signal paths are arranged on the body of the expansion board; N is an integer, N≥2; each IIC signal path is provided with a bidirectional bus buffer.

The two-way bus buffer adopts P82B96 chip.

N is any value in 2-10.

N is 4.

The board is provided with an interface for connecting to the MCU.

The board is provided with a connector for connecting to the IIC bus.

In order to achieve level matching between the board and the MCU, the first end of the N IIC signal paths is connected to a DC voltage V1 through a pull-up resistor, and V1 is the reference voltage of the IIC interface of the MCU;

In order to achieve level matching between the board and the IIC load, the second end of the N IIC signal paths is connected to a DC voltage V2 through a pull-up resistor, and V2 is the reference voltage of the IIC interface at the load end.

V1 is 3.3V.

V2 is 12V.

The board body is a PCB board.

A device based on an IIC interface expansion board, including an MCU and an expansion board; N IIC signal paths are arranged on the expansion board; N is an integer, and N≥2;

The first ends of the N IIC signal paths on the expansion board are respectively connected to the N IIC interfaces on the MCU;

The second ends of the N IIC signal paths on the expansion board are respectively connected to N IIC buses.

The IIC interface on the MCU is the interface of the IIC controller.

The IIC interface on the MCU is an IIC interface simulated by a general-purpose IO port.

The IIC interface on the MCU is the IIC interface realized by the IP core.

Each IIC signal path on the expansion board is provided with a bidirectional bus buffer. A P82B96 chip is preferred.

The MCU is integrated in the core board.

A field programmable gate array is also integrated in the core board. If the MCU has a field programmable gate array inside, such as ZC7020 chip, etc., the IIC interface function can be realized by the programmable gate array, and the MCU does not have to have this function.

In order to achieve level matching between the expansion board and the MCU, the first end of the N IIC signal paths is connected to a DC voltage V1 through a pull-up resistor, and V1 is the reference voltage of the IIC interface of the MCU.

In order to achieve level matching between the expansion board and the IIC load, the second end of the N IIC signal paths is connected to a DC voltage V2 through a pull-up resistor, and V2 is the reference voltage of the IIC interface at the load end.

Beneficial effect:

The device of the IIC interface expansion board of the utility model makes the hardware circuit board more compatible with the collection of downlink IIC slave devices, can meet the expansion of the IIC slave devices, and supports conversion of up to four different bus levels. When the number of slave devices is small and the types of IIC bus levels are small, the buffer chip of the expansion board can be selectively soldered without increasing the additional cost of the system.

Description of drawings

Figure 1 is a block diagram of the overall structure of the IIC interface expansion board;

FIG. 2 is a schematic diagram of the connection of one IIC signal path.

Figure 3 is a schematic diagram of the definitions of interfaces 0-3 and power interfaces;

Fig. 4 is a schematic diagram of interface definition of a certain plug-in component.

Detailed ways

The utility model will be described in further detail below in conjunction with accompanying drawing and specific embodiment:

Embodiment 1: As shown in Figures 1-2, an IIC interface expansion board, the body of the expansion board is provided with 4 IIC signal paths; 4 is an integer, N≥2; each IIC signal path is provided with a bidirectional bus buffer device.

The two-way bus buffer adopts P82B96 chip.

The board is provided with an interface for connecting to the MCU.

The board is provided with a connector for connecting to the IIC bus.

In order to achieve level matching between the board and the MCU, the first end of the N IIC signal paths is connected to a DC voltage V1 through a pull-up resistor, and V1 is the reference voltage of the IIC interface of the MCU;

In order to achieve level matching between the board and the IIC load, the second end of the N IIC signal paths is connected to a DC voltage V2 through a pull-up resistor, and V2 is the reference voltage of the IIC interface at the load end.

V1 is 3.3V.

V2 is 12V.

The board body is a PCB board.

As shown in Figure 1-2, a device based on an IIC interface expansion board includes an MCU and an expansion board; four IIC signal paths are provided on the expansion board; the first ends of the four IIC signal paths on the expansion board are respectively Connect with 4 IIC interfaces on the MCU;

The second ends of the four IIC signal paths on the expansion board are respectively connected to four IIC buses.

The IIC interface on the MCU is the interface of the IIC controller, that is, the IIC interface on the MCU is used, specifically two.

The IIC interface on the MCU is an IIC interface simulated by a general-purpose IO port, that is, an IIC interface is simulated through an IO interface, specifically one.

The IIC interface on the MCU is an IIC interface implemented by an IP core, that is, the IP core is used to configure an IIC interface, specifically one.

Each IIC signal path on the expansion board is provided with a bidirectional bus buffer. A P82B96 chip is preferred.

The MCU is integrated in the core board.

A field programmable gate array is also integrated in the core board.

In order to achieve level matching between the expansion board and the MCU, the first end of the four IIC signal paths is connected to a DC voltage V1 through a pull-up resistor. V1 is the reference voltage of the IIC interface of the MCU, specifically 3.3V.

In order to achieve level matching between the expansion board and the IIC load, the second end of the N IIC signal paths is connected to a DC voltage V2 through a pull-up resistor, and V2 is the reference voltage of the IIC interface at the load end, such as 12V, it may not necessarily be 12V , depending on the working level of the IIC slave device, the picture shows the connection of a bus taking 12V as an example.

The multi-channel IIC expansion method and device of the present utility model include the following modules:

Core board module, which is the smallest system including CPU. It can lead to independent 4-way IIC interfaces IIC0-IIC3 (which can be realized by the built-in IIC controller of the MCU, IO simulation or the IP core built into the field programmable gate array MCU such as ZC7020), responsible for issuing read and write timing, Return ACK, and save, parse and process the data from the device.

The expansion board module is a separate circuit board, which is connected to the core board by means of cables or connectors. There are four sets of interfaces for the upper core board, respectively connected to the four IIC controllers of the core board, and four sets of power interfaces for connecting different level buses and multiple sets of IIC interfaces for connecting IIC slave devices. There are four P82B96 buffer chips on the board to increase the capacitive reactance of the IIC slave device that the system can support, and convert four different bus logic levels to the level of the MCU.

P82B96 is a bidirectional bus buffer; P82B96 is a bipolar, internally latch-free, bidirectional logic interface device, which provides a bridge between standard I ² C devices and long-distance buses, and can connect similar buses of different voltage and current levels Bridge with I ² C bus. The device can bridge SMBus (350μA), 3.3V logic devices, 15V level and low impedance wires can extend the communication distance and increase the anti-interference ability. The device has no special requirements for the I ² C bus protocol and clock rate. P82B96 can increase the number of minimum loads, new bus loads and remote I ² C bus devices connected to I ² C bus nodes without affecting the local nodes. The number of attached devices and physical limitations are also greatly reduced. Signals are sent through balanced transmission lines (twisted pair) or optocoupler isolation (fiber optics). The structural separation of Tx and Rx makes it easy to send, and the Tx and Rx signals are directly connected without locking.

The slave device module is a variety of intelligent acquisition sensors that support the IIC bus transmission protocol. Taking the application scenario on a train as an example, this module includes acceleration sensors, inclination sensors, temperature sensors, and pressure sensors. Sensors of the same type or with the same bus level and amplitude are connected to the same connector group, which is convenient for the P82B96 chip to convert the corresponding level to a suitable threshold and then output the signal to the core board.

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present utility model, but should not be construed as limiting the present utility model. On the contrary, the embodiments of the present invention include all changes, modifications and equivalents falling within the spirit and scope of the appended claims. The description in this part is only exemplary and explanatory, and should not have any limiting effect on the protection scope of the present utility model. In addition, those skilled in the art can make corresponding combinations of features in the embodiments in this document and in different embodiments according to the descriptions in this document.

In the description of the present utility model, it should be noted that unless otherwise specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection, or Integratively connected; it can be mechanically or electrically connected; it can be directly connected or indirectly connected through an intermediary. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention in specific situations. In addition, in the description of the present utility model, unless otherwise specified, "plurality" means two or more.

Any process or method descriptions in flowcharts or otherwise described herein may be understood to represent modules, segments or portions of code comprising one or more executable instructions for implementing specific logical functions or steps of the process , and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order depending on the functions involved, which It should be understood by those skilled in the art to which the embodiments of the present invention belong.

As shown in Figure 2, it is a schematic diagram of hardware connection using the MCU single-channel IIC interface and its corresponding circuit as an example. It should be noted that, in Fig. 2, the IO port of the MCU and the power supply level are 3.3V, the IIC bus level drawn by the sensor is 12V, and four external sensors are used for illustration, and the utility model is responsible for collecting There is no fixed value for the number of IIC devices and the bus level, and the example of four sensors and fixed level is just for clarity.

As shown in Figure 2, it is an example with four IIC slave devices.

Claims (9)

1. A kind of IIC interface expansion board, it is characterized in that, the board body of expansion board is provided with N IIC signal paths; N is an integer, N≥2; Each IIC signal path is provided with a bidirectional bus buffer; The two-way bus buffer adopts P82B96 chip. 2. The IIC interface expansion board according to claim 1, wherein N is any value in 2-10. 3. The IIC interface expansion board according to claim 2, wherein N is 4. 4. The IIC interface expansion board according to claim 1, characterized in that, the board body is provided with an interface for connecting to the MCU. 5. The IIC interface expansion board according to claim 1, wherein a connector for connecting to the IIC bus is provided on the board body. 6. The IIC interface expansion board according to claim 1, wherein, in order to realize the level matching between the board body and the MCU, the first ends of the N IIC signal paths are connected to a DC voltage V1 through a pull-up resistor, and V1 is The reference voltage of the IIC interface of the MCU; In order to achieve level matching between the board and the IIC load, the second end of the N IIC signal paths is connected to a DC voltage V2 through a pull-up resistor, and V2 is the reference voltage of the IIC interface at the load end. 7. The IIC interface expansion board according to claim 6, wherein V1 is 3.3V. 8. The IIC interface expansion board according to claim 6, wherein V2 is 12V. 9. The IIC interface expansion board according to claim 1, wherein the board body is a PCB board.