WO2014201717A1 - 主动矩阵显示装置、扫描驱动电路及其扫描驱动方法 - Google Patents

主动矩阵显示装置、扫描驱动电路及其扫描驱动方法 Download PDF

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WO2014201717A1
WO2014201717A1 PCT/CN2013/078269 CN2013078269W WO2014201717A1 WO 2014201717 A1 WO2014201717 A1 WO 2014201717A1 CN 2013078269 W CN2013078269 W CN 2013078269W WO 2014201717 A1 WO2014201717 A1 WO 2014201717A1
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signal
pulse signal
delay
scan driving
active matrix
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English (en)
French (fr)
Inventor
郭东胜
秦红江
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to GB1522336.5A priority Critical patent/GB2533046B/en
Priority to KR1020167000272A priority patent/KR101789943B1/ko
Priority to JP2016520230A priority patent/JP2016526700A/ja
Priority to RU2016101270A priority patent/RU2620497C1/ru
Priority to US13/985,290 priority patent/US20140375614A1/en
Publication of WO2014201717A1 publication Critical patent/WO2014201717A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit, an active matrix display device, and a scan driving method thereof.
  • FIG. 1 is a schematic diagram of a waveform of a prior art scan driver. As shown in FIG.
  • the start pulse signal STV is used to control the start of the first line
  • the clock pulse signal CKV is used to control the switching frequency of each line, which starts to operate when the rising edge of the start pulse signal STV is detected
  • the control signal OE is set between the switching of the row and the line on and off, which can forcibly pull the output voltage low when it is high. Therefore, the enable control signal OE can shift the turn-on and turn-off time between rows and rows, avoiding the delay of the scan signal due to the presence of parasitic capacitance, thereby causing overlapping and overlapping of adjacent two rows. .
  • the foregoing three control signals are generated by the timing control chip and transmitted to the glass substrate via the flexible circuit board of the data driving chip, and then transmitted to the scanning driving chip by the glass substrate. Therefore, it is necessary to provide three transmission lines on the glass substrate to realize transmission.
  • the design difficulty of the active matrix display device (especially the active frame display device with a narrow bezel) is increased.
  • the output pins of the plurality of timing control chips and the input pins of the scan driver chip need to be correspondingly set, thereby increasing the cost of the chip package.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit, an active matrix display device and a scan driving method thereof for an active matrix display device, which can reduce the number of transmission lines, thereby increasing the spacing of the transmission lines and reducing the design difficulty.
  • the number of output pins of the timing control chip and the input pins of the scan driver chip are reduced, thereby reducing the number of timing control chips and scan drive chips, and reducing the cost of chip packaging.
  • a technical solution adopted by the present invention is to provide a scan driving circuit of an active matrix display device, the scan driving circuit including a delay module, wherein an input end of the delay module receives an initial clock pulse signal and starts The input signal of the pulse signal is integrated, and the input signal is delayed by two parts. After the delay of the first part, the first output end of the delay module outputs an enable control signal, after the delay of the second part The second output end of the delay module outputs a delayed clock pulse signal, wherein the enable control signal and the delayed clock pulse signal are output to the scan line of the active matrix display device.
  • the pulse duration of the start pulse signal is t1
  • the pulse duration of the initial clock signal is t2
  • the period of the initial clock signal is T, wherein t1, t2, and T satisfy the condition: t2 ⁇ t1 ⁇ t2+T.
  • the delay module includes 2n first inverters and 2m second inverters. After the input signals pass through 2n first inverters, an enable control signal is outputted at the first output end, and the input signals pass through. After 2n first inverters and 2m second inverters, a delayed clock pulse signal is outputted at the second output, where n and m are natural numbers.
  • each first inverter is ⁇ tn
  • the delay time of each second inverter is ⁇ tm
  • an active matrix display device including a timing control circuit, a signal integrated circuit, and a scan driving circuit, wherein: the timing control circuit generates an initial clock a pulse signal and a start pulse signal; an input end of the signal integrated circuit is coupled to an output of the timing control circuit for integrating the initial clock pulse signal and the start pulse signal into an input signal; the scan driving circuit includes a delay module, and the delay module The input end is coupled to the output of the signal integrated circuit to receive the input signal, and the input signal is delayed by two parts, wherein after the delay of the first part, the first output end of the delay module outputs an enable control signal After the delay of the second part, the second output end of the delay module outputs a delayed clock pulse signal, wherein the enable control signal and the delayed clock pulse signal are output to the scan line of the active matrix display device.
  • the pulse duration of the start pulse signal is t1
  • the pulse duration of the initial clock signal is t2
  • the period of the initial clock signal is T, where t1, t2 and the condition: t2 ⁇ t1 ⁇ t2+T.
  • the delay module includes 2n first inverters and 2m second inverters. After the input signals pass through 2n first inverters, an enable control signal is outputted at the first output end, and the input signals pass through. After 2n first inverters and 2m second inverters, a delayed clock pulse signal is outputted at the second output, where n and m are natural numbers.
  • each first inverter is ⁇ tn
  • the delay time of each second inverter is ⁇ tm
  • the active matrix display device further includes a scan driving chip, wherein the delay module is disposed inside the scan driving chip.
  • another technical solution adopted by the present invention is to provide a scan driving method for an active matrix display device, the active matrix display device comprising a timing control circuit and a scan driving circuit, the method comprising: a timing control circuit
  • the generated initial clock pulse signal and the start pulse signal are superimposed as an input signal of the scan driving circuit;
  • the scan driving circuit includes a delay module, and the input end of the delay module receives the input signal, and the input signal is delayed by two parts, wherein After the delay of the first part, the first output end of the delay module outputs an enable control signal, and after the delay of the second part, the second output end of the delay module outputs a delayed clock pulse signal, wherein
  • the enable control signal and the delayed clock pulse signal are output to the scan line of the active matrix display device.
  • the pulse duration of the start pulse signal is t1
  • the pulse duration of the initial clock signal is t2
  • the period of the initial clock signal is T, wherein t1, t2, and T satisfy the condition: t2 ⁇ t1 ⁇ t2+T.
  • the delay module includes 2n first inverters and 2m second inverters. After the input signals pass through 2n first inverters, an enable control signal is outputted at the first output end, and the input signals pass through. After 2n first inverters and 2m second inverters, a delayed clock pulse signal is outputted at the second output, where n and m are natural numbers.
  • each first inverter is ⁇ tn
  • the delay time of each second inverter is ⁇ tm
  • the scan driving circuit of the active matrix display device of the present invention is provided with a delay module, which first receives an input integrated by the initial clock pulse signal and the start pulse signal.
  • the signal and the input signal are subjected to two-part delay, wherein after the delay of the first part, the output enable control signal is output, and after the delay of the second part, the delayed clock pulse signal is output, wherein the control signal is enabled and The delayed clock pulse signal is output to the scan line of the active matrix display device.
  • the delay module of the present invention receives the integrated input signal, and only needs to set a transmission line to realize the transmission of the scan control signal.
  • the invention can also reduce the number of output pins of the timing control chip and the input pins of the scan driving chip, thereby reducing the cost of the chip package.
  • FIG. 1 is a schematic diagram of a waveform of a prior art scan driver
  • FIG. 2 is a schematic structural view of an active matrix display device according to a first embodiment of the present invention
  • 3 is a process of integrating the initial clock signal and the start pulse signal of the present invention when a condition is satisfied;
  • FIG. 4 is a schematic structural view of the scan driving circuit shown in FIG. 2;
  • Figure 5 is a waveform diagram of the input signal of the present invention after passing through the delay module
  • FIG. 6 is a waveform diagram of scan driving of an active matrix display device of the present invention.
  • Figure 7 is a process of integration of the initial clock signal and the start pulse signal of the present invention when another condition is satisfied;
  • FIG. 9 is a flow chart showing a scan driving method of an active matrix display device according to a first embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of an active matrix display device according to a first embodiment of the present invention.
  • the active matrix display device 20 of the present invention includes a timing control circuit 21, a signal integrated circuit 22, and a scan driving circuit 23.
  • the timing control circuit 21 generates an initial clock pulse signal CKV and a start pulse signal STV.
  • the input end of the signal integrated circuit 22 is coupled to the output of the timing control circuit 21 for superimposing the initial clock signal CKV and the start pulse signal STV to be integrated into the input signal Vin.
  • the pulse duration of the start pulse signal STV is t1
  • the pulse duration of the initial clock signal CKV is t2
  • the period is T.
  • t1, t2, and T satisfy the condition (1): t2 ⁇ t1 ⁇ T.
  • the scan driving circuit 23 further includes a scan driving chip 231, wherein the scan driving chip 231 includes a delay module 232 (please refer to FIG. 4).
  • FIG. 4 shows a specific implementation of the delay module 232.
  • the delay module 232 is disposed inside the scan driving chip 231.
  • the input of the delay module 232 receives the input signal Vin and delays the input signal Vin by two parts.
  • the first output end of the delay module 232 outputs the enable control signal OE.
  • the second output of the delay module 232 outputs a delay.
  • the enable control signal OE and the delayed clock pulse signal CKV' are output to the scan line of the active matrix display device 20.
  • the delay module 232 includes 2n first inverters 2331 and 2m second inverters 2332.
  • the input signal Vin first operates as the start pulse signal STV' of the scan driving chip 231 at the input end of the delay module 232 to trigger the start of the register of the first row of the active display device 20.
  • the input signal Vin passes through 2n first inverters 2331, outputs an enable control signal OE at the first output terminal, continues to pass through 2m second inverters 2332, and is outputted at the second output.
  • the terminal outputs a delayed clock pulse signal CKV'.
  • n and m are natural numbers.
  • FIG. 5 is a waveform diagram of the input signal of the present invention after passing through the delay module.
  • the delay time of each of the first inverters 2331 is ⁇ tn
  • the delay time of each of the second inverters 2332 is ⁇ tm.
  • ⁇ tn, ⁇ tm, t1 and t2 satisfy the following conditions:
  • t2 ⁇ (2n* ⁇ tn+2m* ⁇ tm) ⁇ T1 causes the start pulse signal STV' to act only on the registers of the first row. Specifically, (2n* ⁇ tn+2m* ⁇ tm) ⁇ T1, so that the first row shift register can be triggered to, t2 ⁇ (2n * ⁇ tn + 2m * ⁇ tm) so that the first row shift register is only triggered once;
  • Condition (3) 0 ⁇ 2m * ⁇ tm ⁇ t2 such that the rising edge of the delayed clock pulse signal CKV' is in the high level of the enable control signal OE.
  • FIG. 6 is a waveform diagram of scan driving of the active matrix display device of the present invention.
  • the start pulse signal STV', the enable control signal OE, and the delayed clock pulse signal CKV' are both high level triggers, wherein when the enable control signal OE is at a high level, the power of all channels is controlled. Ping was forced to pull down.
  • the enable control signal OE When the start pulse signal STV' is at the high level and the delayed clock signal CKV' is also at the high level, since the enable control signal OE is at the high level, the output voltage is forcibly pulled down, so the first line waveform is low. level.
  • the enable control signal OE When the enable control signal OE is in a low state and the delayed clock signal SKV' is still in a high state, a high level signal is output, triggering the register of the first row.
  • the enable control signal OE changes from the low level to the high level state, the output level of the start pulse signal STV' is pulled low.
  • the delay clock pulse signal CKV' has changed from a low level to a high level in the process of starting the output signal level of the pulse signal STV' from a high level to a low level.
  • the trigger output of the next line starts to function, that is, the next line starts to output a high level signal, and so on.
  • the level of the previous row has been pulled low, therefore, Staggered the opening and closing time between the two lines.
  • the waveform of the first row is different from the waveform of the other rows, and cannot be transported to the scanning line, and the waveform of the first row should be discarded.
  • the output terminal connected to the scan line in the first row register corresponding to the start pulse signal STV' may be vacant. Therefore, the output data must be empty one line, that is, the time of T.
  • the integration process of the initial clock pulse signal CKV and the start pulse signal STV is as shown in FIG. 7, and finally the input signal Vin is obtained.
  • the input signal Vin is also not output as the start pulse signal STV' of the scan driving chip 231.
  • the output data is to be empty for two lines, that is, 2T.
  • the present invention integrates the initial clock signal CKV and the start pulse signal STV generated by the timing control circuit 21 into one input signal Vin, and then transmits it to the scan driving chip 231, and only needs to set a corresponding transmission line to implement the input.
  • the transmission of the signal Vin thus reducing the transmission line.
  • the active matrix display device 20 of the present invention further includes a data driving chip 24, a flexible circuit board 25, a glass substrate 26, and a printed circuit board 27.
  • the input signal Vin is first transmitted from the printed circuit board 27 to the flexible circuit board 25 of the data driving chip 24, and then transmitted to the glass substrate 26 by the transmission line on the flexible circuit board 25, and is disposed on the glass substrate 26.
  • a transmission line is transmitted to the scan driving chip 231.
  • the present invention also provides a scan driving method of an active matrix display device, which is described in detail on the basis of the foregoing embodiments. For details, please refer to FIG. 9.
  • the method includes the following steps:
  • Step S1 superimposing the initial clock pulse signal and the start pulse signal generated by the timing control circuit as an input signal of the scan driving circuit.
  • step S1 the period of the initial clock signal is T, the pulse duration is t2, and the pulse duration of the start pulse signal is t1, where t1, t2, and T satisfy the condition: t2 ⁇ t1 ⁇ t2 + T.
  • Step S2 The scan driving circuit comprises a delay module, wherein the input end of the delay module receives the input signal and delays the input signal by two parts, wherein after the delay of the first part, the first output end of the delay module Output enable control signal, after the delay of the second part, the second output end of the delay module outputs a delayed clock pulse signal, wherein the enable control signal and the delayed clock pulse signal are output to the scan of the active matrix display device on-line.
  • the delay module includes 2n first inverters and 2m second inverters.
  • the input signal is used as a start pulse signal of the scan driving chip, and after passing through 2n first inverters, an enable control signal is outputted at the first output end, and the input signal passes through 2n first inverters and 2m seconds.
  • a delayed clock pulse signal is output at the second output, where n and m are natural numbers.
  • the delay time of each first inverter is ⁇ tn
  • the delay time of each second inverter is ⁇ tm, where: t2 ⁇ (2nn+2m* ⁇ tm) ⁇ t1, So that the start pulse signal only acts on the register of the first row, specifically, (2n* ⁇ tn+2m* ⁇ tm) ⁇ T1, so that the first row shift register can be triggered, and t2 ⁇ (2n* ⁇ tn+2m* ⁇ tm) causes the first row shift register to be triggered only once. 0 ⁇ 2m* ⁇ tm ⁇ t2, such that the rising edge of the delayed clock pulse signal CKV' is in the high level of the enable control signal OE.
  • the active matrix display device of the present invention first generates an initial clock pulse signal and a start pulse signal by the timing control circuit, and then integrates the initial clock pulse signal and the start pulse signal into an input signal by the signal integrated circuit, and inputs the signal to the scan.
  • the input end of the delay module of the driving chip, the delay module further delays the input signal by two parts, wherein after the delay of the first part, the output enable control signal is output, and after the delay of the second part, the output delay
  • the clock pulse signal, wherein the enable control signal and the delayed clock pulse signal are output to a scan line of the active matrix display device.
  • the delay module of the present invention receives an integrated input signal, which reduces the number of transmission lines on the one hand, and is more advantageous for designing a narrow bezel; on the other hand, increases the transmission line provided on the flexible circuit board.
  • the spacing, thereby reducing the difficulty of bonding in addition, the present invention can also reduce the number of output pins of the timing control chip and the input pins of the scan driving chip, thereby reducing the cost of the chip package.

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Abstract

一种主动矩阵显示装置（20）、扫描驱动电路（23）及其扫描驱动方法。扫描驱动电路（23）包括延时模块（232），延时模块（232）的输入端接收初始时钟脉冲信号（CKV）和开始脉冲信号（STV）集成的输入信号（Vin），并将输入信号（Vin）进行两部分延时，使得第一输出端输出使能控制信号（OE），第二输出端输出延时时钟脉冲信号（CKV）。通过上述方式，能够减小传输线的数量，同时减少时序控制芯片（21）的输出引脚和扫描驱动芯片（231）的输入引脚的数量，从而降低芯片封装成本。

Description

主动矩阵显示装置、扫描驱动电路及其扫描驱动方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种主动矩阵显示装置的扫描驱动电路、主动矩阵显示装置及其扫描驱动方法。
【背景技术】
目前，扫描驱动芯片的控制信号有3个，其用于控制主动矩阵显示装置的每一行的开启和关闭，其分别是开始脉冲信号（start voltage pulse，STV）、时钟脉冲信号（clock voltage pulse，CKV）和使能控制信号（output enable，OE）。请参阅图1，图1是现有技术的扫描驱动的波形示意图。如图1所示，开始脉冲信号STV用于控制第一行的开始，时钟脉冲信号CKV用于控制每一行的开关频率，其在侦测到开始脉冲信号STV的上升沿时开始动作，使能控制信号OE设置在行与行的开启和关闭的切换之间，其在高电平时可将输出电压强制拉低。因此，使能控制信号OE可使得行与行之间的开启和关闭的时间错开，避免了因存在寄生电容而使扫描信号延迟，从而导致相邻的两行有交叠的开启和关闭的问题。
前述的3个控制信号是由时序控制芯片产生，并经数据驱动芯片的软性电路板传输到玻璃基板，再由玻璃基板传输到扫描驱动芯片，因此需要在玻璃基板上设置3根传输线才能实现传输。
由于需要设置多根传输线，增加了主动矩阵显示装置（特别是窄边框的主动矩阵显示装置）的设计难度。
同时，数据驱动芯片的软性电路板上设置多根传输线时，传输线的间距较小，增加邦定（bonding）难度。
此外，多根传输线在封装时，需要相应设置多个时序控制芯片的输出引脚和扫描驱动芯片的输入引脚，因此提高芯片封装的成本。
【发明内容】
本发明主要解决的技术问题是提供一种主动矩阵显示装置的扫描驱动电路、主动矩阵显示装置及其扫描驱动方法，能够减小传输线的数量，从而增大传输线的间距，降低设计难度，同时也减少了时序控制芯片的输出引脚和扫描驱动芯片的输入引脚的数量，从而减少时序控制芯片和扫描驱动芯片的数量，降低芯片封装成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种主动矩阵显示装置的扫描驱动电路，该扫描驱动电路包括延时模块，延时模块的输入端接收由初始时钟脉冲信号和开始脉冲信号集成的输入信号，并将输入信号进行两部分延时，其中，在经过第一部分的延时后，延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，延时模块的第二输出端输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出至主动矩阵显示装置的扫描线上。
其中，开始脉冲信号的脉冲时长为t1，初始时钟脉冲信号的脉冲时长为t2，初始时钟脉冲信号的周期为T，其中，t1、t2以及T满足条件：t2<t1≤t2+T。
其中，t1、t2以及T满足条件：t2<t1<T。
其中，t1、t2以及T满足条件：T≤t1≤t2+T。
其中，延时模块包括2n个第一反相器和2m个第二反相器，其中，输入信号经过2n个第一反相器后，在第一输出端输出使能控制信号，输入信号经过2n个第一反相器和2m个第二反相器后，在第二输出端输出延时时钟脉冲信号，其中，n和m为自然数。
其中，每个第一反相器的延时时间为∆tn，每个第二反相器的延时时间为∆tm，其中：
t2<（2n*∆tn+2m*∆tm）<t1
0<2m*∆tm<t2。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种主动矩阵显示装置，该主动矩阵显示装置包括时序控制电路、信号集成电路以及扫描驱动电路，其中：时序控制电路产生初始时钟脉冲信号以及开始脉冲信号；信号集成电路的输入端耦接于时序控制电路的输出，用于将初始时钟脉冲信号以及开始脉冲信号集成为输入信号；扫描驱动电路包括延时模块，延时模块的输入端耦接于信号集成电路的输出，以接收输入信号，并将输入信号进行两部分延时，其中，在经过第一部分的延时后，延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，延时模块的第二输出端输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出至主动矩阵显示装置的扫描线上。
其中，开始脉冲信号的脉冲时长为t1，初始时钟脉冲信号的脉冲时长为t2，初始时钟脉冲信号的周期为T，其中，t1、t2以及满足条件：t2<t1≤t2+T。
其中，t1、t2以及T满足条件：t2<t1<T。
其中，t1、t2以及T满足条件：T≤t1≤t2+T。
其中，延时模块包括2n个第一反相器和2m个第二反相器，其中，输入信号经过2n个第一反相器后，在第一输出端输出使能控制信号，输入信号经过2n个第一反相器和2m个第二反相器后，在第二输出端输出延时时钟脉冲信号，其中，n和m为自然数。
其中，每个第一反相器的延时时间为∆tn，每个第二反相器的延时时间为∆tm，其中：
t2<（2nn+2m*∆tm）<t1
0<2m*∆tm<t2。
其中，主动矩阵显示装置还包括扫描驱动芯片，其中，延时模块设置在扫描驱动芯片的内部。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种主动矩阵显示装置的扫描驱动方法，该主动矩阵显示装置包括时序控制电路和扫描驱动电路，该方法包括：将时序控制电路产生的初始时钟脉冲信号以及开始脉冲信号进行叠加，作为扫描驱动电路的输入信号；扫描驱动电路包括延时模块，延时模块的输入端接收输入信号，并将输入信号进行两部分延时，其中，在经过第一部分的延时后，延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，延时模块的第二输出端输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出到主动矩阵显示装置的扫描线上。
其中，开始脉冲信号的脉冲时长为t1，初始时钟脉冲信号的脉冲时长为t2，初始时钟脉冲信号的周期为T，其中，t1、t2以及T满足条件：t2<t1≤t2+T。
其中，t1、t2以及T满足条件：t2<t1<T。
其中，t1、t2以及T满足条件：T≤t1≤t2+T。
其中，延时模块包括2n个第一反相器和2m个第二反相器，其中，输入信号经过2n个第一反相器后，在第一输出端输出使能控制信号，输入信号经过2n个第一反相器和2m个第二反相器后，在第二输出端输出延时时钟脉冲信号，其中，n和m为自然数。
其中，每个第一反相器的延时时间为∆tn，每个第二反相器的延时时间为∆tm，其中：
t2<（2n*∆tn+2m*∆tm）<t1
0<2m*∆tm<t2。
本发明的有益效果是：区别于现有技术的情况，本发明的主动矩阵显示装置的扫描驱动电路设置有延时模块，该延时模块首先接收由初始时钟脉冲信号和开始脉冲信号集成的输入信号，并将输入信号进行两部分延时，其中，在经过第一部分的延时后输出使能控制信号，经过第二部分的延时后输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出至主动矩阵显示装置的扫描线上。通过上述方式，本发明延时模块接收的是集成的输入信号，只需要相应设置一根传输线即可实现扫描控制信号的传输，一方面减少了传输线的数量，更有利于实现窄边框的设计；另一方面，增大了软性电路板上设置的传输线的间距，从而降低了邦定的难度。此外，本发明还可减少时序控制芯片的输出引脚和扫描驱动芯片的输入引脚的数量，降低了芯片封装成本。
【附图说明】
图1是现有技术的扫描驱动的波形示意图；
图2是本发明第一实施例的主动矩阵显示装置的结构示意图；
图3是本发明的初始时钟脉冲信号和开始脉冲信号满足一种条件时集成的过程；
图4是图2所示的扫描驱动电路的结构示意图；
图5是本发明的输入信号经过延时模块后的波形图；
图6是本发明主动矩阵显示装置的扫描驱动的一种波形图；
图7是本发明的初始时钟脉冲信号和开始脉冲信号满足另一种条件时集成的过程；
图8是本发明主动矩阵显示装置的扫描驱动的另一种波形图；
图9是本发明第一实施例的主动矩阵显示装置的扫描驱动方法的流程图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细的说明。
请参阅图2，图2是本发明第一实施例的主动矩阵显示装置的结构示意图。如图2所示，本发明的主动矩阵显示装置20包括时序控制电路21、信号集成电路22以及扫描驱动电路23。
其中，时序控制电路21产生初始时钟脉冲信号CKV以及开始脉冲信号STV。
信号集成电路22的输入端耦接于时序控制电路21的输出，用于将初始时钟脉冲信号CKV以及开始脉冲信号STV进行叠加，以集成为输入信号Vin，具体过程请一起参阅图3，图3是本发明的初始时钟脉冲信号和开始脉冲信号集成的过程。如图3所示，开始脉冲信号STV的脉冲时长为t1，初始时钟脉冲信号CKV的脉冲时长为t2，周期为T，本实施例中，t1、t2和T满足条件（1）：t2<t1<T。
扫描驱动电路23还包括扫描驱动芯片231，其中，扫描驱动芯片231包括延时模块232（请配合参阅图4所示）。
图4显示延时模块232的一种具体实施结构。如图4所示，延时模块232设置在扫描驱动芯片231的内部。延时模块232的输入端接收输入信号Vin，并将输入信号Vin进行两部分延时。其中，在经过第一部分233的延时后，延时模块232的第一输出端输出使能控制信号OE，经过第二部分234的延时后，延时模块232的第二输出端输出延时时钟脉冲信号CKV＇。其中，使能控制信号OE和延时时钟脉冲信号CKV＇输出至主动矩阵显示装置20的扫描线上。
具体而言，延时模块232包括2n个第一反相器2331和2m个第二反相器2332。其中，输入信号Vin首先在延时模块232的输入端作为扫描驱动芯片231的开始脉冲信号STV＇工作，以触发主动显示装置20的第一行的寄存器的开始。输入信号Vin在进入延时模块232内后，经过2n个第一反相器2331，在第一输出端输出使能控制信号OE，继续经过2m个第二反相器2332后，在第二输出端输出延时时钟脉冲信号CKV＇。本实施例中，n和m为自然数。
请一并参阅图5，图5是本发明的输入信号经过延时模块后的波形图。本实施例中，每个第一反相器2331的延时时间为∆tn，每个第二反相器2332的延时时间为∆tm。其中，∆tn、∆tm、t1和t2满足以下条件：
条件（2）：t2<（2n*∆tn+2m*∆tm）< t1，使得开始脉冲信号STV＇只作用于第一行的寄存器。具体而言，（2n*∆tn+2m*∆tm）< t1，使得第一行移位寄存器能被触发到，t2<（2n*∆tn+2m*∆tm）使得第一行移位寄存器只被触发一次；
条件（3）：0<2m*∆tm<t2，使得延时时钟脉冲信号CKV＇的上升沿处于使能控制信号OE的高电平中。
具体工作原理请参阅图6，图6是本发明主动矩阵显示装置的扫描驱动的波形图。如图6所示，开始脉冲信号STV＇、使能控制信号OE以及延时时钟脉冲信号CKV＇都是高电平触发，其中，当使能控制信号OE为高电平时，控制所有通道的电平被强制拉低。
在开始脉冲信号STV＇处于高电平和延时时钟脉冲信号CKV＇同样处于高电平时，因为使能控制信号OE为高电平，强制拉低输出电压，所以此时第一行波形为低电平。当使能控制信号OE处于低电平状态，而延时时钟脉冲信号SKV＇仍处于高电平状态时，输出高电平信号，触发第一行的寄存器。使能控制信号OE由低电平变成高电平状态时，开始脉冲信号STV＇的输出电平被拉低。在开始脉冲信号STV＇的输出电平从高电平拉低到低电平的过程中，延时时钟脉冲信号CKV＇已从低电平变成高电平。因此，在此过程中，使能控制信号OE从高电平变到低电平时，下一行的触发输出开始作用，即下一行开始输出高电平信号，以此类推。本实施例中，由于延时时钟脉冲信号CKV＇的上升沿处于使能控制信号OE的高电平中，使得下一行的触发输出开始作用时，上一行的电平已被拉低，因此，错开了两行之间的开启与关闭的时间。
由图6可知，第一行的波形与其他行的波形不同，不能将其输送到扫描线上，第一行的波形应舍掉。本实施例中，可将开始脉冲信号STV＇对应的第一行寄存器中连接扫描线的输出端空置。因此，输出数据要空一行，即T的时间。
在其他实施例中，在前述的条件（2）—（3）不变的情况下，若t1、t2和T满足条件： T ≤ t1≤ t2+T。则初始时钟脉冲信号CKV和开始脉冲信号STV的集成过程如图7所示，最终得到输入信号Vin。输入信号Vin作为扫描驱动芯片231的开始脉冲信号STV＇同样不输出，如图8所示，输出数据要空两行，即2T的时间。
综上，本发明通过对时序控制电路21产生的初始时钟脉冲信号CKV以及开始脉冲信号STV集成为一个输入信号Vin，然后再传输到扫描驱动芯片231中，只需设置一条相应的传输线来实现输入信号Vin的传输，因此减少了传输线。具体而言，请再参阅图2，本发明的主动矩阵显示装置20还包括数据驱动芯片24、软性电路板25、玻璃基板26以及印刷电路板27。其中，输入信号Vin首先由印刷电路板27传输到数据驱动芯片24的软性电路板25上，再由软性电路板25上的传输线传输到玻璃基板26上，并通过设置在玻璃基板26上的一条传输线传输给扫描驱动芯片231。
本发明还提供了一种主动矩阵显示装置的扫描驱动方法，其在前述实施例的基础上进行详述。具体请参阅图9，该方法包括以下步骤：
步骤S1：将时序控制电路产生的初始时钟脉冲信号以及开始脉冲信号进行叠加，作为扫描驱动电路的输入信号。
在步骤S1中，初始时钟脉冲信号的周期为T，脉冲时长为t2，开始脉冲信号的脉冲时长为t1，其中，t1、t2和T满足条件：t2<t1≤t2+T。
其中，当t2<t1<T时，叠加过程如图3所示。当T≤t1≤t2+T时，叠加过程如图7所示。
步骤S2：扫描驱动电路包括延时模块，延时模块的输入端接收输入信号，并将输入信号进行两部分延时，其中，在经过第一部分的延时后，延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，延时模块的第二输出端输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出到主动矩阵显示装置的扫描线上。
在步骤S2中，延时模块包括2n个第一反相器和2m个第二反相器。其中，输入信号作为扫描驱动芯片的开始脉冲信号，其经过2n个第一反相器后，在第一输出端输出使能控制信号，输入信号经过2n个第一反相器和2m个第二反相器后，在第二输出端输出延时时钟脉冲信号，其中，n和m为自然数。
本实施例中，每个第一反相器的延时时间为∆tn，每个第二反相器的延时时间为∆tm，其中：t2<（2nn+2m*∆tm）<t1，使得开始脉冲信号只作用于第一行的寄存器，具体而言，（2n*∆tn+2m*∆tm）< t1，使得第一行移位寄存器能被触发到，t2<（2n*∆tn+2m*∆tm）使得第一行移位寄存器只被触发一次。0<2m*∆tm<t2，使得延时时钟脉冲信号CKV＇的上升沿处于使能控制信号OE的高电平中。
其中，当t2<t1<T时，第一行的输出波形如图6所示。在T≤t1≤t2+T时，则第一行的输出波形如图8所示。
综上所述，本发明的主动矩阵显示装置首先由时序控制电路产生初始时钟脉冲信号和开始脉冲信号，然后由信号集成电路将初始时钟脉冲信号和开始脉冲信号集成为输入信号，并输入到扫描驱动芯片的延时模块的输入端，延时模块进一步将输入信号进行两部分延时，其中，在经过第一部分的延时后输出使能控制信号，经过第二部分的延时后输出延时时钟脉冲信号，其中，使能控制信号和延时时钟脉冲信号输出至主动矩阵显示装置的扫描线上。通过上述方式，本发明延时模块接收的是集成的输入信号，一方面减少了传输线的数量，更有利于实现窄边框的设计；另一方面，增大了软性电路板上设置的传输线的间距，从而降低了邦定的难度，此外，本发明还可减少时序控制芯片的输出引脚和扫描驱动芯片的输入引脚的数量，从而降低了芯片封装成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种主动矩阵显示装置的扫描驱动电路，其中，所述扫描驱动电路包括延时模块，所述延时模块的输入端接收由初始时钟脉冲信号和开始脉冲信号集成的输入信号，并将所述输入信号进行两部分延时，其中，在经过第一部分的延时后，所述延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，所述延时模块的第二输出端输出延时时钟脉冲信号，其中，所述使能控制信号和所述延时时钟脉冲信号输出至所述主动矩阵显示装置的扫描线上。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述开始脉冲信号的脉冲时长为t1，所述初始时钟脉冲信号的脉冲时长为t2，所述初始时钟脉冲信号的周期为T，其中，所述t1、t2以及T满足条件：t2<t1≤t2+T。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述t1、t2以及T满足条件：t2<t1<T。
  4. 根据权利要求2所述的扫描驱动电路，其中，所述t1、t2以及T满足条件：T≤t1≤t2+T。
  5. 根据权利要求2所述的扫描驱动电路，其中，所述延时模块包括2n个第一反相器和2m个第二反相器，其中，所述输入信号经过2n个所述第一反相器后，在所述第一输出端输出所述使能控制信号，所述输入信号经过2n个所述第一反相器和2m个所述第二反相器后，在所述第二输出端输出所述延时时钟脉冲信号，其中，所述n和m为自然数。
  6. 根据权利要求5所述的扫描驱动电路，其中，每个所述第一反相器的延时时间为∆tn，每个所述第二反相器的延时时间为∆tm，其中：
    t2<（2n*∆tn+2m*∆tm）< t1
    0<2m*∆tm<t2。
  7. 一种主动矩阵显示装置，其中，所述主动矩阵显示装置包括时序控制电路、信号集成电路以及扫描驱动电路，其中：
    所述时序控制电路产生初始时钟脉冲信号以及开始脉冲信号；
    所述信号集成电路的输入端耦接于所述时序控制电路的输出，用于将所述初始时钟脉冲信号以及所述开始脉冲信号集成为输入信号；
    所述扫描驱动电路包括延时模块，所述延时模块的输入端耦接于所述信号集成电路的输出，以接收所述输入信号，并将所述输入信号进行两部分延时，其中，在经过第一部分的延时后，所述延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，所述延时模块的第二输出端输出延时时钟脉冲信号，其中，所述使能控制信号和所述延时时钟脉冲信号输出至所述主动矩阵显示装置的扫描线上。
  8. 根据权利要求7所述的主动矩阵显示装置，其中，所述开始脉冲信号的脉冲时长为t1，所述初始时钟脉冲信号的脉冲时长为t2，所述初始时钟脉冲信号的周期为T，其中，所述t1、t2以及T满足条件：t2<t1≤t2+T。
  9. 根据权利要求8所述的主动矩阵显示装置，其中，所述t1、t2以及T满足条件：t2<t1<T。
  10. 根据权利要求8所述的主动矩阵显示装置，其中，所述t1、t2以及T满足条件：T≤t1≤t2+T。
  11. 根据权利要求8所述的主动矩阵显示装置，其中，所述延时模块包括2n个第一反相器和2m个第二反相器，其中，所述输入信号经过2n个所述第一反相器后，在所述第一输出端输出所述使能控制信号，所述输入信号经过2n个所述第一反相器和2m个所述第二反相器后，在所述第二输出端输出所述延时时钟脉冲信号，其中，所述n和m为自然数。
  12. 根据权利要求11所述的主动矩阵显示装置，其中，每个所述第一反相器的延时时间为∆tn，每个所述第二反相器的延时时间为∆tm，其中：
    t2<（2n*∆tn+2m*∆tm）<t1
    0<2m*∆tm<t2。
  13. 根据权利要求7所述的主动矩阵显示装置，其中，所述主动矩阵显示装置还包括扫描驱动芯片，其中，所述延时模块设置在所述扫描驱动芯片的内部。
  14. 一种主动矩阵显示装置的扫描驱动方法，所述主动矩阵显示装置包括时序控制电路和扫描驱动电路，其中，所述方法包括：
    将所述时序控制电路产生的初始时钟脉冲信号以及开始脉冲信号进行叠加，作为所述扫描驱动电路的输入信号；
    所述扫描驱动电路包括延时模块，所述延时模块的输入端接收所述输入信号，并将所述输入信号进行两部分延时，其中，在经过第一部分的延时后，所述延时模块的第一输出端输出使能控制信号，经过第二部分的延时后，所述延时模块的第二输出端输出延时时钟脉冲信号，其中，所述使能控制信号和所述延时时钟脉冲信号输出到所述主动矩阵显示装置的扫描线上。
  15. 根据权利要求14所述的扫描驱动方法，其中，所述开始脉冲信号的脉冲时长为t1，所述初始时钟脉冲信号的脉冲时长为t2，所述初始时钟脉冲信号的周期为T，其中，所述t1、t2以及T满足条件：t2<t1≤t2+T。
  16. 根据权利要求15所述的扫描驱动方法，其中，所述t1、t2以及T满足条件：t2<t1<T。
  17. 根据权利要求15所述的扫描驱动方法，其中，所述t1、t2以及T满足条件：T≤t1≤t2+T。
  18. 根据权利要求15所述的扫描驱动方法，其中，所述延时模块包括2n个第一反相器和2m个第二反相器，其中，所述输入信号经过2n个所述第一反相器后，在所述第一输出端输出所述使能控制信号，所述输入信号经过2n个所述第一反相器和2m个所述第二反相器后，在所述第二输出端输出所述延时时钟脉冲信号，其中，所述n和m为自然数。
  19. 根据权利要求18所述的扫描驱动方法，其中，每个所述第一反相器的延时时间为∆tn，每个所述第二反相器的延时时间为∆tm，其中：
    t2<（2n*∆tn+2m*∆tm）< t1
    0<2m*∆tm<t2。
PCT/CN2013/078269 2013-06-20 2013-06-28 主动矩阵显示装置、扫描驱动电路及其扫描驱动方法 Ceased WO2014201717A1 (zh)

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