WO2014200044A1 - インバータ装置 - Google Patents

インバータ装置 Download PDF

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Publication number
WO2014200044A1
WO2014200044A1 PCT/JP2014/065531 JP2014065531W WO2014200044A1 WO 2014200044 A1 WO2014200044 A1 WO 2014200044A1 JP 2014065531 W JP2014065531 W JP 2014065531W WO 2014200044 A1 WO2014200044 A1 WO 2014200044A1
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Prior art keywords
level circuit
switch elements
level
output voltage
circuit
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PCT/JP2014/065531
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English (en)
French (fr)
Japanese (ja)
Inventor
馬躍
辻仁司
植木浩一
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株式会社村田製作所
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Priority to JP2015522845A priority Critical patent/JP5843052B2/ja
Priority to DE112014002806.1T priority patent/DE112014002806T5/de
Publication of WO2014200044A1 publication Critical patent/WO2014200044A1/ja

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Definitions

  • the present invention relates to a DC / AC inverter device, and more particularly to an inverter device provided with a multilevel circuit.
  • Patent Document 1 a series circuit of four capacitors and a series circuit of eight switch elements are provided between the positive and negative terminals of a DC power source, and a switch is connected between the connection point of these capacitors and the connection point of the switch elements.
  • a configuration of a five-level inverter in which elements or diodes are connected is disclosed.
  • a multi-level circuit requires at least 2 (n-1) switch elements, where n is the number of levels.
  • n is the number of levels.
  • n is the number of levels.
  • a total of 10 switch elements are used.
  • an object of the present invention is to provide an inverter device capable of obtaining a high-order level output without increasing the number of switch elements.
  • the present invention has a plurality of switch elements connected in series to two terminals to which a DC voltage is input, outputs an n-level potential by switching each of the plurality of switch elements, and is connected in series.
  • a first multi-level circuit and a bridge circuit connected to the first multi-level circuit and inverting the polarity of the n-level potential output from the first multi-level circuit;
  • at least one inductor that generates a smoothing action, the plurality of switch elements included in the first multilevel circuit, and the plurality of switch elements included in the second multilevel circuit.
  • a switching control circuit that performs switching control with a phase difference of (n-1).
  • a high-order level inverter device can be realized with a small number of switch elements by controlling the switching of two multi-level circuits with a phase difference. For example, when a multi-level circuit outputs a three-level voltage (potential), switching control of the switch elements of the two multi-level circuits with a phase difference of 90 degrees can generate a 5-level potential. By inverting the polarity of the output voltage, a 9-level voltage can be output.
  • the polarity of the output from the multi-level circuit is inverted by the bridge circuit, and a sine wave current is output to the connected system. Switching control is performed. Therefore, the inverter device performs PWM control of the switch element at, for example, a carrier frequency of 20 kHz, while switching control of the subsequent-stage switch element at 50 Hz or 60 Hz. As a result, switching loss can be reduced.
  • the inductor is preferably provided on the input side or output side of the bridge circuit.
  • the multilevel circuit includes first, second, third, and fourth switch elements connected in series between a first input terminal to which a DC voltage is input and a second input terminal, and the first switch A floating capacitor having a first end connected to a connection point between an element and the second switch element, and a second end connected to a connection point between the third switch element and the fourth switch element; It is preferable.
  • a single polarity DC voltage can be input to generate an intermediate voltage without loss.
  • a high-order level inverter device can be realized with a small number of switch elements. Moreover, the inverter apparatus which can reduce switching loss is realizable.
  • Circuit diagram of inverter device The figure which shows the relationship between the state of four switch elements of a 1st 3 level circuit, and output voltage (potential). 2 is an equivalent circuit diagram of the first three-level circuit in the four states shown in FIG.
  • the switch elements of the first three-level circuit and the second three-level circuit have an on-duty ratio of 12.5%
  • the output voltage of the first three-level circuit, the output voltage of the second three-level circuit Of the output voltage of the terminal UW
  • the switch elements of the first three-level circuit and the second three-level circuit have an on-duty ratio of 12.5%
  • the output voltage of the first three-level circuit, the output voltage of the second three-level circuit Of the output voltage of the terminal UW
  • FIG. 1 is a circuit diagram of an inverter device according to this embodiment. This embodiment will be described as a 9-level inverter device.
  • the inverter device 101 includes a first input terminal IN1 and a second input terminal IN2 connected to a DC power supply, and a first output terminal OUT1 and a second output terminal OUT2 that output an AC voltage. .
  • a boosted DC voltage generated by a photovoltaic power generation panel is applied to the first input terminal IN1 and the second input terminal IN2.
  • a single-phase three-wire AC voltage is output together with the neutral line NP.
  • the output voltage is 200 Vrms, injection is performed in connection with a single-phase three-wire distribution line.
  • Su and Sw represent a single-phase three-wire system having a U phase and a W phase.
  • An AC voltage having an effective voltage of 100V is output from between the first output terminal OUT1 and the neutral point NP, and an AC voltage having an effective voltage of 100V is output from between the neutral point NP and the second output terminal OUT2.
  • An AC voltage having an effective voltage of 200 V is output between the first output terminal OUT1 and the second output terminal OUT2.
  • Input capacitors C1 and C2 are connected between the first input terminal IN1 and the ground and between the second input terminal IN2 and the ground, respectively.
  • the first three-level circuit 10 is connected between the first input terminal IN1 and the ground
  • the second three-level circuit 20 is connected between the second input terminal IN2 and the ground.
  • the first three-level circuit 10 includes first to fourth switch elements SP1 to SP4, a first switch element SP1 and a second switch element SP2 connected in series between the first input terminal IN1 and the ground. And a floating capacitor Cf1 having a second end connected to a connection point between the third switch element SP3 and the fourth switch element SP4.
  • the second three-level circuit 20 includes the first to fourth switch elements SM1 to SM4, the first switch element SM1 and the second switch connected in series between the second input terminal IN2 and the ground.
  • the floating capacitor Cf2 has a first end connected to the connection point with the element SM2, and a second capacitor connected to the connection point between the third switch element SM3 and the fourth switch element SM4.
  • the switching elements SP1 to SP4 of the first three-level circuit 10 and the switching elements SM1 to SM4 of the second three-level circuit 20 are supplied with a drive signal by the switching control circuit 40 and are subjected to switching control.
  • Both the first three-level circuit 10 and the second three-level circuit 20 output a potential within the range of the input H (high) side potential to the L (low) side potential.
  • Vin is applied to the first input terminal IN1
  • ⁇ Vin is applied to the second input terminal IN2. Therefore, the first three-level circuit 10 has an Vin (H) side potential of Vin and an L (Low) side potential of 0, so the potential of the output terminal VP of the first three-level circuit 10 is Vin. It takes a range of ⁇ 0.
  • the second (three) level circuit 20 has an H (high) side potential of 0 and an L (low) side potential of ⁇ Vin, the potential of the output terminal VM of the second three level circuit 20 is The range is 0 to -Vin.
  • the potential of the output terminal of the first three-level circuit 10 will be described by taking the first three-level circuit 10 as an example. Since the second three-level circuit 20 can be described in the same manner as the first three-level circuit 10, the description thereof is omitted.
  • FIG. 2 is a diagram showing the relationship between the states of the four switch elements SP1 to SP4 of the first three-level circuit 10 and the output voltage (potential) VP.
  • the four switch elements SP1 to SP4 adopt four states H, Mc, Md, and L.
  • FIG. 3 is an equivalent circuit diagram of the first three-level circuit 10 in the four states shown in FIG.
  • the output voltage VP Vin.
  • the output voltage VP Vin ⁇ Vc.
  • the output voltage VP Vin / 2.
  • the output voltage VP in the state Mc and the output voltage VP in the state Md are equal. That is, the charging voltage Vc of the floating capacitor Cf1 is charged / discharged with an average of Vin / 2 which is 1/2 of Vin. If the charging / discharging time constant for the floating capacitor Cf1 is sufficiently large with respect to the switching frequency, the fluctuation range of the charging voltage Vc is small and can be regarded as Vc ⁇ Vin / 2.
  • the first three-level circuit 10 can output Vin / 2 that is an intermediate voltage of Vin by providing the floating capacitor Cf1, and can output three voltage levels of 0, Vin / 2, and Vin. Can do.
  • the second three-level circuit 20 to which ⁇ Vin is applied can output three voltage levels of 0, ⁇ Vin / 2, and ⁇ Vin.
  • a bridge circuit 30 is connected to the output side of the first three-level circuit 10 and the second three-level circuit 20.
  • the bridge circuit 30 includes first to fourth rear-stage switch elements SB1 to SB4 that are bridge-connected to the first to fourth terminals S, T, U, and W.
  • the first terminal S is connected to the connection point between the second switch element SP2 and the third switch element SP3, and the second terminal T is connected to the connection point between the second switch element SM2 and the third switch element SM3. Is connected.
  • the third terminal U is connected to a connection point between the first switch element SB1 and the second switch element SB2, and a fourth point is connected to the connection point between the third switch element SB3 and the fourth switch element SB4. Terminal W is connected.
  • the bridge circuit 30 connects the output of the first three-level circuit 10 to the first output terminal OUT1 via the inductor L1, and connects the output of the second three-level circuit 20 to the second output via the inductor L2.
  • the first state corresponds to the first half cycle of the power supply frequency of the system
  • the second state corresponds to the second half cycle of the power supply frequency of the system.
  • the first inductor L1 and the second inductor L2 may be provided on the input side of the bridge circuit 30, that is, between the three-level circuits 10 and 20 and the bridge circuit 30.
  • the switch elements SP1 to SP4, the switch elements SM1 to SM4, and the switch elements SB1 to SB4 are all MOS-FETs, and FIG. 1 also shows a body diode. Since the three-level circuits 10 and 20 are connected in series, a low-breakdown-voltage switch element can be used for each of the switch elements SP1 to SP4 and the switch elements SM1 to SM4. Therefore, the switch elements SP1 to SP4 and the switch elements SM1 to SM4 can be configured by MOS-FETs instead of IGBTs (Insulated Gate Gate Bipolar Transistors).
  • IGBTs Insulated Gate Gate Bipolar Transistors
  • the first three-level circuit 10 outputs three voltage levels of 0, Vin / 2, and Vin
  • the second three-level circuit 20 similarly outputs 0, ⁇ Vin / 2, ⁇ Vin.
  • the three voltage levels are output. If the first three-level circuit 10 and the second three-level circuit 20 are operated in the same phase, the bridge circuit 30 switches between the first state and the second state described above (polarity inversion),
  • the inverter device 101 outputs five levels of voltage.
  • the inverter device 101 outputs a 9-level voltage by operating the first 3-level circuit 10 and the second 3-level circuit 20 by PWM control using a carrier wave having a phase difference of 90 degrees. be able to.
  • the phase difference of 90 degrees is obtained by substituting “3” of the three-level circuit for n in the relationship of 360 ° / 2 (n ⁇ 1). That is, the inverter device 101 can output a high-order level voltage without increasing the number of switching elements in the case of five levels, and can avoid an increase in size and an increase in switching loss due to an increase in the number of switching elements. .
  • the switch elements SP1 to SP4 and SM1 to SM4 are PWM-controlled at a carrier frequency of 20 kHz, for example, so that the output from the three-level inverter circuits 10 and 20 is a half wave of a sine wave of current injected into the system.
  • the switch elements SB1 to SB4 of the bridge circuit 30 invert the polarity of the output from the three-level circuits 10 and 20 in the first half cycle and the second half cycle of the power supply frequency (50 Hz or 60 Hz) of the system. That is, the switching frequency of the switch elements SB1 to SB4 of the bridge circuit 30 is lower than the switching frequency of the switch elements SP1 to SP4 and SM1 to SM4.
  • the switching frequency of the switch elements SP1 to SP4 and SM1 to SM4 is a frequency at which a smoothing action is generated by the first inductor L1 and the second inductor L2. As a result, a sinusoidal current is injected into the system. As described above, since the four switch elements SB1 to SB4 of the bridge circuit 30 are switching-controlled not at the carrier frequency but at the power supply frequency of the system, switching loss can be reduced.
  • the inverter device 101 when the inverter device 101 outputs a voltage of 9 levels, the states of the switch elements SP1 to SP4, SM1 to SM4, the output voltage VP of the first three-level circuit 10, the output of the second three-level circuit 20 A relationship between the voltage VM and the output voltage Vo at the terminal U-W (voltage difference between the terminals U-W) will be described.
  • the first three-level circuit 10 and the second three-level circuit 20 output a five-level positive voltage, and the polarity of the positive voltage is inverted by the bridge circuit 30, whereby the inverter device 101 is A 9-level sine wave voltage is output.
  • generation of a sine wave positive voltage will be described.
  • the on-duty of each switch element in units of T / 8 (T: switching period).
  • FIG. 4 and 5 show the first three-level circuit 10 when the on-duty ratio is 12.5% when the switching elements SP1 to SP4 and SM1 to SM4 of the second three-level circuit 10 are set to 12.5%.
  • FIG. 6 is a diagram showing the relationship between the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo (voltage difference between the terminals U-W) of the terminal U-W.
  • 6 and 7 are diagrams showing current paths in the eight time intervals I to VIII shown in FIGS.
  • the switching of the first three-level circuit 10 is controlled by 360 ° / (n ⁇ 1) phase shift PWM.
  • n is 3.
  • the switch elements SP1 and SP2 are supplied with drive signals modulated by two triangular waves having phases different from each other by 180 degrees.
  • An inverted signal of the drive signal to the switch element SP2 is input to the switch element SP3.
  • An inverted signal of the drive signal to the switch element SP1 is input to the switch element SP4.
  • the switching of the second three-level circuit 20 is controlled by 360 ° / (n ⁇ 1) phase shift PWM.
  • n is 3.
  • the switch elements SM1 and SM2 are supplied with drive signals modulated by two triangular waves each having a phase difference of 180 degrees.
  • the switch elements SM1, SM2 are turned on with a phase difference of 90 degrees from the switch elements SP1, SP2 of the first three-level circuit 10.
  • An inverted signal of the drive signal to the switch element SM2 is input to the switch element SM3.
  • An inverted signal of the drive signal to the switch element SM1 is input to the switch element SM4.
  • the current path in the time intervals I to VIII repeats the state transition of the states CP1 ⁇ CP2 ⁇ CP3 ⁇ CP2 ⁇ CP4 ⁇ CP2 ⁇ CP5 ⁇ CP2 ⁇ ... Among the five states shown in FIGS.
  • the switch element SP1 or SP2 When the switch element SP1 or SP2 is on, the first three-level circuit 10 outputs an output voltage VP of Vin / 2.
  • the switch element SM1 or SM2 When the switch element SM1 or SM2 is on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin / 2. In this case, the average value of the output voltage Vo (VP ⁇ VM) is Vin / 4.
  • FIG. 8 and 9 show the first three-level circuit 10 when the on-duty ratio is 25.0% when the switch elements SP1 to SP4 and SM1 to SM4 of the second three-level circuit 10 are set to 25.0%.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W. Further, current paths in the eight time intervals I to VIII shown in FIGS. 8 and 9 are shown in FIGS.
  • the switch elements SP1 and SP2 are supplied with drive signals modulated by two triangular waves having phases different from each other by 180 degrees.
  • an inverted signal of the drive signal to the switch element SP1 is input to the switch element SP4 to which the inverted signal of the drive signal to the switch element SP2 is input.
  • the switch elements SM1 and SM2 are turned on when supplied with drive signals modulated by two triangular waves whose phases are different from each other by 180 degrees.
  • the switch elements SM1, SM2 are turned on with a phase difference of 90 degrees from the switch elements SP1, SP2 of the first three-level circuit 10.
  • An inverted signal of the drive signal to the switch element SM2 is input to the switch element SM3.
  • the switch element SM4 receives an inverted signal of the drive signal to the switch element SM1.
  • the current paths in the time intervals I to VIII repeat the state transitions of the states CP1 ⁇ CP1 ⁇ CP3 ⁇ CP3 ⁇ CP4 ⁇ CP4 ⁇ CP5 ⁇ CP5 ⁇ ... Among the states shown in FIGS.
  • the first three-level circuit 10 outputs an output voltage VP of Vin / 2.
  • the switch elements SM1 and SM2 are on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin / 2.
  • the output voltage Vo (VP-VM) is Vin / 2.
  • FIGS. 10 and 11 show the first three-level circuit 10 when the switch elements SP1 to SP4 and SM1 to SM4 of the first three-level circuit 10 and the second three-level circuit 20 have an on-duty ratio of 37.5%.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W.
  • 12 and 13 are diagrams showing current paths in the eight time intervals I to VIII shown in FIGS. 10 and 11.
  • the drive signals supplied to the switch elements SP1 to SP4 and SM1 to SM4 are the same as in the case of FIG. 8 except that the on-duty ratio is different.
  • the current path in the time interval I to VIII repeats the state transitions of state CP1 ⁇ CP2 ⁇ CP3 ⁇ CP4 ⁇ CP5 ⁇ CP6 ⁇ CP7 ⁇ CP8 ⁇ .
  • the first three-level circuit 10 outputs an output voltage VP of Vin / 2.
  • the switch elements SM1 and SM2 are on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin / 2.
  • the average value of the output voltage Vo (VP ⁇ VM) is 3Vin / 4.
  • FIGS. 14 and 15 show the first three-level circuit 10 when the on-duty ratio is 50.0% for the switch elements SP1 to SP4 and SM1 to SM4 of the first three-level circuit 10 and the second three-level circuit 20, respectively.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W.
  • Current paths in the eight time intervals I to VIII shown in FIGS. 14 and 15 are represented in FIGS. 12 and 13.
  • the drive signals supplied to the switch elements SP1 to SP4 and SM1 to SM4 are the same as in the case of FIG. 8 except that the on-duty ratio is different.
  • the current path in the time interval I to VIII repeats the state transition of the states CP3 ⁇ CP3 ⁇ CP3 ⁇ CP3 ⁇ CP7 ⁇ CP7 ⁇ CP7 ⁇ ... Among the states shown in FIGS.
  • the switch element SP1 or SP2 When the switch element SP1 or SP2 is on, the first three-level circuit 10 outputs an output voltage VP of Vin / 2.
  • the switch element SM1 or SM2 When the switch element SM1 or SM2 is on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin / 2.
  • the output voltage Vo (VP-VM) is Vin.
  • FIGS. 16 and 17 show the first three-level circuit 10 when the switch elements SP1 to SP4 and SM1 to SM4 of the first three-level circuit 10 and the second three-level circuit 20 have an on-duty ratio of 62.5%.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W.
  • 18 and 19 are diagrams showing current paths in the eight time intervals I to VIII shown in FIGS. 16 and 17.
  • the drive signals supplied to the switch elements SP1 to SP4 and SM1 to SM4 are the same as in the case of FIG. 8 except that the on-duty ratio is different.
  • the current path in the time interval I to VIII repeats the state transition of the states CP1 ⁇ CP2 ⁇ CP3 ⁇ CP4 ⁇ CP5 ⁇ CP6 ⁇ CP7 ⁇ CP8 ⁇ ... Among the states shown in FIGS.
  • the first three-level circuit 10 outputs the Vin output voltage VP.
  • the Vin / 2 output voltage VP is output. Is output.
  • the second three-level circuit 20 When both switch elements SM1 and SM2 are on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin, and when one of the switch elements SM1 and SM2 is on, an output voltage of ⁇ Vin / 2. Output VM.
  • the average value of the output voltage Vo (VP ⁇ VM) is 5 Vin / 4.
  • FIG. 20 and 21 show the first three-level circuit 10 when the switch elements SP1 to SP4 and SM1 to SM4 of the first three-level circuit 10 and the second three-level circuit 20 have an on-duty ratio of 75.0%.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W. Current paths in the eight time intervals I to VIII shown in FIGS. 20 and 21 are shown in FIGS. 18 and 19.
  • the drive signals supplied to the switch elements SP1 to SP4 and SM1 to SM4 are the same as those in FIG. 8 except that the on-duty ratio is different.
  • the current path in the time interval I to VIII repeats the state transition of the states CP3 ⁇ CP3 ⁇ CP5 ⁇ CP5 ⁇ CP7 ⁇ CP7 ⁇ CP1 ⁇ ... Among the states shown in FIGS.
  • the first three-level circuit 10 outputs the Vin output voltage VP.
  • the Vin / 2 output voltage VP is output. Is output.
  • the second three-level circuit 20 When both switch elements SM1 and SM2 are on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin, and when one of the switch elements SM1 and SM2 is on, an output voltage of ⁇ Vin / 2. Output VM.
  • the output voltage Vo (VP-VM) is 3Vin / 2.
  • FIG. 22 and 23 show the first three-level circuit 10 when the switch elements SP1 to SP4 and SM1 to SM4 of the first three-level circuit 10 and the second three-level circuit 20 have an on-duty ratio of 87.5%.
  • FIG. 6 is a diagram showing the relationship among the output voltage VP of the level circuit 10, the output voltage VM of the second three-level circuit 20, and the output voltage Vo at the terminal U-W.
  • 24 and 25 are diagrams showing current paths in the eight time intervals I to VIII shown in FIGS. 22 and 23.
  • the drive signals supplied to the switch elements SP1 to SP4 and SM1 to SM4 are the same as in the case of FIG. 8 except that the on-duty ratio is different.
  • the current paths in the time intervals I to VIII repeat the state transitions of the states CP1 ⁇ CP2 ⁇ CP1 ⁇ CP3 ⁇ CP1 ⁇ CP4 ⁇ CP1 ⁇ CP5 ⁇ ... Among the states shown in FIGS.
  • the first three-level circuit 10 outputs the Vin output voltage VP.
  • the Vin / 2 output voltage VP is output. Is output.
  • the second three-level circuit 20 When both switch elements SM1 and SM2 are on, the second three-level circuit 20 outputs an output voltage VM of ⁇ Vin, and when one of the switch elements SM1 and SM2 is on, an output voltage of ⁇ Vin / 2. Output VM.
  • the average value of the output voltage Vo (VP ⁇ VM) is in the range of 7Vin / 4.
  • FIG. 26 is a waveform diagram of the target value of the output voltage Vo.
  • PWM modulation is performed with two values of 0 and Vin / 2
  • Vin when the target value is in the range of Vin / 2 to Vin, PWM modulation is performed with binary values of Vin / 2 and Vin.
  • the five three-level circuits 10 and 20 are set to five levels of 0, Vin / 2, Vin, 3Vin / 2, and 2Vin. Is output.
  • the inverter device 101 outputs the 9-level voltage shown in FIG. 26 by inverting the polarity of the output voltage from the two 3-level circuits 10 and 20 by the bridge circuit 30.
  • a sine wave voltage is generated by PWM modulation using a plurality of voltage levels, the ripple current flowing through the inductors L1 and L2 is reduced, and the loss due to the inductors L1 and L2 is reduced.
  • the required inductance value may be small (in principle, it may be 1/16), small inductors L1 and L2 can be used.
  • the inverter device 101 can output a high-order level voltage while avoiding an increase in size due to an increase in the number of switch elements.
  • the inverter device 101 that outputs a voltage of 9 levels with the same number of switch elements as in the case of 5 levels can be realized.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
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WO2020137633A1 (ja) * 2018-12-27 2020-07-02 東芝インフラシステムズ株式会社 電力変換装置
JP2020108326A (ja) * 2018-12-27 2020-07-09 東芝インフラシステムズ株式会社 電力変換装置

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CN106787891B (zh) * 2017-03-06 2023-07-07 云南电网有限责任公司电力科学研究院 一种五电平逆变器
WO2020137633A1 (ja) * 2018-12-27 2020-07-02 東芝インフラシステムズ株式会社 電力変換装置
JP2020108326A (ja) * 2018-12-27 2020-07-09 東芝インフラシステムズ株式会社 電力変換装置
JP7293001B2 (ja) 2018-12-27 2023-06-19 東芝インフラシステムズ株式会社 電力変換装置

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