WO2014191280A1 - Träger für einen optoelektronischen halbleiterchip und optoelektronisches bauteil - Google Patents
Träger für einen optoelektronischen halbleiterchip und optoelektronisches bauteil Download PDFInfo
- Publication number
- WO2014191280A1 WO2014191280A1 PCT/EP2014/060456 EP2014060456W WO2014191280A1 WO 2014191280 A1 WO2014191280 A1 WO 2014191280A1 EP 2014060456 W EP2014060456 W EP 2014060456W WO 2014191280 A1 WO2014191280 A1 WO 2014191280A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- carrier
- optoelectronic semiconductor
- region
- main surface
- semiconductor chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 127
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 102
- 239000000463 material Substances 0.000 claims abstract description 91
- 238000011049 filling Methods 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 239000000945 filler Substances 0.000 claims description 48
- 239000012777 electrically insulating material Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000969 carrier Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000002131 composite material Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000758 substrate Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- 229910052719 titanium Inorganic materials 0.000 description 7
- 239000010936 titanium Substances 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000197 pyrolysis Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02016—Circuit arrangements of general character for the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/483—Containers
- H01L33/486—Containers adapted for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12035—Zener diode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
Definitions
- WO 2012/034752 describes a carrier for an optoelectronic semiconductor chip and a
- An object to be solved is to specify a carrier and an optoelectronic semiconductor component which can be produced particularly inexpensively.
- the carrier is suitable as a carrier for an optoelectronic semiconductor chip.
- the optoelectronic semiconductor chip may be, for example, a light-emitting diode chip, a
- Laser diode chip or a radiation-detecting chip such as a photodiode chip act.
- the carrier is suitable for the optoelectronic semiconductor chip
- the carrier is intended to electrically contact the optoelectronic semiconductor chip.
- the carrier can therefore be, in particular, a connection carrier or a printed circuit board which is connected to the optoelectronic device
- the carrier comprises a base body.
- the main body has a first main surface and a second main surface.
- the first main surface is, for example, the top surface of the main body.
- the second major surface is then around the bottom surface of the body, which is opposite to the top surface of the body.
- the main body can be made homogeneous. That is, the body is in this case formed with a single material and consists, except for possible impurities and dopants, of this material.
- the carrier comprises at least one recess.
- the carrier may comprise two, three or a plurality of similar recesses.
- the at least one recess of the carrier is introduced into the base body. In the region of the recess of the carrier, the material of the base body is removed.
- the recess extends in the main body from the first main surface to the second main surface. In this case, the recess extends, for example, along a straight line between the first main surface and the second main surface, wherein the straight line can extend perpendicular to the first and / or the second main surface within the manufacturing tolerance.
- the at least one recess penetrates the body completely. That is, the recess is
- a hole in the base body which extends from the first main surface to the second main surface and in the region of which the material of the base body is completely removed.
- the region of the recess can already be kept free during the production of the basic body, so that no removal of the material is necessary for the formation of the recess.
- the carrier comprises a filling material, which in the at least one recess is introduced.
- the filling material preferably completely fills the recess within the scope of the manufacturing tolerance.
- the filler is of the material of the body
- the filling material is introduced into the recess of the base body. That is, in the preparation of the carrier, first a recess is present or the recess is produced and then the filler material in the
- Base body is thus not generated by doping or oxidation of the material of the body, but filling material is filled in the recess of the body.
- the carrier is the
- Basic body formed with silicon. It is possible that the base body consists of silicon.
- the main body is formed in particular with crystalline silicon.
- Base body has silicon of a first
- Basic body is for example p-doped or n-doped.
- the main body is electrically conductive in this way
- the silicon of the main body can be any material educated.
- the filling material is formed with polycrystalline silicon of a second conductivity type.
- the filler material may consist of the polycrystalline silicon, or the filler may, in addition to the polycrystalline silicon another
- Material such as a metal include.
- Polycrystalline silicon consists of small ones
- Basic body is formed. In polycrystalline silicon, however, there are crystalline regions which adjoin each other.
- the polycrystalline silicon has a second one
- Conductivity type is different.
- the polycrystalline silicon may be n-doped or p-doped. That is, the first and second conductivity types
- the filler material may be formed electrically conductive in this way.
- this is polycrystalline
- the base body and the filling material are in direct contact with each other in places. That is, there are areas between body and filler in which the body and the filler directly adjacent to each other and a
- the thin layer of silicon oxide has, for example, a thickness of at most 5 nm, for example of 3 nm.
- the thin layer For example, silicon oxide is useful if the polycrystalline silicon of the filler is to be deposited on the silicon of the main body since it is a
- the carrier comprises a main body which has a first main area and a second main area
- the main body has major surface, at least one recess which is introduced into the base body and which completely penetrates the base body from the first main surface to the second main surface and a filler material which is introduced into the at least one recess.
- the main body is formed with silicon of a first conductivity type and the
- Filler material is formed with polycrystalline silicon of a second conductivity type.
- a carrier is specified, which is particularly inexpensive to produce.
- the filler material forms through holes
- Silicon is used, these vias can be generated particularly cost. Furthermore, the base body and the filler material have similar thermal properties due to the similar materials used
- a space charge zone is formed in the region of the direct contact between the base body and the outdiffusion of the filling material. That is, in the area of direct contact, a depletion zone or barrier layer is created, and thus an area in which space charges face excess and lack of charge carriers. In this way, the area of direct contact between the body and the filler material appears to be charge neutral.
- the base body and filling material have a conductivity type which is different from one another.
- the filler is n-type and the base is p-type. In this way, in the region of the direct contact between the filler material and the main body, a pn junction also forms.
- the space charge zone and the formed pn junction can be dispensed with at least in places along the recess on an electrical insulation between the base body and the filler material.
- the base body and the filling material can adjoin one another directly along the complete recess. Nevertheless, the base body and the filler material for connection to p- and n-terminal areas of an optoelectronic
- Discharge protection of the optoelectronic semiconductor chip acts when it is connected in anti-parallel to a pn junction of the optoelectronic semiconductor chip.
- the n-type region of the carrier so for example the
- Base body is electrically conductively connected to the n-type terminal region of the optoelectronic semiconductor chip.
- the carrier is based on the knowledge that optoelectronic semiconductor chips often have no or only insufficient ESD protection. Therefore, must also, depending on the size of the optoelectronic
- varistor be installed. This increases the
- the component produced in this way can then be further processed and, for example as surface-mountable component can be used. It requires no further housing to integrate an ESD protection in the component. Due to the materials used, the pn junction in the carrier used as ESD protection is particularly simple and inexpensive even at the wafer level
- the recesses can be integrated. That is, the recesses can be
- the carrier is in the at least one recess, preferably then in each
- the electrically insulating material may be, for example, a silicon dioxide or a
- Silicon nitride act, which adheres particularly well to the body and the filler.
- the area in which a space charge zone is formed is formed
- the cross-sectional area of the filling material is in a plane parallel to the first and / or second
- the filler material comprises a metal, wherein the polycrystalline silicon at least in places between the metal and the
- Filler material not of the polycrystalline silicon but the filler comprises at least one other material, namely a metal such as tungsten, aluminum or titanium. Further, it is possible that the filler material comprises a combination of at least two of these metals.
- the filling material then comprises, for example, the polycrystalline silicon, which is in direct contact with the main body in places.
- the polycrystalline silicon may be, for example, a
- Form lateral surface which encloses the metal.
- the metal is in the manner of a metallic via within the via polycrystalline
- the polycrystalline silicon serves to form a space charge zone and thus to form an ESD protection diode within the carrier.
- the electrical resistance of the via is reduced, so that this example with a smaller
- Cross-sectional area can be formed than this
- the filler material consists of polycrystalline silicon.
- the polycrystalline silicon is introduced in the production of the carrier, for example, only as a layer in the recess, which does not completely fill the recess. There remains a smaller recess, the body completely from the first to the second major surface
- the metal may be, for example, via a CMP process, Sputtering or an alternating deposition ⁇ t zuze in the reduced by the polycrystalline silicon
- a second electrically insulating material which completely surrounds the openings of the recess on the first main surface and / or the second main surface, is applied to the first main surface and / or the second main surface of the base body.
- the second electrically insulating material can thus be structured on at least one of the main surfaces of the
- the second electrically insulating material may be coated with materials such as
- Silicon dioxide or silicon nitride may be formed
- first electrically insulating material and the second electrically insulating material are formed with the same material and are applied or incorporated in the same production step onto the basic body or into the basic body.
- a first cross-sectional area of the filling material at the first main area and / or the second main area is smaller than a second cross-sectional area within the main body between the first main area and / or the second
- Main surface is arranged.
- the two cross-sectional surfaces extend, for example, parallel to the first and / or the second main surface. In other words, that can
- Fill material within the carrier have a larger cross-section than where it is at the top or
- the maximum cross-sectional area is
- the thickness of the filling material is for example at least 100 ⁇ m, e.g. 150 pm.
- resistivity of the filler of 0.001 gauge, a cross-sectional area of 225,000 square micrometer and a thickness of the filler of 150 ⁇ m gives a resistance of approximately 0.07 ⁇ .
- an electrically conductive material is applied to the first main area and / or the second main area in a first area of the carrier in direct contact with the filler material and in a second area of the carrier in direct contact with the base body stands.
- the electrically conductive material is electrically insulated in the first region from the electrically conductive material in the second region by the second electrically insulating material.
- the electrically conductive material may be any electrically conductive material.
- a metal such as aluminum, copper, silver, gold or an alloy with at least one of these
- the electrically conductive material serves to connect the carrier to its underside, for example at the place of use. At the top of the carrier, so at the Side of the first main surface of the body, the material is used for connection to the optoelectronic
- the carrier is in the main body directly below the electrically conductive
- the optoelectronic semiconductor component has a carrier described here. That is, all features disclosed to the wearer are also for the
- Optoelectronic semiconductor device disclosed. Furthermore, the optoelectronic semiconductor device has a
- optoelectronic semiconductor chip which comprises a first electrical connection region and a second electrical connection region.
- Semiconductor component can also be a variety of
- the optoelectronic semiconductor chip is on the side facing the first main surface of the base body, ie the
- Connection area electrically connected to the carrier.
- the optoelectronic semiconductor chip is, for example, a large semiconductor chip which
- optoelectronic semiconductor chips have a lower inherent ESD protection than is the case for smaller optoelectronic semiconductor chips. Large optoelectronic
- Luminance depending on the operating current in particular when the optoelectronic semiconductor chips are thin-film chips in which a growth substrate is removed from the epitaxially grown layers, has advantages.
- the first electrical connection region of the semiconductor chip with the electrically conductive material is in the first region of the carrier and the second electrical
- connection region of the semiconductor chip with the electrically conductive material in the second region of the carrier electrically conductively and mechanically connected, wherein the first electrical connection region and the second electrical connection region are each connected to an electrically unlike region of the carrier.
- the optoelectronic semiconductor chip has a pn junction which leads to the pn junction of the carrier due to the connection of unlike connection points is connected in antiparallel of carrier and optoelectronic semiconductor chips.
- the carrier can form an ESD protection for the optoelectronic semiconductor chip.
- Optoelectronic semiconductor device can therefore measures without further ESD protection, for example as
- the outer connection points of the optoelectronic semiconductor device are characterized by the electrically conductive material on the
- insulating material is electrically isolated from each other.
- a plurality of carriers as described herein are first prepared in combination.
- the recesses in the material of the body which is present as a disc, introduced and filled with the filling material.
- the main body is present, for example, as silicon wafers, for example as 6-inch, 8-inch or 12-inch silicon wafers.
- a multiplicity of optoelectronic semiconductor chips are applied to the multiplicity of
- the optoelectronic semiconductor chips may still be present in the wafer composite. That is to say, the optoelectronic semiconductor chips are connected to one another, for example, via a growth substrate and, when applied to the carriers, are not yet singulated into individual optoelectronic semiconductor chips. After the application of the optoelectronic semiconductor chips on the carriers then, for example, a detachment of the
- Optoelectronic semiconductor device at least one
- optoelectronic semiconductor chip comprises. When the arrangement is singulated, the composite of carriers is then severed by sawing, cutting or breaking.
- Components such as layers, structures,
- Base body 10 is provided, which may be, for example, a silicon single crystal wafer.
- Base 10 is doped p-type, for example.
- the main body has a first main surface 10a on the upper side and a second main surface 10b on the lower side.
- the main body 10 is formed, for example, by silicon doped with boron.
- the dopant concentration is at least 10 19 / cm 2 .
- the second electrically insulating material 16 is structured on the first main surface 10a and on the second main surface 10b
- the second electrically insulating material 16 is a dielectric material which serves as an etching mask and remains in the substrate in the course.
- the second electrically insulating material may be silicon dioxide or silicon nitride.
- the production of recesses 11 anisotropically takes place, for example, by means of reactive ion etching through the mask formed in the base body 10 by the second electrically insulating material 16.
- the recesses 11 penetrate the base body 10 from the first main surface 10a to the second main surface 10b.
- the filler material 12 may also be initially arranged on the upper side of the second electrically insulating material 16 facing away from the main body 10.
- the filler material 12 is polycrystalline silicon, which may be n-doped with phosphorus, for example.
- Recesses 11 is suitable, for example, a CVD process from the gas phase with an in situ doping of the filler.
- a CVD process from the gas phase with an in situ doping of the filler.
- SiH 4 silanes
- pyrolysis of SiH 4 occurs in one PVCD method and doping with PH3, BH3, B2H6 or AsH3.
- methods such as MBE or LPE for
- Activation of the dopant may take place by heating, for example to temperatures higher than 900 ° C for 60 minutes or longer.
- Filler can also be deposited amorphous silicon, which by a subsequent annealing step, for example in the activation of the dopant, to polycrystalline
- the filling material 12 is removed from the upper side of the second electrically insulating material 16 facing away from the main body 10, for example by etching back dry-chemical or wet-chemical. Subsequently, a diffusion of, for example, by annealing takes place
- the annealing may, for example, be at least 900 ° C for at least ten minutes.
- the second electrically insulating material 16 is removed in places, so that the second electrically insulating material 16 completely surrounds the filling material 12 on the first main surface 10a and the second main surface 10b, and areas on the first main surface 10a and the second main surface 10b of the main body are exposed ,
- next method step it is optionally possible to carry out a further p-doping, for example with boron, of the base body 10 by, for example, planar implantation or diffusion in the exposed areas of the base body 10.
- dopant is introduced in such a concentration that no undotation takes place in the filler material 12.
- an electrically conductive material 17, for example a metal in the first
- Base 10 is in direct contact. In this way, by the electrically conductive material
- Connection points of the carrier 1 is formed.
- Filler 12 includes a metal 121 as another
- the metal 121 is arranged, for example, in the recess 11 such that the polycrystalline silicon is arranged between the metal 121 and the base body 10.
- the recess 11 for example, initially produced by etching and filled with polycrystalline silicon, wherein the recess 11, for example, not completely with the polycrystalline
- Silicon is filled, but the base body 10 in the region of the recess 11 with the polycrystalline silicon
- the metal 121 may, for example, be at least one of the following metals: W, Al, Ti.
- the metal 121 may in any case comprise titanium which reacts with silicon to form TiSi, which is characterized by a low ohmic contact resistance.
- the titanium can be introduced, for example, by sputtering. Subsequently, for example, an annealing is carried out at at least 600 ° C. In a next step, after removing the titanium from the electrically insulating material 16, a second annealing step may be performed at a higher temperature to produce the highly conductive TiSi. Further, it is possible that the metal 121 is titanium in
- the titanium can, for example, the formation of unwanted
- a plated-through hole is formed, which has a jacket surface which is formed with polycrystalline silicon which encloses a metallic core which is formed with the metal 121.
- the space charge zone 13 is preferably formed before the introduction of the metal 121.
- the first electrically insulating material 15 may be, for example, a silicon nitride or a silicon oxide. Further, it is possible that the first electrically insulating material and the second electrically insulating material are integrally formed
- the recesses 11 thus coated with the first electrically insulating material 15 are filled with the filling material 12, see FIG. 2A.
- FIG. 2B a back etching of the filling material takes place into the recesses 11, such that a part of the first electrically insulating material 15
- first electrically insulating material 15 is used for the first electrically insulating material 15 and silicon nitride is used for the second electrically insulating material 16 or first electrically insulating material 15 and second electrically insulating material 16 are formed with the same material, wherein the second electrically insulating material 16 is thicker than the first electrically insulating material 15 is formed.
- first electrically insulating material 15 is completely removed in places in the recess 11 and the second electrically
- insulating material 16 in the dry or wet chemical Etch back remains on the first main surface 10a of the body 10.
- Filler 12 'deposited which may also be doped polycrystalline silicon.
- outdiffusion of the dopant of the filling material 12 takes place by annealing, for example, again at a temperature of at least 900 ° C. over a period of at least ten minutes. Furthermore, an etching of the other
- the space charge zone 13 and the pn junction 14 arise.
- the filling material 12 in the inner region of the main body 10 has a larger one
- Cross-sectional area A2 as the smaller cross-sectional area AI at the top and the bottom of the carrier 1. In this way, the resistance of the via, which is formed with the filler material 12 can be reduced without the pads on the top for connecting an optoelectronic semiconductor chip or at the
- Main surface 10 a of the main body 10 take place, wherein a Distance between the carrier bottom to the pn junction 14 of greater than 200 nm is advantageous.
- a carrier 1 is first provided, as for example, by one of the in connection with the figures 1A to IG or 2A to 2F
- optoelectronic semiconductor chips 2 take place.
- these are light-emitting diode chips in which a growth substrate 27, which is formed, for example, with sapphire, remains in the semiconductor chip.
- Each optoelectronic semiconductor chip 2 has the growth substrate 27, an n-type region 24, a p-type region 25, a mirror 26 and plated-through holes 28. Between the n-type region 24 and the p-type region 25, the pn junction 23 of the semiconductor chip 2 is arranged.
- Vias 28 extend, for example, from of the second connection point 22 into the n-type region, so that the second connection region 22 forms the n-type connection point of the semiconductor chip 2.
- the semiconductor chip 2 is connected via the first connection region 21.
- the semiconductor chips 2 are individually connected to the composite of carriers 1 in such a way that the n-conducting connection point of the second connection region 22 is electrically conductively connected to the p-conducting second region B2 of the carrier. Accordingly, the p-type junction of the
- optoelectronic semiconductor chip 2 include.
- the optoelectronic semiconductor component is then connected on the n side in the p-type second region B2 and connected on the p-side in the n-type first region B1.
- the optoelectronic semiconductor chip 2 is electrically contacted and the carrier 1 forms an ESD protection.
- the polarities in the semiconductor chip 2 and in the carrier 1 can also be selected reversed. That is, the
- Base 10 may be doped n-type, for example, and be electrically connected to the p-type region of the semiconductor chip 2.
- Optoelectronic semiconductor chip 2 not individually, but also connected in the wafer composite with the carriers present in the composite 1 and electrically connected.
- the semiconductor chips 2 are first mechanically connected to one another via the growth substrate 27 and are mounted in a composite on the composite of carriers 1. This is illustrated in connection with FIGS. 4A and 4B. In the next
- Semiconductor chips 2 for example, by a mesa etch, wherein the mesa etch before the application of the semiconductor chips 2 on the carrier, so still on the growth substrate 27, can be done.
- the mesa etching takes place from the side facing away from the growth substrate 27.
- FIG. 4E separation takes place into individual optoelectronic semiconductor components.
- Such an optoelectronic semiconductor component is shown again in FIG.
- Semiconductor component comprises the carrier 1 with the base body 10, which is formed for example of p-doped crystalline silicon.
- the recess 11 is introduced, which is partially covered on their side surfaces of the first electrically insulating material 15.
- the filling material 12 is, for example, n-doped polycrystalline silicon. In the area of
- the space charge zone 13 is generated by diffusion of the n-type dopant of the filling material into the p-doped material of the base body 10 during annealing.
- the base body 10 of the carrier is structuredly covered by the second electrically insulating material 16.
- the second electrically insulating material 16 constitutes an electrical insulation between the electrically conductive material applied in the first region B1 and in the second region B2 of the carrier.
- a semiconductor chip 2 is arranged on the upper side of the carrier 1 facing the first main surface 10a of the carrier 10 an n-type region 24, a p-type region 25, and a pn junction 23 therebetween.
- Through-holes 28 extend through the mirror 26, the p-type region 25 and the pn junction 23 into the n-type region 24. N-side, so on the second
- the semiconductor chip 2 is connected to the p-type region of the carrier 1.
- the carrier 1 is contacted on its underside via the electrically conductive material 17 on the p-side.
- the invention is not limited by the description based on the embodiments of these, but includes each new feature and any combination of features, which in particular any combination of features in the
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112014002623.9T DE112014002623B4 (de) | 2013-05-31 | 2014-05-21 | Optoelektronisches Bauteil und Herstellungsverfahren hierfür |
US14/889,771 US20160141286A1 (en) | 2013-05-31 | 2014-05-21 | Carrier For An Optoelectronic Semiconductor Chip And Optoelectronic Component |
KR1020157036202A KR20160016876A (ko) | 2013-05-31 | 2014-05-21 | 광전 반도체 칩을 위한 캐리어 및 광전 소자 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102013105631.8A DE102013105631A1 (de) | 2013-05-31 | 2013-05-31 | Träger für einen optoelektronischen Halbleiterchip und optoelektronisches Bauteil |
DE102013105631.8 | 2013-05-31 |
Publications (1)
Publication Number | Publication Date |
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WO2014191280A1 true WO2014191280A1 (de) | 2014-12-04 |
Family
ID=50771281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/EP2014/060456 WO2014191280A1 (de) | 2013-05-31 | 2014-05-21 | Träger für einen optoelektronischen halbleiterchip und optoelektronisches bauteil |
Country Status (4)
Country | Link |
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US (1) | US20160141286A1 (de) |
KR (1) | KR20160016876A (de) |
DE (2) | DE102013105631A1 (de) |
WO (1) | WO2014191280A1 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106601706A (zh) * | 2015-10-16 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件和电子装置 |
US20190027669A1 (en) * | 2015-08-12 | 2019-01-24 | Osram Opto Semiconductors Gmbh | Semiconductor chip |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102015107526A1 (de) * | 2015-05-13 | 2016-11-17 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und optoelektronisches Modul |
DE102018101815A1 (de) * | 2018-01-26 | 2019-08-01 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauelement und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauelements |
FR3102298B1 (fr) * | 2019-10-16 | 2022-07-29 | Aledia | Procede de protection d'un dispositif optoelectronique contre les decharges electrostatiques |
JP2022092294A (ja) * | 2020-12-10 | 2022-06-22 | スタンレー電気株式会社 | 半導体発光装置及び半導体発光素子の支持基板 |
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US20100301349A1 (en) * | 2005-01-26 | 2010-12-02 | Harvatek Corporation | Wafer level led package structure for increasing light-emitting efficiency and heat-dissipating effect and method for manufacturing the same |
WO2008021973A2 (en) * | 2006-08-10 | 2008-02-21 | Icemos Technology Corporation | Method of manufacturing a photodiode array with through-wafer vias |
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- 2014-05-21 US US14/889,771 patent/US20160141286A1/en not_active Abandoned
- 2014-05-21 WO PCT/EP2014/060456 patent/WO2014191280A1/de active Application Filing
- 2014-05-21 DE DE112014002623.9T patent/DE112014002623B4/de active Active
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US20050121686A1 (en) * | 2003-12-09 | 2005-06-09 | Bernd Keller | Semiconductor light emitting devices and submounts and methods for forming the same |
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Also Published As
Publication number | Publication date |
---|---|
US20160141286A1 (en) | 2016-05-19 |
DE112014002623B4 (de) | 2021-08-19 |
DE112014002623A5 (de) | 2016-03-10 |
DE102013105631A8 (de) | 2015-02-12 |
KR20160016876A (ko) | 2016-02-15 |
DE102013105631A1 (de) | 2014-12-04 |
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