WO2014187164A1 - 集成led发光器件及其制作方法 - Google Patents

集成led发光器件及其制作方法 Download PDF

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Publication number
WO2014187164A1
WO2014187164A1 PCT/CN2014/071093 CN2014071093W WO2014187164A1 WO 2014187164 A1 WO2014187164 A1 WO 2014187164A1 CN 2014071093 W CN2014071093 W CN 2014071093W WO 2014187164 A1 WO2014187164 A1 WO 2014187164A1
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Prior art keywords
electrode pad
epitaxial
pad layer
led
electrode
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PCT/CN2014/071093
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English (en)
French (fr)
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黄少华
曾晓强
赵志伟
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厦门市三安光电科技有限公司
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Publication of WO2014187164A1 publication Critical patent/WO2014187164A1/zh
Priority to US14/748,921 priority Critical patent/US9472726B2/en
Priority to US15/289,145 priority patent/US9812613B2/en

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Definitions

  • the present invention relates to the field of semiconductor lighting devices, and in particular, to an integrated LED light emitting device and a manufacturing method thereof.
  • the former proposed the concept of high-voltage LED chip, and realized its advantages in practical applications, but the traditional high-voltage chip still has no improvement in package soldering, electrode shading and poor stability of each LED connection in the core particles. .
  • the invention provides an integrated LED
  • the light-emitting device and the manufacturing thereof can effectively improve problems such as package soldering, electrode shading, and poor connection stability.
  • an integrated LED lighting device comprises: at least two or more separate LEDs An illuminating epitaxial unit comprising upper and lower surfaces, the upper surface of which is a light-emitting surface; and an electrode pad layer formed on a lower surface of the LED light-emitting epitaxial unit, having a sufficient thickness to support the LED
  • the epitaxial unit is connected to the respective LED light-emitting epitaxial units to form a joint circuit having no plane of high and low drop; the electrode pad layer is divided into P and N electrode regions.
  • Each of the LED light emitting epitaxial units constitutes a series, parallel or series-parallel circuit.
  • the light emitting device can be directly applied to an SMT package, which is packaged on the carrier substrate through the electrode pad layer.
  • the electrode pad layer is formed by electroforming.
  • the electrode pad layer has a thickness of 50 ⁇ m or more to support the epitaxial film.
  • the area of the P, N electrode regions of the electrode pad layer is substantially equal.
  • At least one insulating layer is disposed between the electrode pad layer and the LED light emitting epitaxial unit for adjusting the electrode pad layer P , N electrode area distribution.
  • the electrode pad layer and the thin film LED At least two insulating layers are further disposed between the light emitting epitaxial units, wherein the first insulating layer realizes isolation of P and N regions of each thin film LED light emitting epitaxial unit, and the second insulating layer realizes P and N of the electrode pad layer
  • the electrode area is substantially equal.
  • an insulator is further included, which is inserted into the electrode pad layer to divide the electrode pad layer under each LED light-emitting epitaxial unit into P , N two regions, the lower surface of which is not higher than the surface of the electrode pad.
  • the P and N regions of the electrode pad layer are electrically isolated by the insulator, and the gap may be 20 ⁇ 100 ⁇ m .
  • the height difference between the surface of one end of the insulator away from the epitaxial layer and the surface of the electrode pad layer and the lower surface of the electrode pad layer is 20-100 ⁇ m. .
  • the melting point or softening point of the insulator is lower than the melting point of the P and N electrode pads, and the material thereof may be a colloidal material such as SU8, BCB. Or dry film, etc.
  • the electrode pad layer and insulator occupy the entire surface of the LED epitaxial structure.
  • the P-type pad in the single thin film LED and the N in the adjacent independent LED light-emitting unit The pad is coupled to the lower surface, and the coupling circuit is a plane having no height difference.
  • a method of fabricating an integrated LED light emitting device is as follows:
  • Epitaxial growth forming an LED light-emitting epitaxial stack on a growth substrate by an epitaxial growth process
  • Making an electrode pad layer defining a dicing street on the surface of the LED epitaxial laminate, which will be the LED
  • the epitaxial stack is divided into a series of light emitting units, and the surface of each unit is divided into P, N electrode regions and isolation regions; an electrode pad layer is formed on the LED epitaxial stack, covering the cutting streets and P, N An electrode region having sufficient thickness to support the LED light emitting epitaxial stack; removing the growth substrate and removing the LED light emitting epitaxial stack of the scribe line to form a series of connections connected by the electrode pad layer led Illumination epitaxial unit;
  • the above-formed structure is cut along the scribe line as needed to form a series of integrations consisting of several LED illuminating epitaxial units LED light emitting device, wherein the P and N connecting circuits between the adjacent thin film LED light emitting epitaxial units are
  • the electrode pad layer may be formed by electroforming in the chip fabrication step.
  • an insulator is formed in the isolation region of the LED epitaxial stack to separate P, N of the electrode pad layer.
  • the electrode region which is away from the surface of one end of the epitaxial stack, is flush with or higher than the surface of the electrode pad layer.
  • the P and N electrode regions of the electrode pad layer are electrically isolated by the insulator, and the gap may be 20 ⁇ 100 ⁇ m.
  • the step of fabricating the electrode pad layer includes: the electrode pad layer and the thin film LED Forming at least two insulating layers between the light emitting epitaxial units, wherein the first insulating layer realizes isolation of P and N electrode regions of each thin film LED light emitting epitaxial unit, and the second insulating layer realizes P and N of the electrode pad layer
  • the area is basically the same size.
  • the electrode pad layer in the fabrication of the electrode pad layer, P, N of the electrode pad layer on each cell The electrode regions are uniformly distributed.
  • a series of LED light emitting cell arrays connected in series, in parallel or in series and parallel are formed by removing corresponding electrode pad layers of a portion of the dicing streets.
  • each of the LEDs In fabricating an electrode pad layer, each of the LEDs
  • the light-emitting epitaxial cells are arranged in rows (columns) in which P, N of the electrode pad layer of each of the P, N electrode regions and even rows (columns) of the odd row (column) electrode pad layer
  • the electrode regions are reversely distributed, and in the cutting step, an alternating current circuit connection is formed by removing a portion of the corresponding electrode pad layer of the scribe line.
  • integrated LED The light-emitting device has the advantages of a general high-voltage serial chip and a series-parallel chip, and helps to improve the electro-optic efficiency of the entire light-emitting device including the power supply.
  • the integrated LED The light-emitting device saves the package material and has an advantage in manufacturing cost;
  • the epitaxy is directly attached to the pad, which is more effective than the general chip package.
  • the overall device area is relatively small compared to the chip package.
  • the integrated LED The device can also be coated with phosphor before the chip is cut to form a wafer-level white light-emitting device, forming a simple component, which is more convenient for mass production. In heat treatment, the thermal resistance of the package is reduced, so that the integrated LED The device has better heat dissipation, and better heat treatment can increase the lifetime of the LED device.
  • the structure of the light-emitting device realizes the structural design in which the light-emitting and the line are separated, and the structure design can easily obtain multiple serial-parallel structures, and the circuit can be made without going through the high and low series lines compared with the general high-voltage series chip. A failure occurs, and this structural design can avoid the limitation of surface shading caused by the design of the circuit.
  • Figure 1 is a cross-sectional view showing the structure of an integrated LED light-emitting device according to Embodiment 1 of the present invention.
  • FIG. 2 is a bottom view and an equivalent circuit of the light emitting device shown in FIG. 1.
  • FIG. 3 is a cross-sectional view showing the structure of an integrated LED light-emitting device of Embodiment 2.
  • FIG. 4 is a cross-sectional view showing the structure of an integrated LED light-emitting device of Embodiment 3.
  • Figure 5 is a cross-sectional view showing the structure of an integrated LED light-emitting device of Embodiment 4.
  • Figure 6 is a cross-sectional view taken along line A-A of Figure 5.
  • FIG. 7 to 18 are schematic views of the process of preparing the light emitting device shown in Fig. 5.
  • Fig. 19 shows a first modified embodiment of the embodiment 4.
  • the core idea of the invention is to provide an integrated LED a light emitting device and a method of fabricating the same, wherein the light emitting epitaxial structure is supported by an electrode pad layer on a device structure and the respective LEDs are connected
  • the illuminating epitaxial unit forms a planar connecting circuit with no high and low drop, and the formed illuminating device can be directly mounted on the carrying substrate; in the manufacturing method, the singulated LED
  • the light-emitting epitaxial unit is supported by the electrode pad layer and electrically connected.
  • the integrated electrode light-emitting device of the planar connection circuit without high and low drop can be formed according to the device needs to cut the electrode pad layer.
  • three LED lighting units are taken to form an integrated LED.
  • the present invention is not limited thereto, and the number of light-emitting units may be selected according to specific implementation requirements.
  • an integrated LED light emitting device includes: an light emitting epitaxial unit 110, an ohmic contact layer 121, 122 , electrode pad layer 130, insulator 140. Specifically, each of the light-emitting epitaxial units 110 performs isolation of the epitaxial layers through the isolation channels 150. In a preferred embodiment, the isolation tracks 150 Filled with insulating material.
  • the light-emitting epitaxial unit 110 is a flip-chip structure, and includes an N-type epitaxial layer, a light-emitting layer, and a P-type epitaxial layer from top to bottom, but is not limited thereto.
  • N-type ohmic contact layer 121 and P The ohmic contact layer 122 is respectively located on the N-type epitaxial layer and the P-type epitaxial layer and is flush with the lower surface, and the material thereof may be Ti, Ni, Ag, Pt, Au, Cr or TiW.
  • One or a combination of them employs a multilayer structure of highly reflective metal material which acts as an ohmic contact on the one hand and a specular reflection on the other hand.
  • Electrode pad layer 130 is located The P and N type ohmic contact layers have a thickness of 50 ⁇ m or more to ensure support of the flip chip junction 110, preferably 70 to 150 ⁇ m.
  • the material of the electrode pad 130 can be One or a combination of Ti, Ni, Cu, Au, AuSn, SnCu, SnBi.
  • the insulator 140 is located at the P and N electrode pads 130p, The gap between the 130n and the N-type ohmic contact layer 121 and the P-type ohmic contact layer 122 is stepped, and the material thereof may be a permanent insulating colloid, such as SU8, BCB. Or dry film, etc.
  • the P region 130p and the N region 130n of the electrode pad layer 130 are The gap D is 20 ⁇ 150 ⁇ m, except for the first and last LED light-emitting units, the P area of each LED light-emitting unit electrode pad layer and the N of the electrode pad layer of the adjacent LED light-emitting unit.
  • the areas are connected into one piece, corresponding to the N area of each LED light-emitting unit electrode pad layer and the electrode pad layer of the adjacent LED light-emitting unit P
  • the zones are connected in one piece to achieve a circuit-free plane with no height difference.
  • the edge of the electrode pad layer is beyond the edge of the epitaxial structure, and the distance is controlled to be 30 ⁇ m.
  • Figure 2 is a bottom view and equivalent circuit of the device shown in Figure 1, and P and N represent the P and N regions of the electrode pad layer.
  • P and N represent the P and N regions of the electrode pad layer.
  • Each The LED lighting unit forms a series circuit connection through the electrode pad layer. Further, the electrode pad layer 130 and the insulator 140 fill the LED in the device.
  • the entire surface of the epitaxial structure ensures the integrity of the epitaxial structure support and can effectively prevent damage of the flip-chip epitaxial film.
  • the electrode pad layers P, N The shape and size of the area will become one of the important factors affecting the reliability of the device. For example, in the asymmetric electrode design of the prior art, the difference in electrode area size in the eutectic process may cause the chip to tilt, and the area is relatively large. A eutectic failure occurs at the small electrode, which eventually leads to failure of the electrical connection.
  • the main difference between this embodiment and the embodiment 1 is that the P and N regions 130p and 130n of the electrode pad layer.
  • the area is close to or substantially the same.
  • the insulating layer 160 is disposed on the P and N ohmic contact layers 122 and 121, and the N-type ohmic contact layer 121 and the LED are disposed.
  • the light-emitting layer of the epitaxial structure and the p-type epitaxial layer are electrically insulated. Opening a hole corresponding to the P, N ohmic contact layer on the insulating layer 160, and the electrode pad layer is filled through the open hole structure, P, N
  • the regions are in contact with the P and N ohmic contact layers, respectively.
  • the insulator 140 protrudes away from the one end lower surface of the light-emitting epitaxial stack to protrude the electrode pad layer 130.
  • the lower surface effectively prevents short-circuiting of the P and N electrodes in the package process of the device.
  • H the height difference between the relative position of the lower surface of the electrode pad layer 130 and the relative position of the lower surface of the insulator.
  • the gap D between the P and N regions of the electrode pad layer can optimize the implementation effect of the embodiment by adjusting the sizes of H and D.
  • the height difference H can be 20 ⁇ 100 ⁇ m
  • 50 ⁇ m and the gap D may be 20 to 100 ⁇ m, preferably 50 ⁇ m.
  • This embodiment optimizes the current injection structure of the LED epitaxial layer in Embodiment 2, and the main difference from Embodiment 2 is: in P, A double insulating layer and a conductive layer structure are disposed between the N ohmic contact layer and the electrode pad layer, wherein the first insulating layer and the conductive layer realize uniform current injection into the LED epitaxial structure, and the second insulating layer realizes the P and N
  • the area of the electrode pads is substantially the same. Referring to Figure 5 and Figure 6, wherein Figure 6 is a cross-sectional view along the first insulating layer 161, at each of the LED light-emitting epitaxial junction units 110.
  • the central region opens a plurality of first hole structures, which pass through the P-type epitaxial layer and the light-emitting layer to the N-type epitaxial layer, and cover the surface of the P-type epitaxial layer with the ohmic contact layer 120, and the ohmic contact layer 120
  • the upper insulating layer 161 is covered to cover the sidewall of the hole structure to expose the N-type epitaxial layer; the ohmic contact layer 120 corresponding to the first insulating layer 161
  • At least one second hole structure is formed in the position; a conductive layer is formed on the first insulating layer 161, and is divided into an N conductive region 170n and a P conductive region 170p, wherein the N conductive region 170n
  • the P conductive region 170p is in contact with the ohmic contact layer 120 through the second hole structure;
  • the second insulating layer 162 is formed on the conductive layer, and is respectively N
  • the third hole structure is opened at
  • Figure 7 ⁇ 17 shows the preparation of Figure 5
  • the process schematic of the illustrated light emitting device mainly includes three major process steps: epitaxial growth, chip fabrication, and cutting.
  • 9 to 16 are partial enlarged cross-sectional views of the B region of Fig. 8.
  • epitaxial growth is performed, specifically: providing a growth substrate 100, sequentially growing a buffer layer, an N-type epitaxial layer, a light-emitting layer, and P
  • the epitaxial layer is named 110, as shown in Figure 7.
  • a conventional epitaxial growth process such as MOCVD can be used.
  • a chip fabrication process including mesa etching, fabrication of an ohmic contact layer, fabrication of an insulator, fabrication of an electrode pad, and the like. details as follows:
  • the LED epitaxial stack is separated into a series of light emitting units 100 as shown in FIG. 8;
  • the ohmic contact layer 120 may be a highly reflective P-type ohmic contact material, specifically one or more of Cr, Ag, Ni, Al, Pt, Au, Ti, and the overall thickness is not less than 0.5um. , the optimal thickness is 1um;
  • first insulating layer 161 on the sidewalls of the ohmic contact layer 120 and the first hole structure 181 to expose the first hole structure
  • An N-type epitaxial layer at the bottom surface of 181 has at least one second hole structure 182 at a position corresponding to the ohmic contact layer 120 on the first insulating layer 161 of each of the LED light-emitting units, as shown in FIG. Shown
  • the electrode pad layer 130 is formed on the second insulating layer 162 to the respective light emitting units 110.
  • the electrode pad layer 130 is divided into N electrode regions 130n and P electrode regions 130p which are electrically isolated from each other, and an insulating material is filled as an insulator between the P and N electrode regions.
  • the P electrode area of each LED light emitting unit electrode pad layer and the N of the electrode pad layer of the adjacent LED light emitting unit The electrode areas are connected in a single piece to achieve a circuit-free plane with no height difference, as shown in Figure 14.
  • the plating material may be selected from Ni, Cu, Au, etc., which can be fused with Sn, and the thickness thereof is not less than 50um and forming a plating layer capable of supporting the light-emitting epitaxial structure;
  • the growth substrate 001 is removed by a known substrate lift-off technique to expose the surface of the light-emitting epitaxial laminate
  • the luminescent epitaxial stack is divided by a dicing street 150 into a series of individual cells that are isolated from one another.
  • electrode pad layer P for each cell The electrode region is in contact with the electrode pad layer N electrode region of the left cell, and is connected to the electrode pad layer P electrode region of the cell above and below; the electrode pad layer N electrode region of each cell is electrode-welded to the right cell thereof Disk layer P The electrode regions are connected to each other, and the electrode pad layer P electrode regions of the cells above and below are connected, and the insulator 140 is distributed in an uninterrupted line.
  • chip cutting please refer to Figure 18, cutting the core particles along the cutting channel in the direction of the arrow (a) to form a series of LEDs.
  • An integrated LED light-emitting device consisting of an illuminating epitaxial unit. Its equivalent circuit is shown in (b).
  • each of the LED light-emitting epitaxial cells is distributed in rows, and P and N of the electrode pad layers of each row The electrode regions are uniformly distributed, and each row is cut in the lateral direction, and cut in the longitudinal direction by the number of cascades of the light-emitting epitaxial cells.
  • the reticle design is changed to obtain the effect diagram of FIG. 20: each LED
  • the light-emitting epitaxial cells are distributed in rows (columns) in which the P, N electrode regions of the electrode pad layer of the odd-numbered row (column) and the P, N electrode regions of the electrode pad layer of each of the even rows (columns) are reversed distributed.

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Abstract

一种集成LED发光器件及其制作方法。所述集成LED发光器件，包括：至少两个以上相互分离的LED发光外延单元（110），包含上下两个表面，其上表面为出光表面；电极焊盘层（130），形成于所述LED发光外延单元（110）下表面，具有足够的厚度以支撑所述LED外延单元（110）并连接所述各个LED发光外延单元（110），形成一无高低落差之平面的联接电路；所述电极焊盘层划分为P、N电极区（130ρ、130n）。所述各LED发光外延单元（110）构成串联、并联或串并联电路。可改善封装焊接、电极遮光及连线稳定差等问题。

Description

集成LED发光器件及其制作方法
本申请主张如下优先权：中国发明专利申请号201310196146.3，题为 ' 集成LED发光器件及其制作方法 ' ，于 2013 年 5 月 24 日提交。上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体照明器件技术领域，具体涉及一种集成 LED 发光器件以及制作方法。
背景技术
近年来随着半导体照明技术突飞猛进， LED 芯片与封装及后续模组灯具等技术难点一个个被攻破；目前主流的照明封装方式基本采用多颗芯粒构成串联或者串并联的结构，如此需要多颗 LED 芯粒，在封装过程中会对每颗 LED 芯片进行固晶、打线、涂荧光粉等操作，操作较为繁琐。
为解决上述问题，前人提出高压 LED 芯片理念，并在实际应用中，实现其优势，但传统高压芯片仍然存在封装焊接无改善，电极遮光以及芯粒中的各颗 LED 连线稳定性差等问题。
发明内容
本发明提出一种集成 LED 发光器件及其制作，其可以有效改善封装焊接、电极遮光及连线稳定差等问题。
根据本发明的第一个方面，集成 LED 发光器件，包括：至少两个以上相互分离的 LED 发光外延单元，包含上下两个表面，其上表面为出光表面；电极焊盘层，形成于所述 LED 发光外延单元下表面，具有足够的厚度以支撑所述 LED 外延单元并连接所述各个 LED 发光外延单元，形成一无高低落差之平面的联接电路；所述电极焊盘层划分为 P 、 N 电极区。
所述各 LED 发光外延单元构成串联、并联或串并联电路。
所述发光器件可直接应用于 SMT 封装，其通过所述电极焊盘层封装于承载基板上。
在一些实施例中，所述电极焊盘层通过电铸形成。
在一些实施例中，所述电极焊盘层的厚度为 50 μ m 以上，以支撑外延薄膜。
在一些实施例中，所述电极焊盘层的 P 、 N 电极区的面积基本等大。
在一些实施例中，所述电极焊盘层与 LED 发光外延单元之间还设置有至少一绝缘层，用于调整所述电极焊盘层 P 、 N 电极区的分布。
在一些实施例中，所述电极焊盘层与薄膜 LED 发光外延单元之间还设置有至少两层绝缘层，其中第一绝缘层实现各个薄膜 LED 发光外延单元的 P 、 N 区域的隔离，第二绝缘层实现所述电极焊盘层的 P 、 N 电极区基本等大。
在一些实施例中，还包括绝缘体，其插入所述电极焊盘层，将各个 LED 发光外延单元下方的电极焊盘层划分为 P 、 N 两个区域，其下表面不高于所述电极焊盘表面。所述极焊盘层的 P 、 N 区域通过所述绝缘体实现电隔离，其间隙可为 20~100 μ m 。进一步地，在较佳的实施例中，所述绝缘体远离外延叠层的一端表面与所述电极焊盘层表面与所述电极焊盘层的下表面的高度差为 20~100 μ m 。在一些实施例中，所述绝缘体的熔点或软化点低于所述 P 、 N 电极焊盘的熔点，其材料可选用胶体材料，如 SU8 ， BCB 或干膜等。在另一些较佳实施例中，所述电极焊盘层和绝缘体占满所述 LED 外延结构的整个表面。
在上述发光器件中，单颗薄膜 LED 中的 P 型焊盘与相邻独立的 LED 发光单元中的 N 型焊盘相联接形成于下表面，且联接电路为一无高低落差之平面。
根据本发明的第二个方面，集成 LED 发光器件的制作方法，步骤如下：
外延生长：采用外延生长工艺在生长衬底上形成 LED 发光外延叠层；
制作电极焊盘层：在所述 LED 外延叠层表面定义切割道，其将所述 LED 外延叠层分隔为一系列发光单元，各个单元的表面划分为 P 、 N 电极区及隔离区；在所述 LED 外延叠层之制作电极焊盘层，其覆盖所述切割道及 P 、 N 电极区，并具有足够的厚度以支撑所述 LED 发光外延叠层；移除生长衬底，并去除所述切割道的 LED 发光外延叠层，从而形成一系列由所述电极焊盘层连接的 LED 发光外延单元；
器件切割：将上述形成的结构根据需要沿切割道进行切割，形成一系列由若干 LED 发光外延单元构成的集成 LED 发光器件，所述相邻薄膜 LED 发光外延单元之间的 P 、 N 联接电路为
具体地，所述芯片制作步骤中可以通过电铸形成所述电极焊盘层。
在一些实施例中，在所述述 LED 外延叠层的隔离区制作绝缘体以分隔电极焊盘层的 P 、 N 电极区，其远离外延叠层的一端表面与所述电极焊盘层表面齐平或高于所述电极焊盘层的表面。所述极焊盘层的 P 、 N 电极区域通过所述绝缘体实现电隔离，其间隙可为 20~100 μ m 。
在一些实施例中，所述制作电极焊盘层步骤包括：在所述电极焊盘层与薄膜 LED 发光外延单元之间形成至少两层绝缘层，其中第一绝缘层实现各个薄膜 LED 发光外延单元的 P 、 N 电极区的隔离，第二绝缘层实现所述电极焊盘层的 P 、 N 区域基本等大。
在一些实施例中，在制作电极焊盘层中，每个单元上电极焊盘层的 P 、 N 电极区分布一致，在切割步骤中，通过去除部分切割道相应的电极焊盘层从而形成一系列串联、并联或串并联连接的 LED 发光单元阵列。
在一些实施例中，在制作电极焊盘层中，所述每个 LED 发光外延单元按行（列）分布，其中奇数行（列）的电极焊盘层的 P 、 N 电极区与偶数行（列）的每个单元上电极焊盘层的 P 、 N 电极区反向分布，在切割步骤中，通过去除部分切割道相应的电极焊盘层从而形成交流电路连接。
在本发明中，集成 LED 发光器件具备一般高压串联芯片及串并联芯片的优点，有助于提升包括供电电源在内的整个发光器件的电光效率。该集成 LED 发光器件，节省了封装体材料，在制作成本上有优势；由于 LED 外延直接贴在焊盘上，相比一般贴片封装体散热效果更加；另外，整体器件面积相对贴片封装体相对较小。该集成 LED 器件亦可在芯片切割前涂布荧光粉，制成晶圆级白光发光器件，形成一单纯的零组件，更有利于批量化使用。在热处理上，减少了封装体的热阻，使集成 LED 器件能够有更好的散热，较佳的热处理能够增加 LED 器件的使用寿命。
本发明集成 LED 发光器件的结构实现了发光与线路分开进行的结构设计，使用此结构设计能够轻易的得到多重的串并结构，并且与一般的高压式串联芯片相比，无需通过高低的串联线路而可能使电路产生失效，且通过此结构设计能够避免电路的设计产生表面遮光的限制。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图 1 为本发明实施例 1 之一种集成 LED 发光器件的结构剖面图。
图 2 为图 1 所示发光器件的仰视图及等效电路。
图 3 为实施例 2 之一种集成 LED 发光器件的结构剖面图。
图 4 为实施例 3 之一种集成 LED 发光器件的结构剖面图。
图 5 为实施例 4 之一种集成 LED 发光器件的结构剖面图。
图 6 为沿图 5 之线 A-A 剖开的截面图。
图 7~18 为制备图 5 所示的发光器件的过程示意图 . 。
图 19 显示了实施例 4 的第一种变型实施例。
图 20 和 21 显示了实施例 4 的第二种变型实施例。
具体实施方式
下面将结合示意图对本发明的集成 LED 发光器件的方法进行更详细的描述，本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有利效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于，提供一种集成 LED 发光器件及其制作方法，在器件结构上通过电极焊盘层支撑所述发光外延结构并连接所述各个 LED 发光外延单元，形成一无高低落差之平面的联接电路，形成的发光器件可直接贴面安装于承载基板上；在制作方法上，单一化的 LED 发光外延单元通过电极焊盘层支撑并起到电性联接，最后根据器件需要切割电极焊盘层即可形成一无高低落差的平面联接电路的集成 LED 发光器件。
以下结合核心思想，详细说明本发明所述 SMT 发光器件及其制作方法。
实施例 1
在本实施例中，为化简附图及方便说明，取三个 LED 发光单元构成集成 LED 发光器件，应该知道的是本发明并不以此为限，可以根据具体实施需要选择发光单元的个数。
请参看附图 1 ，集成 LED 发光器件，包括：发光外延单元 110 ，欧姆接触层 121 、 122 ，电极焊盘层 130 ，绝缘体 140 。具体地，各个发光外延单元 110 通过隔离道 150 实施外延层的相互隔离，在一较佳实施例中，可在隔离道 150 中填充绝缘材料。发光外延单元 110 为倒装薄膜结构，至上而下包括 N 型外延层、发光层、 P 型外延层，但不限制于此。 N 型欧姆接触层 121 和 P 型欧姆接触层 122 分别位于 N 型外延层和 P 型外延层上且下表面齐平，其材料可选用 Ti 、 Ni 、 Ag 、 Pt 、 Au 、 Cr 或 TiW 的一种或其组合，作为一个较佳的实施方式，采用具有高反射性的金属材料的多层结构，其一方面可作为欧姆接触，另一方面起到镜面反射作用。电极焊盘层 130 分别位于 P 、 N 型欧姆接触层上，其厚度为 50 μ m 以上，以保证支撑前述倒装薄膜结 110 ，较佳值为 70~150 μ m 。电极焊盘 130 的材料可为 Ti 、 Ni 、 Cu 、 Au 、 AuSn 、 SnCu 、 SnBi 的一种或其组合。绝缘体 140 位于 P 、 N 电极焊盘 130p 、 130n 之间并填充 N 型欧姆接触层 121 和 P 型欧姆接触层 122 之间的间隙，呈台阶状，其材料可为永久绝缘胶体，如选用 SU8 ， BCB 或干膜等。
在本实施例中，在各个 LED 发光单元中，电极焊盘层 130 之 P 区 130p 和 N 区 130n 的间隙 D 为 20~150 μ m ，除首尾 LED 发光单元外，各个 LED 发光单元电极焊盘层的 P 区与相邻的 LED 发光单元的电极焊盘层的 N 区连成一片，对应的各个 LED 发光单元电极焊盘层的 N 区与相邻的 LED 发光单元的电极焊盘层的 P 区连成一片，实现一个无高低落差有电路联接平面。进一步地，电极焊盘层的边缘超出外延结构的边缘，其超出距离控制在 30 μ m 以上，防止器件在后续封装时因锡膏的回流导致锡膏爬上外延层导致器件漏电。
附图 2 为图 1 所示器件的仰视图及等效电路， P 和 N 表示了电极焊盘层的 P 、 N 区域。每个 LED 发光单元通过电极焊盘层构成了一个串联电路连接。进一步地，在器件中电极焊盘层 130 和绝缘体 140 占满 LED 外延结构的整个表面，其保证了外延结构支撑的完整性，可以有效防止倒装外延薄膜的损坏。
实施例 2
在一些大尺寸的发光器件中，电极焊盘层 P 、 N 区的形状及大小会成为影响器件可靠性的重要因素之一，如在习知技艺的非对称式电极设计，在共晶制程中因电极面积大小差异过大可能导致芯片倾斜，在面积相对较小的电极处产生共晶失效，最后导致电性连接失败。
请参看附图 3 ，本实施例与实施例 1 的主要区别在于：电极焊盘层的 P 、 N 区 130p 、 130n 的面积接近或基本相同。具体通过下面方式实现：在 P 、 N 欧姆接触层 122 、 121 上设置绝缘层 160 ，并使 N 型欧姆接触层 121 与 LED 外延结构的发光层和 p 型外延层实现电绝缘。在绝缘层 160 上对应 P 、 N 欧姆接触层的位置上开孔，电极焊盘层填充通过该开孔结构，其 P 、 N 区域分别与 P 、 N 欧姆接触层接触。
实施例 3
在本实施例中，绝缘体 140 远离发光外延叠层的一端下表面突出电极焊盘层 130 的下表面，有效防止了在器件在后面封装工艺中的 P 、 N 电极短路问题。假设电极焊盘层 130 下表面的相对位置与绝缘体的下表面的相对位置的高度差为 H ，电极焊盘层的 P 、 N 区的间隙 D ，通过调整 H 和 D 的大小可以优化本实施例的实施效果。在本实施例中，高度差 H 可为 20 ~100 μ m ，优选 50 μ m ，间隙 D 可为 20~100um ，优选 50 μ m 。
实施例 4
本实施例对实施例 2 中 LED 外延层的电流注入结构进行优化，其与实施例 2 的主要区别在于：在 P 、 N 欧姆接触层与电极焊盘层之间设置双绝缘层和导电层结构，其中第一绝缘层与导电层实现电流均匀注入 LED 外延结构，第二绝缘层实现所述 P 、 N 电极焊盘的面积基本相同。请参看附图 5 和附图 6 ，其中附图 6 为沿第一绝缘层 161 的剖开的截面图，在各个 LED 发光外延结单元 110 的中央区域开复数个第一孔洞结构，其穿过 P 型外延层和发光层至 N 型外延层，在 P 型外延层的表面上覆盖欧姆接触层 120 ，在欧姆接触层 120 上覆盖第一绝缘层 161 ，其同时覆盖孔洞结构的侧壁，露出 N 型外延层；在第一绝缘层 161 对应的欧姆接触层 120 的位置上至少开一个第二孔洞结构；在第一绝缘层 161 上制作导电层，其划分为 N 导电区 170n 和 P 导电区 170p ，其中 N 导电区 170n 通过第一孔洞结构与 N 型外延层接触， P 导电区 170p 通过第二孔洞结构与欧姆接触层 120 接触；在导电层上制作第二绝缘层 162 ，并分别在 N 导电区 170n 和 P 导电区 170p 对应的位置开第三孔洞结构，电极焊盘层填充通过该开孔结构，其 P 、 N 区域分别与导电层的 P 、 N 导电区接触。
图 7~17 为制备图 5 所示的发光器件的过程示意图，其主要包括三大工艺步骤：外延生长，芯片制作，切割。其中图 9~16 为图 8 之 B 区域的局部放大剖面图。
首先进行外延生长，具体为：提供生长衬底 100 ，在其上依次成长缓冲层、 N 型外延层、发光层、 P 型外延层，此外延堆叠层命名为 110 ，如图 7 所示。在此步骤中可采用常规外延生长工艺进行即可，如 MOCVD 。
接下来进行芯片制作工艺，包括台面蚀刻、制作欧姆接触层、制作绝缘体、制作电极焊盘等。具体如下：
1 ）按照 LED 发光外延单元的尺寸在在 LED 外延叠层 110 表面的定义切割道区 150 ，将 LED 外延叠层分隔为一系列发光单元 100 ，如图 8 所示；
2 ）进行台面蚀刻：利用黄光微影技术图案化外延叠层 110 ，利用 ICP 干法刻蚀在各个 LED 发光外延单元 110 的中央区域开复数个第一孔洞结构 181 ，其穿过 P 型外延层和发光层至 N 型外延层，如图 9 所示；
3 ）在 p 型外延层表面上形成欧姆接触层 120 ，如图 10 所示，欧姆接触层 120 的材料可为高反射 P 型欧姆接触材料，具体可包含 Cr 、 Ag 、 Ni 、 Al 、 Pt 、 Au 、 Ti 的一种或者多种，总体厚度不小于 0.5um ，最佳厚度为 1um ；
4 ）在欧姆接触层 120 及第一孔洞结构 181 的侧壁形成第一绝缘层 161 ，露出第一孔洞结构 181 的底面处的 N 型外延层，在各个 LED 发光单元的第一绝缘层 161 上对应欧姆接触层 120 的位置上至少开一个第二孔洞结构 182 ，如图 11 所示；
5 ）在第一绝缘层 161 上制作导电层，在各个发光单元上该导电层由相互电隔离的 N 导电区 170n 和 P 导电区 170p ，其中 N 导电区 170n 填充第一孔洞结构 181 并与 N 型外延层接触， P 导电区 170p 填充第二孔洞结构 182 并与欧姆接触层 120 接触，如图 12 所示；
6 ）在导电层上制作第二绝缘层 162 ，并分别在导电层 N 导电区 170n 和 P 导电区 170p 对应的位置开第三孔洞结构 183 ，如图 13 所示；
7 ）利用电镀技术，在第二绝缘层 162 上制作电极焊盘层 130 ，以各个发光单元 110 为单位，电极焊盘层 130 划分为相互电隔离的 N 电极区 130n 和 P 电极区 130p ， P 、 N 两电极区之间填充绝缘材料作为绝缘体 140 ，除首尾 LED 发光单元外，各个 LED 发光单元电极焊盘层的 P 电极区与相邻的 LED 发光单元的电极焊盘层的 N 电极区连成一片，实现一个无高低落差有电路联接平面，如图 14 所示。电镀材料可选为 Ni 、 Cu 、 Au 等能与 Sn 共熔的金属材料，其厚度不少于 50um ，并形成可支撑发光外延结构的电镀层；
8 ）如图 15 所示，采用已知衬底剥离技术去除生长衬底 001 ，露出发光外延叠层的表面；
9 ）利用 ICP 干法刻去除切割道区 150 的发光外延叠至露出第一绝缘层 161 ，形成一系列由所述电极焊盘层连接的 LED 发光外延单元，如图 16 所示。
至此发光外延叠层由切割道 150 划分了一系列彼此隔离的独立单元。请附看图 17 ，每个单元的电极焊盘层 P 电极区与其左边单元的电极焊盘层 N 电极区相接、与其上方及下方的单元的电极焊盘层 P 电极区相接；每个单元的电极焊盘层 N 电极区与其右边单元的电极焊盘层 P 电极区相接、与其上面及下面的单元的电极焊盘层 P 电极区相接，绝缘体 140 呈不间断线条分布。
最后进行芯片切割，请参看附图 18 ，按（ a ）中箭头方向沿切割道切割芯粒，形成一系列由若干 LED 发光外延单元构成的集成 LED 发光器件。其等效电路如（ b ）所示。在本实施例中，每个 LED 发光外延单元按行分布，每行的电极焊盘层的 P 、 N 电极区的分布一致，在横向上每行进行切割，在纵向上按发光外延单元串接的个数进行切割。
变形实施例 1
请参看附图 19 ，按箭头线为切割芯粒，可得到 2*3 颗 LED 串并联的组合，等效电路如图中所示。
变形实施例 2
在本实施例中变更光罩设计获得图 20 的效果图：每个 LED 发光外延单元按行（列）分布，其中奇数行（列）的电极焊盘层的 P 、 N 电极区与偶数行（列）的每个单元上电极焊盘层的 P 、 N 电极区反向分布。
请参考 14 所示，按箭头线为切割芯粒，可得到 2*2 颗 LED 串并联的组合，等效电路如图中所示。

Claims (18)

  1. 集成 LED 发光器件，包括：
    至少两个以上相互分离的 LED 发光外延单元，包含上下两个表面，其上表面为出光表面；
    电极焊盘层，形成于所述 LED 发光外延单元下表面，具有足够的厚度以支撑所述 LED 外延单元并连接所述各个 LED 发光外延单元，形成一无高低落差之平面的联接电路；所述电极焊盘层划分为 P 、 N 电极区。
  2. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述电极焊盘层直接用于 SMT 封装。
  3. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：还包括绝缘体，其插入所述电极焊盘层，将各个 LED 发光外延单元下方的电极焊盘层划分为 P 、 N 两个区域，其下表面不高于所述电极焊盘表面。
  4. 根据权利要求 2 所述的集成 LED 发光器件，其特征在于：所述绝缘体下表面与所述电极焊盘层的下表面的高度差为 20~100 μ m 。
  5. 根据权利要求 2 所述的集成 LED 发光器件，其特征在于：所述绝缘体的熔点或软化点低于所述电极焊盘层的熔点。
  6. 根据权利要求 2 所述的集成 LED 发光器件，其特征在于：所述绝缘体的材料选用胶体材料。
  7. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述电极焊盘层的厚度为 50 μ m 以上，以支撑所述 LED 发光外延单元。
  8. 根据权利要求 8 所述的集成 LED 发光器件，其特征在于：所述电极焊盘层与 LED 发光外延单元之间还设置有至少一绝缘层，用于调整所述电极焊盘层 P 、 N 电极区的分布。
  9. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述电极焊盘层的 P 、 N 电极区的面积基本相同。
  10. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述 P 、 N 电极焊盘和绝缘体占满所述 LED 外延结构的整个表面。
  11. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述 P 、 N 电极焊盘的边缘超越 LED 发光外延边缘。
  12. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述极焊盘层的 P 、 N 区域通过所述绝缘体实现电隔离，其间隙为 20~100 μ m 。
  13. 根据权利要求 1 所述的集成 LED 发光器件，其特征在于：所述各个 LED 发光外延单元构成串联、并联或串并联电路。
  14. 集成 LED 发光器件的制作方法，步骤如下：
    外延生长：采用外延生长工艺在生长衬底上形成 LED 发光外延叠层；
    芯片制作：在所述 LED 外延叠层表面的定义切割道，其将所述 LED 外延叠层分隔为一系列发光单元，各个单元的表面划分为 P 、 N 电极区及隔离区；在所述 LED 外延叠层之制作电极焊盘层，其覆盖所述切割道及 P 、 N 电极区，并具有足够的厚度以支撑所述 LED 发光外延叠层；移除生长衬底，并去除所述切割道的 LED 发光外延叠层，从而形成一系列由所述电极焊盘层连接的 LED 发光外延单元；
    器件切割：将上述形成的结构根据需要沿切割道进行切割，形成一系列由若干 LED 发光外延单元构成的集成 LED 发光器件，所述相邻薄膜 LED 发光外延单元之间的 P 、 N 联接电路为一无高低落差的平面。
  15. 根据权利要求 14 所述的集成 LED 发光器件的制作方法，其特征在于：在芯片制作中，在所述 LED 外延叠层的隔离区制作绝缘体以分隔电极焊盘层的 P 、 N 电极区，其远离外延叠层的一端表面与所述电极焊盘层表面齐平或高于所述电极焊盘层的表面。
  16. 根据权利要求 14 所述的集成 LED 发光器件的制作方法，其特征在于：在芯片制作中，所述形成的 P 、 N 电极焊盘的边缘超越 LED 发光外延边缘。
  17. 根据权利要求 14 所述的集成 LED 发光器件的制作方法，其特征在于：在芯片制作中，每个单元上电极焊盘层的 P 、 N 电极区分布一致，在切割步骤中，通过去除部分切割道相应的电极焊盘层从而形成一系列串联、并联或串并联连接的 LED 发光单元阵列。
  18. 根据权利要求 14 所述的集成 LED 发光器件的制作方法，其特征在于：在芯片制作中，所述每个 LED 发光外延单元按行（列）分布，其中奇数行（列）的电极焊盘层的 P 、 N 电极区与偶数行（列）的每个单元上电极焊盘层的 P 、 N 电极区反向分布，在切割步骤中，通过去除部分切割道相应的电极焊盘层从而形成交流电路连接。
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