WO2013044817A1 - 一种倒装集成发光二极管及其制备方法 - Google Patents

一种倒装集成发光二极管及其制备方法 Download PDF

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WO2013044817A1
WO2013044817A1 PCT/CN2012/082117 CN2012082117W WO2013044817A1 WO 2013044817 A1 WO2013044817 A1 WO 2013044817A1 CN 2012082117 W CN2012082117 W CN 2012082117W WO 2013044817 A1 WO2013044817 A1 WO 2013044817A1
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electrode
type semiconductor
semiconductor layer
region
layer
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PCT/CN2012/082117
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English (en)
French (fr)
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吴厚润
黄少华
吴志强
邹博闳
邓有财
林科闯
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厦门市三安光电科技有限公司
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Publication of WO2013044817A1 publication Critical patent/WO2013044817A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to a light emitting diode and a manufacturing method thereof, and more particularly to a flip-chip integrated light emitting diode and a preparation method thereof.
  • LED Light Emitting Diode
  • P-N A semiconductor light-emitting device made by the principle of junction electroluminescence, in order to make LEDs widely used in public places such as road lighting, LED
  • the luminous flux of a light source must reach several thousand or even tens of thousands of lumens.
  • Such high light output cannot be achieved by a single chip.
  • the first method uses multiple LEDs that are made.
  • the chip meets the requirements of high-brightness illumination through subsequent series connection of leads, which solves the problem of insufficient single light source to some extent.
  • the second method is to integrate a plurality of series-connected light-emitting diodes into one chip to form a light-emitting device. It can work directly under a high voltage DC voltage or AC voltage and has been widely used.
  • Chinese patent CN03820622.6 discloses an integrated light-emitting device which is formed in two-dimensional monolithic form on an insulating substrate such as sapphire
  • the LEDs form an array with overhead bridges between individual LEDs and between the LEDs and the electrodes. By means of a zigzag LED
  • the array achieves high drive voltage and low drive current.
  • Such an integrated light-emitting device has various problems including low luminous efficiency, low heat dissipation, low power, and reliability.
  • Each individual LED is adjacent to it LED isolation by etching the N-type semiconductor layer to the insulating substrate 1 The surface is implemented.
  • the tandem metal wire needs to cross the ditch with a large height drop, which is prone to the problem of disconnection of the metal wire in the fabrication, which causes the problem that the whole diode cannot be connected.
  • Chinese patent CN200580042802.8 discloses another flip-chip integrated chip which will have multiple LEDs Bonded to the secondary carrier substrate. Since the P and N electrodes are formed on the p-type semiconductor layer and the n-type semiconductor layer, respectively, P and N The electrode height difference is large, and after flip-chip bonding to the secondary carrier substrate, the peeling yield of the growth substrate will be affected. To make the P, N electrodes the same height, it is necessary to go through a number of electrode formation processes or to add a planarization process.
  • the present invention provides a flip-chip integrated light-emitting diode and a preparation method thereof, which improve the heat dissipation problem, strengthen the stability of the metal wire layer for series connection, and improve light extraction. effectiveness.
  • a flip-chip integrated light emitting diode includes: a substrate with a metal wiring array; and an electrically isolated LED An array is flip-chip formed on the substrate and connected to the metal wiring array on the substrate; each LED includes an illuminating epitaxial layer composed of an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, an N electrode and a P An electrode, the epitaxial layer is defined as a light-emitting region and an N-electrode region, and the p-type semiconductor layer and the active layer of the light-emitting region are respectively associated with the p-electrode region
  • the semiconductor layer is separated from the active layer, and the upper surface of the entire light-emitting region is flush with the upper surface of the entire N-electrode region; the n-type semiconductor layer of the N-electrode region is short-circuited with the p-type semiconductor layer to form an N-electrode, A P electrode is formed on the p-type
  • a method for fabricating an integrated light emitting diode includes the following process steps: 1) providing a growth substrate; Depositing an illuminating epitaxial layer on the growth substrate, the bottom layer including the n-type layer, the active layer and the p-type layer; 3) separating the luminescent epitaxial layer into mutually electrically isolated LED arrays; 4)
  • the epitaxial layer is defined as a light-emitting region and an N-electrode region, and the p-type semiconductor layer and the active layer of the light-emitting region are respectively separated from the p-type semiconductor layer and the active layer of the N-electrode region, and the upper surface of the entire light-emitting region With the whole N The upper surface of the electrode region is flush; the n-type semiconductor layer and the p-type semiconductor layer of the N electrode region are short-circuited to form an N electrode; and a P electrode is formed on the p-type semiconductor layer of the light-emitting region; Providing
  • the invention changes the N-electrode of the conventional flip-chip integrated light-emitting diode, and the P-type semiconductor layer and the active layer are first etched, and formed on the n
  • the semiconductor type method first defines an N electrode region and a light emitting region in an LED light emitting epitaxial layer, and an active layer of the N electrode region, a P-type semiconductor and an active layer of the light-emitting region, P
  • the type semiconductor is isolated, and the n-type semiconductor layer and the p-type semiconductor layer in the N-electrode region are short-circuited, and the P electrode and the N electrode are formed on the P-type semiconductor layer of the light-emitting region and the N-electrode region, respectively, so that P
  • the N electrode is at the same height, and the P electrode and the N electrode occupy almost the entire chip to improve the yield of the flip-chip bonding and the laser stripping growth substrate; and the large-area electrode is used for eutectic soldering to further enhance the heat
  • FIG. 1 is a schematic structural view of a flip-chip integrated light emitting diode according to an embodiment of the invention.
  • FIGS. 2 to 11 are cross-sectional views showing a manufacturing process of a half-integrated light emitting diode according to an embodiment of the present invention.
  • 010 growth substrate; 020: support substrate; 100: LED unit; 110: N-type semiconductor layer; 120: active layer; 130: p-type semi-conductive layer; 200: metal wiring 210: N electrode; 220: P electrode; 300: metal wiring; 310, 320: metal wiring terminal; 400: roughened surface; 500: insulating layer; 600: channel; 700: isolation trench; area A: light-emitting area; area B: n electrode area.
  • a flip-chip integrated LED As shown in Figure 1, a flip-chip integrated LED, a series of isolated LED units 100 It is integrated on the support substrate 020 by flip chip soldering or other connection, and is connected in series through the metal wiring 300 on the substrate.
  • Support substrate 020 A material having good thermal conductivity and high electrical resistance may be aluminum nitride, boron nitride, or other similar materials, and the PN of the LED unit 100 in each light emitting diode The heat generated by the junction can be easily transferred to the substrate 020 and distributed to the outer casing.
  • the metal wiring 300 array is fabricated on the support substrate 020, and the metal wiring 300 will be an LED unit 100 P
  • the electrode 220 is connected to the N electrode 210 of its adjacent LED unit 100 such that the entire LED array is connected in series via the support substrate 020. Terminals 310 and 320 A power connection point is provided for each end of the LED array.
  • the material of the metal wiring 300 may be selected from one of Au, Sn, In, or a combination thereof.
  • the array can be fabricated on a growth substrate using a standard integrated chip fabrication process, connected to the metal wiring by a flip chip soldering process, and then the growth substrate removed. There is a channel between adjacent LED units 100.
  • the individual LEDs are electrically isolated from each other throughout the entire epitaxial layer.
  • Each of the LED units 100 includes an n-type semiconductor layer 110, an active layer 120, and a p-type semiconductor layer 130.
  • the luminescent epitaxial layer is composed of an N electrode 210 and a P electrode 220.
  • the luminescent epitaxial layer is generally mesa-shaped and is defined as the illuminating region A and the N electrode region B, and the illuminating region A p
  • the type semiconductor layer 130 and the active layer 120 are separated from the p-type semiconductor layer 130 and the active layer 120 of the N electrode region B by the insulating layer 500.
  • Insulation layer 500 The material may be one or a combination of SiO2, Si3N4, TiO2, Ti2O3, Ti3O5, BCB (benzocyclobutene resin) materials.
  • Wired through metal 200 is connected to the n-type semiconductor layer 110 of the N electrode region B and the p-type semiconductor layer 130 to form a short-circuit connection, and the light-emitting epitaxial layer of the entire N electrode region B after the short-circuit connection is used as N Electrode 210.
  • the P electrode 220 is formed on the p-type semiconductor layer 130 of the light-emitting region A.
  • the material of the metal wire 200 and the P electrode 220 may be selected from Cr, Pt, One of or a combination of metals such as Ni, Au, Ag, Al, Ti, W, and Sn.
  • the n-type semiconductor layer 110 may be a roughened surface 400, reducing the reflection of the surface light. Further, in order to improve the light extraction efficiency, a light-reflecting metal layer (not shown) is incorporated in the P electrode, and the light emitted to the support substrate 020 is reflected back to n. Type semiconductor layer.
  • FIG. 2 to 11 illustrate a fabrication process of a flip-chip integrated light emitting diode according to the present invention, which mainly includes an epitaxial growth process, LED Cell separation, electrode fabrication process, flip chip soldering process, etc.
  • a growth substrate 010 is provided, and a light-emitting epitaxial layer is deposited on the growth substrate, and the bottom surface includes n Type semiconductor layer 110, active layer 120 and p-type semiconductor layer 130 .
  • the growth substrate may be transparent, translucent, or have similar light transmission properties, but may also be non-translucent, and specifically, materials such as sapphire, silicon carbide, silicon, gallium arsenide, or the like may be used.
  • the deposited luminescent epitaxial layer can be a general epitaxial growth process.
  • Next step Define the LED unit size and divide the illuminating epitaxial layer into LED arrays, each LED unit 100 Electrically isolated from each other.
  • the reticle pattern illuminates the epitaxial layer to define the LED cell region and the insulating region.
  • the luminescent semiconductor layer of the insulating region may be removed by etching to form a trench 600, and the cross-sectional view thereof is as shown in FIG. Shown.
  • the semiconductor material layer of the isolation region may not be removed, instead of the semiconductor material layer of the high-resistance insulating region, such as ion implantation to implant specific ions into the surface of the substrate to make the insulating region high-resistance. , can also be separated LED unit.
  • the light-emitting area A and the N-electrode area B of the LED unit 100 are defined in the N-electrode area.
  • the p-type semiconductor layer 130 and the active layer 120 are etched between the B and the light-emitting region A to form the isolation trench 700. Its attached view is shown in Figure 5.
  • Next step as shown in Fig. 6, short-circuiting the n-type semiconductor layer 110 and the p-type semiconductor layer 130 of the N electrode region B
  • the N electrode 210 is formed; a P electrode 220 is formed on the p-type semiconductor layer 130 of the light-emitting region A.
  • the specific method of making the N electrode making a metal wire 200, and connecting it The n-type semiconductor layer 110 and the p-type semiconductor layer 130 of the N electrode region B, the n-type semiconductor layer 110 and the p-type semiconductor layer 130 of the N electrode region B A short-circuit connection is formed, and the light-emitting epitaxial layer of the entire N-electrode region after the short-circuit connection can be used as the N electrode.
  • the material of the metal wire 200 and the P electrode 220 may be selected from Cr, Pt, Ni, One of or a combination of metals such as Au, Ag, Al, Ti, W, and Sn.
  • an insulating layer is formed in the isolation trench 700 to ensure the p-type semiconductor layer 130 of the light-emitting region A.
  • the active layer 120 is separated from the p-type semiconductor layer 130 and the active layer of the N electrode region B, respectively.
  • a support substrate 020 is provided on which a metal wiring array is formed.
  • Each metal wiring 300 Electrically isolated from each other.
  • the support substrate 020 and the LED array are flip-chip soldered to form a flip-chip integrated LED.
  • the P electrode 230 and the N electrode 210 are connected to the metal wiring 300 array on the substrate, and the P electrode 230 of the LED electrically isolated from each other and the N electrode of the adjacent LED 210 connected.
  • the growth substrate can be removed or thinned. Its cross-sectional view is shown in Figure 10. Further, as shown in Figure 11 As shown, in order to achieve better light extraction efficiency, the light-emitting surface can be roughened.

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Abstract

本发明公开了一种倒装集成发光二极管及其制备方法。一种倒装集成发光二极管：包括一个带有金属布线阵列的基板；一个相互电隔离的LED阵列倒装形成于所述基板上，与基板上的金属布线阵列连接；每个LED包括由n型半导体层、有源层、p型半导体层组成的发光外延层，N电极和P电极，所述外延层被定义为发光区和N电极区，所述发光区的p型半导体层和有源层分别与N电极区的p型半导体层和有源层分隔开；N电极区的n型半导体层与p型半导体层形成短路连接从而构成N电极，P电极形成于发光区的p型半导体层上；所述的金属布线阵列使相互电隔离的LED的P电极和其相邻的LED的N电极相连。

Description

一种倒装集成发光二极管及其制备方法
本申请要求于 2011 年9月 30 日 提交中国专利局、申请号为201110296970.7、发明名称为“一种倒装集成发光二极管及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本发明涉及一种发光二极管及其制作方法 , 更具体地为涉及一种倒装集成发光二极管及其制备方法。
发光二极管（英文为 Light Emitting Diode, 简称 LED ）是利用半导体 P-N 结电致发光原理制成的一种半导体发光器件，要使 LED 大规模应用于道路照明等公众场所， LED 光源的光通量必须达到几千甚至上万流明，如此高的光输出量无法通过单颗芯片来实现。为满足如此高的光输出要求，可以采用两种方法。第一种方法采是用多颗制作好的 LED 芯片通过后续的引线串联来满足高亮度照明的要求，这种方式在一定程度上解决了单颗光源不足的问题。但是由于 LED 芯片制备和 LED 芯片之间的引线串联是两个独立的步骤，存在制作过程复、可靠性不高、占用空间大、生产效率低等缺点，在一定程度上限制了 LED 芯片在半导体照明节领域的应用与推广。第二种方法是将许多串联连接的发光二极管集成在一个芯片中制成一个发光装置。它可以直接工作在一个高压直流电压或交流电压下，得到了比较广泛的应用。
中国专利 CN03820622.6 公开了一种集成式的发光装置，在蓝宝石等绝缘基板上，以二维单片式形成多个 LED 组成阵列，单个 LED 之间及 LED 与电极之间为架空桥式布线。通过曲折状配置 LED 阵列，获得高驱动电压和低驱动电流。此种集成式的发光装置存在多种问题：包括发光效率低，不易散热，功率低，及可靠性方面的问题。每一个独立的 LED 与其相邻 LED 的隔离是通过刻蚀 N 型半导体层到绝缘衬底 1 的表面来实现的。串联金属线需跨过高度落差极大的沟渠，在制作上容易发生金属线断接的问题，造成整体二极管无法连接的问题。
中国专利 CN200580042802.8 公开了另一种倒装集成芯片，此种倒装集成芯片将多个 LED 接合到次载基板上。由于 P 、 N 电极分别形成于 p 型半导体层和 n 型半导体层上， P 、 N 电极高低落差大，在倒装接合到次载基板后，将影响生长衬底的剥离良率。若要使 P, N 电极同高则需经过较多次的电极形成工艺或者加入平坦化工艺。
针对现在技术中存在的上述问题，本发明提出一种倒装集成发光二极管及其制备方法，其在改善了散热性问题的同时，强化用于串联的金属线层的稳定性，提高了光取出效率。
根据本发明的一方面，一种倒装集成发光二极管，包括：一个带有金属布线阵列的基板；一个相互电隔离的 LED 阵列倒装形成于所述基板上，与基板上的金属布线阵列连接；每个 LED 包括由 n 型半导体层、有源层、 p 型半导体层组成的发光外延层， N 电极和 P 电极，所述外延层被定义为发光区和 N 电极区，所述发光区的 p 型半导体层和有源层分别与 N 电极区的 p 型半导体层和有源层分隔开，且整个发光区的上表面与整个 N 电极区的上表面齐平； N 电极区的 n 型半导体层与 p 型半导体层形成短路连接从而构成 N 电极， P 电极形成于发光区的 p 型半导体层上；所述的金属布线阵列使相互电隔离的 LED 的 P 电极和其相邻的 LED 的 N 电极相连。
根据本发明人另一个方面：一种集成发光二极管的制备方法，其包括如下工艺步骤： 1 ）提供生长衬底； 2 ）在生长衬底上沉积发光外延层，其至下而上包括 n 型层，有源层和 p 型层； 3 ）将发光外延层分隔成相互电隔离的 LED 阵列 ; 4) 将外延层定义为发光区和 N 电极区，所述发光区的 p 型半导体层和有源层分别与 N 电极区的 p 型半导体层和有源层分隔开，且整个发光区的上表面与整个 N 电极区的上表面齐平；短路连接 N 电极区的 n 型半导体层和 p 型半导体层，构成 N 电极；在发光区的 p 型半导体层上形成 P 电极； 5 ）提供基板，其上分布有金属布线阵列； 6 ）将相互电隔离的 LED 阵列倒装焊接在基板上， P 电极与 N 电极与基板上的金属布线阵列连接，且相互电隔离的 LED 的 P 电极和其相邻的 LED 的 N 电极相连。
本发明改变了传统倒装集成发光二极管中 N 电极需先蚀刻 P 型半导体层、有源层，形成于 n 型半导体型上的方法，先在 LED 发光外延层定义出 N 电极区和发光区，将 N 电极区的有源层、 P 型半导体导与发光区的有源层、 P 型半导体导隔离，并且短路 N 电极区的 n 型半导体层和 p 型半导体层，分别在发光区和 N 电极区的 P 型半导体层上制作 P 电极与 N 电极，使得 P 、 N 电极同高，且 P 电极与 N 电极几乎占满整面芯片进而提升倒装键合及激光剥离生长衬底之良率；利用大面积电极做共晶焊接进一步加强散热能力。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图 1 为根据本发明实施例的一种倒装集成发光二极管的结构示意图。
图 2 ～图 11 为根据本发明实施例的一种倒半集成式发光二极管制作流程的剖面图。
图中部件符号说明： 010 ：生长衬底； 020 ：支撑基板； 100 ： LED 单元； 110 ： n 型半导体层； 120 ：有源层； 130 ： p 型半导层； 200 ：金属连线 210 ： N 电极； 220 ： P 电极； 300 ：金属布线； 310 ， 320 ：金属布线端子； 400 ：粗化面； 500 ：绝缘层； 600 ：沟道； 700 ：隔离槽； A 区：发光区； B 区： n 电极区。
本发明的实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
如图 1 所示，一个倒装集成发光二极管，一系列相互隔离的 LED 单元 100 通过覆晶焊接或其他接连方式集成在支撑基板 020 上，通过基板上的金属布线 300 串联起来。
支撑基板 020 选用具有良好的热传导性及高电阻的材料，可以是氮化铝，氮化硼，或其他相近料材，每个发光二极管中的 LED 单元 100 的 PN 结所产生的热量就可以轻易地转移至基板 020 上并散发到外壳上。
金属布线 300 阵列制作在支撑基板 020 上，金属布线 300 将一个 LED 单元 100 的 P 电极 220 与其相邻 LED 单元 100 的 N 电极 210 连接起来，从而使整个 LED 列阵通过支撑基板 020 串联起来。端子 310 和 320 为 LED 阵列的每一端提供了电源连结点。金属布线 300 的材料可选用 Au 、 Sn 、 In 中的一种或其组合。
LED 阵列可以使用标准的集成芯片制作工艺先制作在生长衬底上，通过覆晶焊接工艺连接到金属布线上，然后再去除生长衬底。相邻 LED 单元 100 之间有一条沟道 600 贯穿整个发光外延层，使各个 LED 相互电隔离。每个 LED 单元 100 包括由 n 型半导体层 110 、有源层 120 、 p 型半导体层 130 组成的发光外延层， N 电极 210 和 P 电极 220 。发光外延层一般为台面形的，被定义为发光区 A 和 N 电极区 B ，发光区 A 的 p 型半导体层 130 、有源层 120 通过绝缘层 500 与 N 电极区 B 的 p 型半导体层 130 、有源层 120 分隔开。绝缘层 500 的材料可以为 SiO2 、 Si3N4 、 TiO2 、 Ti2O3 、 Ti3O5 、 BCB( 苯并环丁烯树脂 ) 材料中一种或其结合。通过金属连线 200 连接 N 电极区 B 的 n 型半导体层 110 和 p 型半导体层 130 ，形成短路连接，短路连接后的整个 N 电极区 B 的发光外延层作为 N 电极 210 。 P 电极 220 形成地发光区 A 的 p 型半导体层 130 上。金属连线 200 及 P 电极 220 的材料可选用 Cr 、 Pt 、 Ni 、 Au 、 Ag 、 Al 、 Ti 、 W 、 Sn 等金属中的一种或其组合。
光从 LED 单元 100 的 n 型半导体层 110 发出。 n 型半导体层 110 可以是一个粗化面 400 ，减少了出面光的反射。进一步地，为了提高取光效率，要在 P 电极并入一个高反射金属层（图中未显示），把向支撑基板 020 发射的光反射回 n 型半导体层。
图 2 ～图 11 示意了本发明一种倒装集成发光二极管的制作流程，主要包括了外延生长工艺， LED 单元分隔，电极制作工艺，覆晶焊接工艺等。
第一步：如图 2 所示，提供一生长衬底 010 ，在生长衬底上沉积发光外延层，其至下而上包括 n 型半导体层 110 ，有源层 120 和 p 型半导体层 130 。生长衬底可以是透明、半透明、或具有类似透光的特性，但也可以是非透光性的，具体可使用蓝宝石、炭化硅、硅、砷化镓等材料。沉积发光外延层为一般外延生长工艺即可。
下一步：定义 LED 单元大小，将发光外延层划分为 LED 阵列，每个 LED 单元 100 相互电隔离。首先，光罩图形化发光外延层，定义出 LED 单元区和绝缘区。可采用蚀刻去除绝缘区的发光半导体层，形成沟道 600 ，其剖面示意图如图 3 所示。应该注意的地，可以不去除隔离区的半导体材料层，替代地是高阻化绝缘区的半导体材料层，如采用离子注入法在绝缘区注入特定离子至衬底表面，使绝缘区高阻化，同样地也可以分隔 LED 单元。
下一步：如图 4 所示，定义 LED 单元 100 的发光区 A 、 N 电极区 B ，在 N 电极区 B 与发光区 A 间蚀刻 p 型半导体层 130 和有源层 120 ，形成隔离槽 700 。其附视图如图 5 所示。
下一步：如图 6 所示，短路连接 N 电极区 B 的 n 型半导体层 110 和 p 型半导体层 130 ，构成 N 电极 210 ；在发光区 A 的 p 型半导体层 130 上形成 P 电极 220 。 N 电极的具体制作方法：制作一金属连线 200 ，其连接 N 电极区 B 的 n 型半导体层 110 和 p 型半导体层 130 ，使 N 电极区 B 的 n 型半导体层 110 和 p 型半导体层 130 形成短路连接，短路连接后的整个 N 电极区的发光外延层即可作为 N 电极。金属连线 200 及 P 电极 220 的材料可选用 Cr 、 Pt 、 Ni 、 Au 、 Ag 、 Al 、 Ti 、 W 、 Sn 等金属中的一种或其组合。
下一步：如图 7 所示，在隔离槽 700 中形成绝缘层，保证了发光区 A 的 p 型半导体层 130 、有源层 120 分别与 N 电极区 B 的 p 型半导体层 130 、有源层分隔开。
下一步：如图 8 所示，提供一支撑基板 020 ，在其上形成金属布线阵列。每个金属布线 300 相互彼此电隔离。
下一步：如图 9 所示，将支撑基板 020 与 LED 阵列进行覆晶焊接，形成倒装集成式发光二极管。 P 电极 230 与 N 电极 210 与基板上的金属布线 300 阵列连接，且相互电隔离的 LED 的 P 电极 230 和其相邻的 LED 的 N 电极 210 相连。
完成上述步骤后，可将生长衬底去除或作减薄处理。其剖面示图如图 10 所示。进一步地，如图 11 所示，为了取得更佳的取光效率，可在出光面上作粗化处理。
以上实施例仅供说明本发明之用 , 而非对本发明的限制 , 有关技术领域的技术人员 , 在不脱离本发明的精神和范围的情况下 , 还可以作出各种变换或变化。因此 , 所有等同的技术方案也应该属于本发明的范畴 , 应由各权利要求限定。

Claims (10)

  1. 一种倒装集成发光二极管：包括
    一个带有金属布线阵列的基板；
    一个相互电隔离的 LED 阵列倒装形成于所述基板上，与基板上的金属布线阵列连接；
    每个 LED 包括由 n 型半导体层、有源层、 p 型半导体层组成的发光外延层， N 电极和 P 电极，所述外延层被定义为发光区和 N 电极区，所述发光区的 p 型半导体层和有源层分别与 N 电极区的 p 型半导体层和有源层分隔开，且整个发光区的上表面与整个 N 电极区的上表面齐平； N 电极区的 n 型半导体层与 p 型半导体层形成短路连接从而构成 N 电极， P 电极形成于发光区的 p 型半导体层上；
    所述的金属布线阵列使相互电隔离的 LED 的 P 电极和其相邻的 LED 的 N 电极相连。
  2. 根据权利要求 1 所述的一种倒装集成发光二极管，其特征在于：所述基板选用散热型材料。
  3. 根据权利要求 1 所述的一种倒装集成发光二极管，其特征在于：所述 LED 阵列通过沟道相互电隔离，每个 LED 的 P 、 N 电极几乎占满整个芯片表面。
  4. 根据权利要求 1 所述的一种倒装集成发光二极管，其特征在于：在所述发光区和 N 电极区之间有一绝缘层。
  5. 根据权利要求 1 所述的一种倒装集成发光二极管，其特征在于：所述金属布线材料选用 Au 、 Sn 、 In 中的一种或其组合。
  6. 一种倒装集成发光二极管的制备方法 , 其包括如下工艺步骤：
    1 ）提供一生长衬底；
    2 ）在所述生长衬底上沉积发光外延层，其至下而上包括 n 型半导体层，有源层和 p 型半导体层；
    3 ）将发光外延层分隔成相互电隔离的 LED 阵列；
    4) 将外延层定义为发光区和 N 电极区，所述发光区的 p 型半导体层和有源层分别与 N 电极区的 p 型半导体层和有源层分隔开，且整个发光区的上表面与整个 N 电极区的上表面齐平；短路连接 N 电极区的 n 型半导体层和 p 型半导体层，构成 N 电极；在发光区的 p 型半导体层上形成 P 电极；
    5 ）提供基板，其上分布有金属布线阵列；
    6 ）将相互电隔离的 LED 阵列倒装焊接在基板上， P 电极与 N 电极与基板上的金属布线阵列连接，且相互电隔离的 LED 的 P 电极和其相邻的 LED 的 N 电极相连。
  7. 根据权利要求 6 所述的一种倒装集成发光二极管的制备方法 , 其特征在于：所述基板选用散热型材料。
  8. 根据权利要求 6 所述的一种倒装集成发光二极管的制备方法 , 其特征在于：步骤 3 ）中通过沟道将发光外延层分隔成相互电隔离的 LED 阵列。
  9. 根据权利要求 6 所述的一种倒装集成发光二极管的制备方法 , 其特征在于：步骤 4 ）中通过一隔离槽将发光区的 p 型半导体层和有源层分别与 N 电极区的 p 型半导体层和有源层分隔开。
  10. 根据权利要求 6 所述的一种倒装集成发光二极管的制备方法 , 其特征在于：步骤 4 ）中通过金属连线连接 N 电极区的 n 型半导体层和 p 型半导体层，形成短路连接，短路连接后的整个 N 电极区的发光外延层作为 N 电极。
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