WO2014185086A1 - 電界効果型半導体装置及びその製造方法 - Google Patents

電界効果型半導体装置及びその製造方法 Download PDF

Info

Publication number
WO2014185086A1
WO2014185086A1 PCT/JP2014/051222 JP2014051222W WO2014185086A1 WO 2014185086 A1 WO2014185086 A1 WO 2014185086A1 JP 2014051222 W JP2014051222 W JP 2014051222W WO 2014185086 A1 WO2014185086 A1 WO 2014185086A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor device
sige
source
field effect
Prior art date
Application number
PCT/JP2014/051222
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
雄一 上牟田
佳彦 守山
Original Assignee
独立行政法人産業技術総合研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 独立行政法人産業技術総合研究所 filed Critical 独立行政法人産業技術総合研究所
Publication of WO2014185086A1 publication Critical patent/WO2014185086A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Embodiments described herein relate generally to a field effect semiconductor device having a Ge channel and a SiGe source / drain region and a method of manufacturing the same.
  • MISFET field effect transistors
  • An epitaxial method is used as a method for forming buried SiGe in the source and drain regions.
  • damage to the crystal due to ion implantation is significant, and a high-temperature process is required to restore crystallinity. If the element is manufactured without recovering the crystallinity, carriers are generated due to crystal defects, which causes a leakage current.
  • a high-temperature process is introduced to recover crystallinity, desorption of germanium (II) oxide having a high vapor pressure occurs from the surface, so that device characteristics are deteriorated.
  • a method of performing n-type doping by introducing PH 3 gas or the like when epitaxially growing an embedded SiGe layer in the source and drain regions with respect to Ge can be considered.
  • P is sufficiently introduced into the SiGe layer.
  • the contact resistance with the wiring is sufficiently reduced even if n-type doping is performed on the SiGe layer.
  • the contact resistance with the wiring is sufficiently reduced even if n-type doping is performed on the SiGe layer.
  • high-temperature heat treatment is performed to reduce the contact resistance, there is a problem that device characteristics are greatly deteriorated with the occurrence of defects in the SiGe layer.
  • SiGe sources and drains doped during epitaxial growth in an n-type Ge channel MISFET have difficulty in lowering resistance without improving carrier concentration, and applying tensile strain to the channel and reducing parasitic resistance. There was an incompatible problem.
  • the problem to be solved by the present invention is that, in a configuration in which tensile strain is applied to the Ge channel by the SiGe layer, the contact resistance with the wiring can be reduced without causing defects in the SiGe layer. It is an object to provide a field effect semiconductor device that can contribute to the improvement of the above and a method for manufacturing the same.
  • a field effect semiconductor device includes a Ge-containing semiconductor layer, a gate electrode provided on the semiconductor layer via a gate insulating film, and a channel region below the gate electrode.
  • a source / drain region made of Si 1-x Ge x (0 ⁇ x ⁇ 1) is provided on the semiconductor layer, and is applied to the channel region, and is formed on the source / drain region.
  • a wiring layer in contact with the Ge layer is provided on the semiconductor layer, and is applied to the channel region, and is formed on the source / drain region.
  • the method of manufacturing a semiconductor device of the present invention includes a step of forming a gate electrode on a semiconductor layer containing Ge via a gate insulating film, and a source / surface of the surface portion of the semiconductor layer located on both sides of the gate electrode. Etching the drain region to form a trench, forming a Si 1-x Ge x (0 ⁇ x ⁇ 1) layer to fill the trench, and forming a Ge on the Si 1-x Ge x layer The method includes a step of forming a layer and a step of forming a wiring layer in contact with the Ge layer.
  • the contact resistance with the wiring can be greatly reduced without subjecting SiGe to high-temperature heat treatment. Can do. For this reason, it is possible to reduce the contact resistance with the wiring while applying a tensile strain to the Ge channel, which can contribute to an increase in driving force of the transistor.
  • FIG. 1 is a diagram showing the measurement results of resistance in the source / drain structure (Ge / SiGe) of the present invention and the conventional structure (SiGe).
  • FIG. 2A is a diagram showing measurement results of P concentration and carrier concentration of the SiGe layer.
  • FIG. 2B is a diagram showing the activation rate calculated from the measurement results of the P concentration and the carrier concentration of the SiGe layer.
  • FIG. 3 is a diagram showing the measurement results of the uniaxial tensile strain applied to the channel region when the source / drain structure of the present invention is used.
  • FIG. 4 is a sectional view showing an element structure of a field effect transistor according to an embodiment of the present invention.
  • FIG. 5 is a sectional view showing a manufacturing process of the field effect transistor of FIG.
  • the Ge layer in the source and drain regions is epitaxially grown on Ge
  • the Ge layer is epitaxially grown continuously on the SiGe layer.
  • a Ge layer is inserted between the wiring layer of the transistor and the SiGe layer that is the source and drain regions.
  • FIG. 1 is a diagram showing a change in resistance with respect to the distance of the SiGe layer from the wiring layer when the SiGe layer is in direct contact with the wiring layer and when the Ge layer is formed on the SiGe layer and in contact therewith. The resistance increases with increasing distance. The point at zero distance is the contact resistance, which is 9.2 ⁇ in Ge / SiGe, which is two orders of magnitude smaller than 900 ⁇ in SiGe.
  • FIGS. 2A and 2B show the same n-type impurity without going through a high-temperature process for electrical activation. This is because the activation rate is sufficiently high in the case of Ge with respect to the introduction amount, whereas the activation rate is nearly two orders of magnitude in the case of SiGe.
  • FIG. 2A shows the P concentration and the electron concentration with respect to the Ge concentration in SiGe
  • FIG. 2B shows the activation rate with respect to the Ge concentration in SiGe. 2A and 2B, the Ge concentration 1 corresponds to Ge.
  • the P concentration is 1 ⁇ 10 20 cm ⁇ 3
  • the electron concentration is 7 ⁇ 10 19 cm ⁇ 3
  • the activation rate is 70%.
  • the P concentration is 7 ⁇ 10 19 cm ⁇ 3
  • the electron concentration is 5 ⁇ 10 18 cm ⁇ 3
  • the activation rate is about 7%. Therefore, for the same amount of introduced n-type impurities, Ge is almost 100% electrically activated without going through a high temperature process such as electrical activation, whereas SiGe is activated. , Almost no activation. That is, it is possible to reduce the contact resistance with the wiring layer by inserting the Ge layer.
  • the contact resistance with the wiring layer is defined by the carrier concentration of the semiconductor layer and the Schottky barrier height at the metal / semiconductor interface. This is thought to have led to a significant reduction in resistance.
  • A proportionality constant
  • ⁇ B Schottky barrier height at the metal / semiconductor interface
  • Ns carrier concentration of semiconductor layer
  • ⁇ s dielectric constant of semiconductor
  • m * effective mass of electrons.
  • the amount of tensile strain introduced into the channel is sufficient for improving the driving force. Further, as shown in FIG. 3, in the case of the Ge / SiGe source / drain, the strain is larger than that of the Ge source / drain, and the strain amount is increased as the gate length is further reduced. For this reason, improvement in the driving capability of the transistor is expected.
  • FIG. 4 is a sectional view showing an element structure of a field effect transistor according to an embodiment of the present invention.
  • reference numeral 10 denotes a p-type Ge substrate (a semiconductor layer containing Ge), and an element isolation insulating film 11 is formed on a part of the Ge substrate 10 so as to surround an element formation region.
  • an oxide, oxynitride, or nitride of aluminum, titanium, zirconium, or hafnium, or a mixture thereof can be used. It is also possible to use rare earth element oxides such as yttrium and lanthanum, oxynitrides, nitrides, or mixtures thereof. Further, it is possible to use a silicate or aluminate of titanium, zirconium, or hafnium, or an insulating film in which nitrogen is added to these. It is also possible to use a rare earth element silicate or aluminate such as yttrium or lanthanum, or an insulating film in which nitrogen is added thereto.
  • a metal film such as tantalum, titanium, zirconium, hafnium, and nitrides and carbides thereof can be used.
  • a noble metal film such as chromium, molybdenum, tungsten, rhenium, ruthenium, rhodium, iridium, palladium, or platinum can be used.
  • a polycrystalline silicon film, a polycrystalline silicon germanium film, or a polycrystalline germanium film which is a semiconductor gate electrode may be used.
  • one or more types can be selected from a metal gate electrode and a semiconductor gate electrode, respectively, and used as a laminated film.
  • the thickness of the gate electrode 31 can be set to an arbitrary thickness, it is preferably set in a range of approximately 5 nm to 150 nm from the viewpoint of device variations and ease of processing.
  • Gate sidewall insulating films 33 (bottom width 10 nm) made of silicon oxide (SiO 2 ) are formed on both side surfaces of the gate stacked structure portion made up of the gate insulating film 20, the gate electrode 31, and the hard mask 32. Then, source and drain regions 60 are formed on both sides thereof.
  • the source and drain regions 60 include a thin extension diffusion layer 40 (thickness 10 nm) formed under the gate sidewall insulating film 33 and a SiGe epitaxial layer 61 (thickness 25 nm) formed outside the gate sidewall insulating film 33.
  • An n-type doped SiGe epitaxial layer 62 (thickness 25 nm), an n-type doped Ge epitaxial layer 63 (thickness 10 nm), and a Ge metal compound layer 64 (thickness 10 nm).
  • the n-type doped SiGe epitaxial layer 62 functions as a source / drain region, and the SiGe epitaxial layer 61 is for imparting sufficient strain to the channel.
  • the SiGe layer has a so-called elevated source / drain structure formed above the upper surface of the Ge channel.
  • the thickness of the SiGe epitaxial layer 61 is preferably 10 nm or more and 50 nm or less when the Ge composition of the substrate 10 is 70%, for example.
  • the Ge composition in SiGe can be set arbitrarily, but when x ⁇ 0.7, the difference in lattice constant from Ge increases, and threading dislocations due to lattice mismatch occur at the SiGe / Ge interface. The possibility increases. When x> 0.9, the difference in lattice constant is not sufficient, and sufficient strain cannot be applied to the channel. Therefore, 0.7 ⁇ x ⁇ 0.9 is desirable for the Ge composition x in SiGe.
  • the thickness of the n-type doped SiGe epitaxial layer 62 can also be arbitrarily selected, in order to efficiently suppress the short channel effect, it is desirable to set it to about 1 ⁇ 2 to 3 of the gate length.
  • the contact resistance reduction effect is not sufficient when the n-type doped Ge epitaxial layer 63 is thin, and when it is thick, the tensile strain on the channel due to the SiGe layer is alleviated and lattice mismatch occurs at the SiGe / Ge interface. Since threading dislocation due to the occurrence occurs, the thickness is preferably 11 nm or more and 20 nm or less.
  • the SiGe epitaxial layers 61 and 62 By forming the SiGe epitaxial layers 61 and 62, tensile strain can be applied to the Ge channel. Further, the formation of the Ge epitaxial layer 63 can reduce the contact resistance with the metal wiring. Further, the formation of the Ge metal compound layer 64 can increase the area of the interface between the metal and the semiconductor, and can further reduce the contact resistance.
  • the Ge metal compound layer 64 is made of an alloy of at least one metal selected from Ni, Fe, Co, Pd, Pt, and Cu and the n-type doped Ge epitaxial layer 63.
  • Ni is selected as a metal, and a part of the Ge layer 63 is formed into a NiGe alloy in order to reduce parasitic resistance by increasing the area of the metal contact, and the NiGe layer is formed to a thickness of about 10 nm.
  • an element isolation insulating film 11 made of an oxide film or the like is formed on a part of the Ge substrate 10 so as to surround an element formation region.
  • a gate insulating film 20 composed of a GeOx film 21 having a thickness of 1 nm and a high dielectric film 22 having a thickness of 2.5 nm is formed on the substrate 10, and a gate electrode 31 having a thickness of 10 nm is further formed thereon. To do.
  • the gate insulating film 20 As a method for forming the gate insulating film 20, an appropriate method is selected from MOCVD (Metal Organic Chemical Vapor Deposition), ALD (Atomic Layer Deposition), MBE (Molecular Beam Epitaxy), PVD (Physical Vapor Deposition), and the like. Can be used. Furthermore, a laminated structure can be appropriately selected from these and used. The thickness of the gate insulating film 20 can be determined as appropriate within a range of 2 nm to 10 nm. As a method of forming the gate electrode 31, a sputtering method can be used.
  • the gate electrode 31 and the gate insulating film 20 are patterned into a gate pattern using this to form a gate stacked structure portion. .
  • a method for forming a hard mask 32 As a method for forming a hard mask 32, another low pressure CVD method using SiH 4 and O 2, the use of the plasma CVD method using TEOS and O 2, SiH 4 and O 2, SiH 4 and N 2 O Can do. Further, a SiN film may be used instead of SiO 2 .
  • the source / drain extension diffusion layer 40 is formed by ion implantation or the like using the gate stacked structure portion as a mask.
  • impurity ions P, As, Sb, etc.
  • gases such as PH 3 , AsH 3 , SbH 3 are used. You may anneal and form in atmosphere.
  • gate sidewall insulating films 33 are formed on both side surfaces of the gate stacked structure portion.
  • the gate sidewall insulating film 33 may be formed by depositing an insulating film such as an oxide film on the entire surface by CVD and then etching back by RIE.
  • the non-doped SiGe layer 61, the n-SiGe layer 62, and the n-Ge layer 63 are epitaxially grown in this order using the CVD method.
  • a gas such as SiH 4 or GeH 4 is used.
  • the thickness of the SiGe layer can be arbitrarily selected, but if the thickness is small, the amount of strain applied to the channel becomes small. Further, when deposited to a thickness greater than the critical thickness, threading dislocations due to lattice mismatch occur at the SiGe / Ge interface. Therefore, for example, when the Ge composition is 70%, 10 nm or more and 50 nm or less are desirable.
  • the thickness of the n-SiGe layer 62 can also be selected arbitrarily, in order to suppress the short channel effect efficiently, it is desirable to set it to about 1/2 to 1/3 of the gate length.
  • the carrier concentration of the n-Ge layer 63 is higher than that of the n-SiGe layer 62 even when the same growth conditions are used, the contact resistance is reduced even if the contact with the wiring layer is formed. Can be kept low. Further, even in the Ge / SiGe two-layer structure, the strain to the channel is efficiently applied, and an increase in driving force of the transistor due to tensile strain can be expected.
  • the composition and thickness of the SiGe layer and the thickness of the n-type doped layer were determined in view of the above circumstances.
  • the SiGe layer 61, the n-SiGe layer 62, and the n-Ge layer 63 are formed by the CVD method, they can be continuously formed while appropriately selecting a gas flow rate or the like at the time of formation. The cost is not increased due to complicated processes.
  • a Ge metal compound layer 64 is formed on the n-Ge layer 63.
  • the Ge metal compound layer 64 is selected from one or more metals of Ni, Fe, Co, Pd, Pt, and Cu, and is deposited on the n-Ge layer 63 by using a sputtering method or a CVD method, followed by heat treatment. It is formed by performing. For example, it is possible to form a NiGe layer of about 10 nm by selecting Ni as the metal and performing annealing under conditions of a deposited film thickness of 5 nm and a heat treatment of 350 ° C. for 1 minute. At that time, the Ge layer is consumed by reacting by about 10 nm. Therefore, if the thickness of the n-type doped Ge epitaxial layer is set to 11 nm or more and 20 nm or less as described above, The thickness is 1 nm or more and 10 nm or less.
  • Unreacted Ni metal can be easily and selectively dissolved in Ge by an acid having no oxidizing power such as hydrochloric acid or dilute sulfuric acid.
  • an acid having no oxidizing power such as hydrochloric acid or dilute sulfuric acid.
  • the structure shown in FIG. 4 is obtained by forming the interlayer insulating film 71, forming the contact holes, and forming the contact vias 72 serving as wirings.
  • tensile strain can be applied to the Ge channel by embedding the SiGe layers 61 and 62 in the source / drain regions.
  • the contact resistance can be reduced by providing the n-Ge layer 63 on the n-SiGe layer 62.
  • the contact resistance can be further reduced by forming the Ge metal compound layer 64 on the n-Ge layer 63.
  • the contact resistance with the wiring can be reduced without causing defects in the n-SiGe layer 62, and the device characteristics are improved. It becomes possible to contribute to. This is effective in realizing a CMOS-LSI with high performance and low power consumption.
  • the semiconductor constituting the channel is not necessarily limited to the Ge substrate, but may be a substrate containing Ge as a main component.
  • the channel may be a SiGe substrate, and the source / drain regions may be SiGe layers having a lower Ge concentration than the channel.
  • the Ge composition x of Si 1-x Ge x constituting the source / drain region may be any as long as it is smaller than the Ge composition in the semiconductor layer and can apply strain to the semiconductor layer. A range of 7 ⁇ x ⁇ 0.9 is desirable.
  • the thickness of the Ge layer is preferably in the range of 1 nm or more and 10 nm or less from the viewpoint of obtaining a sufficient contact resistance reduction effect and further suppressing relaxation of tensile strain and occurrence of threading dislocations.
  • the SiGe layer constituting the source / drain region is not necessarily formed in two layers. If sufficient strain can be applied only by the upper n-type doped SiGe layer, the lower SiGe layer may be omitted. Is possible.
PCT/JP2014/051222 2013-05-14 2014-01-22 電界効果型半導体装置及びその製造方法 WO2014185086A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013102017A JP2014222723A (ja) 2013-05-14 2013-05-14 電界効果型半導体装置及びその製造方法
JP2013-102017 2013-05-14

Publications (1)

Publication Number Publication Date
WO2014185086A1 true WO2014185086A1 (ja) 2014-11-20

Family

ID=51898074

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/051222 WO2014185086A1 (ja) 2013-05-14 2014-01-22 電界効果型半導体装置及びその製造方法

Country Status (3)

Country Link
JP (1) JP2014222723A (zh)
TW (1) TW201444024A (zh)
WO (1) WO2014185086A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10580882B2 (en) 2015-12-21 2020-03-03 Intel Corporation Low band gap semiconductor devices having reduced gate induced drain leakage (GIDL)
CN116705837A (zh) * 2018-10-26 2023-09-05 中国科学院微电子研究所 半导体器件与其制作方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214481A (ja) * 2006-02-13 2007-08-23 Toshiba Corp 半導体装置
JP2012501093A (ja) * 2008-08-25 2012-01-12 東京エレクトロン株式会社 アルミニウムがドープされた金属炭窒化物ゲート電極の作製方法
WO2012087404A1 (en) * 2010-12-21 2012-06-28 Intel Corporation Selective germanium p-contact metalization through trench

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214481A (ja) * 2006-02-13 2007-08-23 Toshiba Corp 半導体装置
JP2012501093A (ja) * 2008-08-25 2012-01-12 東京エレクトロン株式会社 アルミニウムがドープされた金属炭窒化物ゲート電極の作製方法
WO2012087404A1 (en) * 2010-12-21 2012-06-28 Intel Corporation Selective germanium p-contact metalization through trench

Also Published As

Publication number Publication date
JP2014222723A (ja) 2014-11-27
TW201444024A (zh) 2014-11-16

Similar Documents

Publication Publication Date Title
JP5173582B2 (ja) 半導体装置
US9401417B2 (en) Method of manufacturing a semiconductor device
US7943469B2 (en) Multi-component strain-inducing semiconductor regions
JP5756996B2 (ja) マルチゲートトランジスタおよび形成する方法
JP5306320B2 (ja) 歪みが強化された半導体デバイスとその製造方法
US8487348B2 (en) Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
US10170469B2 (en) Vertical field-effect-transistors having multiple threshold voltages
JP5745076B2 (ja) ＳｉＧｅチャネルを有するｐＦＥＴ接合プロフィールのための方法および構造体
US8035141B2 (en) Bi-layer nFET embedded stressor element and integration to enhance drive current
JP2009032955A (ja) 半導体装置、およびその製造方法
US20110169105A1 (en) Semiconductor device and method for manufacturing the same
TWI387010B (zh) 用於製造電晶體之方法
TW201230209A (en) Semiconductor device and method for manufacturing the same
JP2014060286A (ja) 半導体装置およびその製造方法
CN111987159A (zh) 半导体结构和形成半导体结构的方法
CN106663634A (zh) 半导体器件及半导体器件的制造方法
US9966466B2 (en) Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof
US8247279B2 (en) Method of fabricating semiconductor device using epitaxial growth inhibiting layers
JP2009182264A (ja) 半導体装置およびその製造方法
JP5526493B2 (ja) トレンチゲート型半導体装置およびその製造方法
WO2014185086A1 (ja) 電界効果型半導体装置及びその製造方法
JP2018206872A (ja) 半導体装置
US20070066023A1 (en) Method to form a device on a soi substrate
US20230122250A1 (en) Field effect transistor with multiple hybrid fin structure and method
US20220352311A1 (en) Semiconductor Devices with Counter-Doped Nanostructures

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14797205

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14797205

Country of ref document: EP

Kind code of ref document: A1