TW201444024A - 場效型半導體裝置及其製造方法 - Google Patents

場效型半導體裝置及其製造方法 Download PDF

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TW201444024A
TW201444024A TW103102685A TW103102685A TW201444024A TW 201444024 A TW201444024 A TW 201444024A TW 103102685 A TW103102685 A TW 103102685A TW 103102685 A TW103102685 A TW 103102685A TW 201444024 A TW201444024 A TW 201444024A
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Yuuichi Kamimuta
Yoshihiko Moriyama
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Nat Inst Of Advanced Ind Scien
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Abstract

本發明係有關於一種具有Ge通道與SiGe之源極‧汲極區域的場效型半導體裝置。場效型半導體裝置具備有半導體層、閘極絕緣膜、閘極電極、源極‧汲極區域、Ge層、及配線層。半導體層含有Ge。閘極電極係隔著閘極絕緣膜設置於半導體層上。源極‧汲極區域係設置於半導體層且挾著閘極電極下之通道區域，且由對通道區域施加拉伸應變之Si1-xGex(0＜x＜1)所構成。Ge層係形成於源極‧汲極區域上。配線層係與Ge層接觸。

Description

場效型半導體裝置及其製造方法 發明領域
本發明之實施形態係有關於一種具有Ge通道與SiGe源極‧汲極區域之場效型半導體裝置及其製造方法。
發明背景
近年來，為求場效電晶體(MISFET)之性能提昇，正研討使用與以往所使用之Si相比之下在電子及電洞之遷移率皆比高的Ge通道之嘗試。以該方法來說，藉由高遷移率使MISFET之電流驅動力提昇，可期待高速動作或低消費電力化。
對於此種使用Ge通道之MISFET，已有提出為了更提昇特性而對Ge通道施加應變之結構。與Si的狀況相同，已知藉由對Ge通道施加拉伸應變，電子遷移率會增大(參照非專利文獻1)。特別是，n型MISFET中，與將晶格常數比Si小的SiC形成於源極及汲極區域之方法相同地，藉由將晶格常數比Ge小的SiGe埋入源極及汲極區域，對通道施加單軸拉伸應變而可使電子遷移率增大，驅動力提昇。
作為埋入源極及汲極區域之SiGe的形成方法係使用磊晶法。然而，為了對SiGe層作n型雜質摻雜而使用離 子注入法，則離子注入導致之對結晶的損害顯著，而結晶性之回復則需要高溫處理。若不回復結晶性而直接製造元件，會因為結晶之缺陷而產生載子，成為洩漏電流之原因。又，若因結晶性之回復而導入高溫處理，則會從表面發生高蒸氣壓之氧化鍺(II)之脫離，元件特性會產生劣化。
為了避免離子注入所導致的結晶之損傷，在將埋入源極及汲極區域之SiGe層對Ge進行磊晶成長時，有想到導入PH3氣體等進行n型摻雜之方法。此時，於SiGe層會導入充足的P，但為了降低與配線之接觸電阻(源極及汲極區域與接觸孔之接觸電阻)而要電性激活，則需要高溫處理。此時，SiGe/Ge之磊晶層之界面會發生缺陷，與上述同樣地，會產生載子而成為洩漏電流之原因。又，同樣地會從表面發生高蒸氣壓之氧化鍺(II)之脫離，元件特性會產生劣化。
先行技術文獻 非專利文獻
非專利文獻1：Y.-J. Yang, et al., Appl. Phys. Lett. 91, 102103 (2007).
發明概要
如此，為了對Ge通道施加拉伸應變而在源極‧汲極區域填埋SiGe層之構成中，即使對SiGe層進行n型摻雜，仍舊難以充分降低與配線之接觸電阻。又，若為了降 低接觸電阻而施以高溫熱處理，則隨著SiGe層之缺陷產生而會有元件特性大幅地劣化之問題。亦即，對於n型Ge通道之MISFET來說，磊晶成長中進行了摻雜之SiGe源極‧汲極中，難以作到不提昇載子濃度而能低電阻化，會有對通道施加拉伸應變與降低寄生電阻不能兩立之問題。
本發明欲解決之課題係提供一種在對Ge通道以SiGe層附加了拉伸應變之構成中，能不導致SiGe層之缺陷產生，且降低與配線之接觸電阻，對提昇元件特性能有助益之場效型半導體裝置及其製造方法。
為解決上述課題，本發明之場效型半導體裝置之特徵在於具備有：含Ge之半導體層；閘極電極，係隔著閘極絕緣膜設置於前述半導體層上；源極‧汲極區域，係設置於前述半導體層且挾著前述閘極電極下之通道區域，且由對前述通道區域施加拉伸應變之Si1-xGex(0<x<1)所構成；形成於前述源極‧汲極區域上之Ge層；與前述Ge層接觸之配線層。
又，本發明之半導體之製造方法的特徵在於包含：於含Ge之半導體層上隔著閘極絕緣膜形成閘極電極之步驟；將位於前述閘極電極兩側之前述半導體層表面部之源極‧汲極區域蝕刻而形成溝部之步驟；以填埋前述溝部之方式形成Si1-xGex(0<x<1)層之步驟；於前述Si1-xGex層上形成Ge層之步驟；及形成與前述Ge層接觸之配線層之步驟。
依據本發明，藉由以SiGe所構成之源極‧汲極區域與配線層之間插入Ge層，可不用對SiGe施加高溫熱處理而能大幅降低與配線之接觸電阻。因此可對Ge通道施加拉伸應變，並降低與配線之接觸電阻，能對提昇電晶體之驅動力增大有助益。
10‧‧‧p型Ge基板(半導體層)
11‧‧‧元件分離絕緣膜
20‧‧‧閘極絕緣膜
21‧‧‧GeOx層
22‧‧‧高介電絕緣膜
31‧‧‧閘極電極
32‧‧‧SiO2硬遮蔽罩
33‧‧‧閘極側壁絕緣膜
40‧‧‧延伸擴散層
50‧‧‧凹入結構
60‧‧‧源極‧汲極區域
61‧‧‧SiGe磊晶層
62‧‧‧n型摻雜SiGe磊晶層
63‧‧‧n型摻雜Ge磊晶層
64‧‧‧Ge金屬化合物層
71‧‧‧層間絕緣膜
72‧‧‧接觸孔(配線)
圖1係顯示本發明之源極‧汲極結構(Ge/SiGe)與習知結構(SiGe)的電阻測定結果之圖。
圖2A係顯示SiGe層之P濃度及載子濃度之測定結果之圖。
圖2B係顯示由SiGe層之P濃度及載子濃度之前述測定結果來計算之活性化率之圖。
圖3係顯示使用本發明之源極‧汲極結構時，施加於通道區域之單軸拉伸應變量的測定結果之圖。
圖4係顯示本發明之一種實施形態之場效電晶體的元件結構之剖面圖。
圖5係顯示圖4之場效電晶體的製造步驟之剖面圖。
用以實施發明之形態
在說明發明之實施形態前，先對本發明之基本原理作說明。
將埋入源極及汲極區域之SiGe層對Ge進行磊晶成長時，係於SiGe層上連續地使Ge層進行磊晶成長。藉此，會構成電晶體之配線層與源極及汲極區域之SiGe層之間插 入有Ge層之結構。
藉由源極及汲極區域之n型摻雜SiGe層與配線層之間插入Ge層，會如圖1所示，能大幅降低與配線層之接觸電阻(源極及汲極區域與接觸孔之接觸電阻)。圖1係顯示令SiGe層與配線層直接接觸之狀況、以及SiGe層上形成有Ge層來接觸之狀況，兩狀況下的SiGe層相對於與配線層之距離的電阻變化之圖，隨著距離變長而電阻變大。距離零之點為接觸電阻，相對於SiGe之900Ω，Ge/SiGe為小了兩位數之9.2Ω。
藉由插入Ge層可降低與配線層之接觸電阻，其理由係如圖2A、圖2B所示，不必經過令其電性激活這種高溫處理，對於同樣的n型雜質之導入量，以Ge來說，活性化率屬於足夠高，相對於SiGe來說，活性化率為低的少了將近兩位數。圖2A顯示相對於SiGe中Ge濃度之P濃度與電子濃度，圖2B顯示相對於SiGe中Ge濃度之活性化率。圖2A、圖2B中，Ge濃度1相當於Ge。
以Ge來說，相對於P濃度為1×1020cm-3之電子濃度為7×1019cm-3，活性化率為70%。相對於此，以Ge濃度0.8之SiGe來說，相對於P濃度為7×1019cm-3之電子濃度為5×1018cm-3，活性化率約為7%。故不必經過電性激活這種高溫處理，對於同樣的n型雜質之導入量，以Ge來說，幾乎100%電活性化，相對於此，以SiGe來說，幾乎沒有活性化。亦即，藉由插入Ge層可謀求降低與配線層之接觸電阻係屬可能。
與配線層之接觸電阻係如式(1)所示，係以半導體層之載子濃度與金屬/半導體界面之蕭特基位障高度來規定，故可想見插入活性化率高之Ge層係與接觸電阻之大幅降低有關連。
在此，A：比例常數、ΦB：金屬/半導體界面之蕭特基位障高度、Ns：半導體層之載子濃度、εS：半導體之介電常數、m*：電子之有效質量。
又，導入至通道之拉伸應變量亦為足夠提昇驅動力之量。此外，如圖3所示，以Ge/SiGe之源極．汲極來說，應變比起Ge之源極．汲極還大，還有隨著閘極長變細而應變量亦變大。因此，可期待電晶體之驅動力提昇。
由以上之觀點來看，相較於以往不施加應變之電晶體或源極．汲極區域形成有SiGe層之施加應變電晶體，能期待大幅的電流驅動力提昇、高速動作或低消費電力化。
以下將參照圖示來說明實施形態之場效型半導體裝置。
(實施形態)
圖4係顯示本發明之一種實施形態之場效電晶體的元件結構之剖面圖。
圖中的10為p型Ge基板(含Ge之半導體層)，在該Ge基板10之一部份以圍住元件形成區域之方式形成有元件分離絕緣膜11。元件形成區域上之一部分形成有由GeOx層 21(厚度1nm)及高介電絕緣膜22(厚度2.5nm)所構成之閘極絕緣膜20。此外，閘極絕緣膜20上形成有閘極電極31(厚度10nm)與SiO2硬遮蔽罩(厚度5nm)32。
作為閘極絕緣膜20之高介電絕緣膜22，可使用鋁、鈦、鋯、鉿任一者之氧化物、氮氧化物、或氮化物、或者該等之混合物。又，亦可使用釔、鑭等稀土族元素之氧化物、氮氧化物、或氮化物、或者該等之混合物。此外，亦可使用鈦、鋯、鉿之矽酸鹽或鋁酸鹽、或者添加氮至該等之絕緣膜。又，亦可使用釔、鑭等稀土族元素之矽酸鹽或鋁酸鹽、或者添加氮至該等之絕緣膜。
作為閘極電極31，可使用鉭、鈦、鋯、鉿等金屬膜及該等之氮化物、碳化物。此外，亦可使用鉻、鉬、鎢、錸、釕、銠、銥、鈀、白金等貴金屬膜。又，亦可使用半導體閘極電極之多結晶矽膜、多結晶矽鍺膜、多結晶鍺膜。又，亦可從金屬閘極電極與半導體閘極電極各選擇1種類以上作為積層膜使用。閘極電極31之厚度可設定為任選之厚度，然而從元件不一致與加工容易度之觀點來看，係以設定於大約5nm~150nm之範圍為佳。
由閘極絕緣膜20、閘極電極31、硬遮蔽罩32構成之閘極積層結構部，在其兩側面形成有由氧化矽(SiO2)構成之閘極側壁絕緣膜33(底部之寬10nm)。其次，其兩側形成有源極及汲極區域60。源極及汲極區域60係由形成於閘極側壁絕緣膜33下部之薄的延伸擴散層40(厚度10nm)、形成於閘極側壁絕緣膜33外側之SiGe磊晶層61(厚度25nm)、n型 摻雜SiGe磊晶層62(厚度25nm)、n型摻雜Ge磊晶層63(厚度10nm)、Ge金屬化合物層64(厚度10nm)所構成。
在此，發揮作為源極．汲極區域之機能者為n型摻雜SiGe磊晶層62，而SiGe磊晶層61係用以對通道施加充分應變者。為了有效地施加對通道之應變，SiGe層係形成於比Ge通道上面之更上側，亦即成為所謂抬升式源極．汲極結構。
關於SiGe磊晶層61之厚度，例如以基板10之Ge組成70%來說，以10nm以上、50nm以下為理想。又，關於SiGe中的Ge組成可以設定為任選，然而x<0.7時，與Ge之晶格常數的差會變大，發生起因於SiGe/Ge界面晶格不匹配之貫穿式差排的可能性會提高。又，x>0.9時，晶格常數的差會不足且無法對通道施加足夠應變。因此，關於SiGe中的Ge組成x，係以0.7≦x≦0.9為理想。n型摻雜SiGe磊晶層62之厚度亦可以任意選擇，然而為了有效地抑制短通道效果，係以閘極長度之1/2至1/3左右為理想。
關於n型摻雜Ge磊晶層63之厚度，若薄則降低接觸電阻之效果不充分，而若厚則藉由SiGe層對通道之拉伸應變變得緩和、且發生起因於SiGe/Ge界面晶格不匹配之貫穿式差排，故以11nm以上、20nm以下為理想。
藉由上述SiGe磊晶層61、62之形成，可對Ge通道施加拉伸應變。又，藉由Ge磊晶層63之形成，可降低與金屬配線之接觸電阻。此外，藉由Ge金屬化合物層64之形成，能擴大金屬與半導體之界面的面積，可望進一步降低 接觸電阻。
Ge金屬化合物層64係由選自於Ni、Fe、Co、Pd、Pt、Cu中至少1種金屬與n型摻雜Ge磊晶層63之合金構成。例如，選擇Ni作為金屬，為了金屬接觸之面積增大造成寄生電阻之減低，將Ge層63之一部份與NiGe合金化，將NiGe層形成為約10nm之厚度。
其次，參照圖5並說明本實施形態之半導體裝置之製造方法。
首先，如圖5(a)所示，於Ge基板10之一部份以圍住元件形成區域之方式形成由氧化膜等構成之元件分離絕緣膜11。接著，於基板10上形成由厚度1nm之GeOx膜21及厚度2.5nm之高介電膜22所構成之閘極絕緣膜20，更於其上形成有厚度10nm之閘極電極31。
作為閘極絕緣膜20之成膜方法，可從MOCVD(Metal Organic Chemical Vapor Deposition)法、ALD(Atomic Layer Deposition)法、MBE(分子束磊晶法)法、PVD(Physical Vapor Deposition)法等作適宜選擇來使用。此外，可從該等中適宜選擇積層結構來使用。閘極絕緣膜20之膜厚可在2nm~10nm範圍內作適宜決定。作為閘極電極31之形成方法可使用濺鍍法。
接著，在閘極電極31形成厚度5nm之SiO2硬遮蔽罩32之後，利用其將閘極電極31及閘極絕緣膜20來圖案成形成為閘極圖案，形成閘極積層結構部。
作為形成硬遮蔽罩32之方法，除了使用SiH4與O2 之減壓CVD法，還可使用TEOS與O2、SiH4與O2、SiH4與N2O之電漿CVD法。又，可使用SiN膜代替SiO2。作為此情形之形成方法，除了可使用SiH2Cl2與NH3之減壓CVD法，還可使用SiH4與NH3、SiH2Cl2與NH3之電漿CVD法。
接著，藉由將閘極積層結構部進行對遮蔽罩之離子注入等，形成源極．汲極之延伸擴散層40。作為薄的延伸擴散層40之形成方法，除了將雜質離子(P、As、Sb等)在低加速能量下注入，進行活性化退火之方法以外，還可在PH3、AsH3、SbH3等氣體環境中進行退火來形成。
接著，在閘極積層結構部之兩側面形成閘極側壁絕緣膜33。閘極側壁絕緣膜33之形成只需在整面以CVD堆積氧化膜等絕緣膜之後，以RIE進行回蝕刻即可。
其次，如圖5(b)所示，藉由僅對Ge基板10表面之源極及汲極預定區域以RIE進行選擇性蝕刻之後，進行各向異性之濕法蝕刻，來形成凹入結構50。
其次，如圖5(c)所示，以CVD法使無摻雜之SiGe層61、n-SiGe層62、及n-Ge層63依序進行磊晶成長。以CVD法形成時會使用SiH4、GeH4等氣體。SiGe層之厚度亦可以任意選擇，然而厚度若薄則對通道施加之應變量變小。又，若堆積至臨界膜厚以上則會發生起因於SiGe/Ge界面晶格不匹配之貫穿式差排。因此，以Ge組成70%來說，以10nm以上、50nm以下為理想。n-SiGe層62之厚度亦可以任意選擇，然而為了有效地抑制短通道效果，係以閘極長度之1/2至1/3左右為理想。
在此，n-Ge層63之載子濃度與n-SiGe層62比較，即使在同樣的成長條件下，活性化之載子濃度仍較高，即使與配線層形成接觸，可維持低的接觸電阻。此外，即使是Ge/SiGe之2層結構，仍有效地施加對通道之應變，可期待拉伸應變造成的電晶體之驅動力增大。
本實施形態係鑑於上述情事來決定SiGe層之組成、厚度、n型摻雜之層的厚度。此外，SiGe層61、n-SiGe層62、n-Ge層63之形成若以CVD法來進行時，可適宜選擇形成時之氣體流量等並連續地形成，故不會發生步驟繁雜化導致之成本增大。
其次，如圖5(d)所示，於n-Ge層63之上形成Ge金屬化合物層64。Ge金屬化合物層64係從Ni、Fe、Co、Pd、Pt、Cu中選擇1種以上之金屬，於n-Ge層63上以濺鍍法或CVD法進行堆積，並進行熱處理來形成。例如，選擇Ni作為金屬、堆積膜厚5nm、熱處理350℃、1分鐘之條件下進行退火，則可形成約10nm之NiGe層。此時，Ge層會有約10nm反應並被消費，故如前述般將n型摻雜Ge磊晶層之厚度事先設定成11nm以上、20nm以下，則未反應而殘存之Ge層之厚度會變成1nm以上、10nm以下。
關於未反應之Ni金屬，可藉由鹽酸或稀硫酸等無氧化力之酸來容易地對Ge選擇性地溶解。形成Ge金屬化合物層64時，必須在n-Ge層63不會完全反應掉之條件下來形成。因為若在所堆積之金屬的膜厚為厚，或是退火之溫度為高的條件下進行，n-Ge層63會全部與Ge金屬化合物層反 應，接觸界面會變成SiGe層。接觸界面若變成SiGe層，則如前述，SiGe層之活性化率為低，故會招致接觸電阻之顯著增大。
其後，藉由進行層間絕緣膜71之形成、接觸孔之形成、作為配線之接觸孔72之形成，獲得前述圖4所示之結構。
依據本實施形態，藉由於源極‧汲極區域填埋SiGe層61、62，可對Ge通道施加拉伸應變。而且藉由在n-SiGe層62上設置n-Ge層63，可降低接觸電阻。再加上，藉由在n-Ge層63上設置Ge金屬化合物層64，可進一步降低接觸電阻。
亦即，對Ge通道以SiGe層61、62施加拉伸應變之構成中，不會招致n-SiGe層62之缺陷產生，且可降低與配線之接觸電阻，對提昇元件特性能有助益。而這對於高性能．低消費電力之CMOS-LSI之實現係有效的。
(變形例)
又，本發明並非受限於上述各實施形態者。
構成通道之半導體並不一定限於Ge基板，只需為含有Ge作為主成份之基板即可。例如，通道為SiGe基板而源極．汲極區域係Ge濃度比通道低之SiGe層亦可。此外，不需要是塊狀基板，亦可為在基板上形成有含有Ge之半導體層。
構成源極‧汲極區域之Si1-xGex之Ge組成x，其係比半導體層之Ge組成更小而能對半導體層施加應變者即 可，半導體層為Ge單體時，係以0.7≦x≦0.9為理想。從獲得充分降低接觸電阻之效果、更加上拉伸應變之緩和還有抑制貫穿式差排之發生的觀點來看，Ge層之膜厚係以1nm以上、10nm以下之範圍為理想。
構成源極‧汲極區域之SiGe層不必非得形成為2層不可，僅有上層側之n型摻雜SiGe層就能施加足夠應變時，下層側之SiGe層亦可省略。
對於本發明之數個實施形態已作說明，該等實施形態係作為舉例而提示者，並無意用作限定發明之範圍。該等實施形態可用其他各種形態來實施，在不脫離發明要旨之範圍內，可作各種省略、置換、變更。該等實施形態或其變形係專利申請之範圍所記載之發明及其均等之範圍所包含者，一如被包含於發明之範圍及要旨。
10‧‧‧p型Ge基板(半導體層)
11‧‧‧元件分離絕緣膜
20‧‧‧閘極絕緣膜
21‧‧‧GeOx層
22‧‧‧高介電絕緣膜
31‧‧‧閘極電極
32‧‧‧SiO2硬遮蔽罩
33‧‧‧閘極側壁絕緣膜
40‧‧‧延伸擴散層
60‧‧‧源極‧汲極區域
61‧‧‧SiGe磊晶層
62‧‧‧n型摻雜SiGe磊晶層
63‧‧‧n型摻雜Ge磊晶層
64‧‧‧Ge金屬化合物層
71‧‧‧層間絕緣膜
72‧‧‧接觸孔(配線)

Claims (10)

  1. 一種場效型半導體裝置，其特徵在於具備有：含Ge之半導體層；閘極電極，係隔著閘極絕緣膜設置於前述半導體層上；源極‧汲極區域，係設置於前述半導體層且挾著形成於前述閘極電極下之前述半導體層的通道區域，且由對前述通道區域施加拉伸應變之Si1-xGex(0<x<1)層所構成；形成於前述源極‧汲極區域上之Ge層；及與前述Ge層接觸之配線層。
  2. 如請求項1之場效型半導體裝置，其中前述Ge層與前述Si1-xGex層之界面位於比前述通道區域之上面更上側。
  3. 如請求項1或2之場效型半導體裝置，其中前述Si1-xGex層之Ge組成x為0.7≦x≦0.9。
  4. 如請求項1至3項中任1項之場效型半導體裝置，其中前述Ge層之膜厚為1nm以上且10nm以下。
  5. 如請求項1至4項中任1項之場效型半導體裝置，其中前述Ge層之表面上形成有Ge金屬化合物區域。
  6. 如請求項5之場效型半導體裝置，其中前述Ge金屬化合物區域之金屬係選自於Ni、Fe、Co、Pd、Pt、Cu中之至少1個。
  7. 如請求項1至6項中任1項之場效型半導體裝置，其中前 述半導體層為p型，前述Si1-xGex層及前述Ge層為n型。
  8. 如請求項7之場效型半導體裝置，其中前述源極‧汲極區域係無摻雜第1Si1-xGex層與n型摻雜第2Si1-xGex層之積層結構。
  9. 一種場效型半導體裝置之製造方法，其特徵在於包含：於含Ge之半導體層上隔著閘極絕緣膜形成閘極電極之步驟；將位於前述閘極電極兩側之前述半導體層表面部的源極‧汲極區域蝕刻而形成溝部之步驟；以填埋前述溝部之方式形成Si1-xGex(0<x<1)層之步驟；於前述Si1-xGex層上形成Ge層之步驟；及形成與前述Ge層接觸之配線層之步驟。
  10. 如請求項9之場效型半導體裝置之製造方法，其中形成前述Si1-xGex層及前述Ge層之步驟係以CVD法連續進行。
TW103102685A 2013-05-14 2014-01-24 場效型半導體裝置及其製造方法 TW201444024A (zh)

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