WO2014173138A1 - 阵列基板及其制作方法以及显示装置 - Google Patents

阵列基板及其制作方法以及显示装置 Download PDF

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Publication number
WO2014173138A1
WO2014173138A1 PCT/CN2013/089141 CN2013089141W WO2014173138A1 WO 2014173138 A1 WO2014173138 A1 WO 2014173138A1 CN 2013089141 W CN2013089141 W CN 2013089141W WO 2014173138 A1 WO2014173138 A1 WO 2014173138A1
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Prior art keywords
conductive structure
array substrate
tft
passivation layer
data line
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PCT/CN2013/089141
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English (en)
French (fr)
Inventor
郤玉生
封宾
刘家荣
林鸿涛
王章涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/379,231 priority Critical patent/US9741744B2/en
Publication of WO2014173138A1 publication Critical patent/WO2014173138A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • Embodiments of the present invention relate to an array substrate and a method of fabricating the same, and to a display device having such an array substrate. Background technique
  • a spacer is usually disposed between the two substrates, and generally, in order to avoid the dislocation of the spacer, for example, a spacer on the side of the color filter substrate is usually used in the liquid crystal panel.
  • a thin film transistor (TFT) on the array substrate side abuts.
  • the mutual friction between the spacer 4 and the passivation layer 3 in the array substrate generates an electrostatic charge (usually a positive charge), thereby forming an electric field.
  • a charge (usually an electron) is accumulated in the channel of the TFT to turn on the source 2 and the drain 1.
  • the gate of the TFT is at a low voltage and the TFT is turned off, the source 2 and the drain 1 are disconnected. If the accumulated charge in the channel of the TFT is sufficient to make the source 2 and the drain 1 conduct, then the drain 1 will The pixel electrode 5 is supplied with power, so that the panel forms an unstable pressing bright spot when displaying a black screen, resulting in poor display of the panel.
  • Fig. 2 shows an equivalent schematic diagram of the formation of a pressed bright spot, wherein the broken line indicates the path between the source S and the drain D which is formed due to the friction between the spacer and the passivation layer.
  • the source S and the drain D should be disconnected, and in the figure, the source S and the drain D due to the action of the accumulated charges. Turn on, charge capacitor C st . Summary of the invention
  • An object of an embodiment of the present invention is to provide an array substrate capable of avoiding a pressing bright spot due to friction between a spacer and a TFT, a method of fabricating the array substrate, and a display device having the array substrate.
  • an embodiment of the present invention provides an array substrate including: a TFT, a data line, a gate line, and a TFT, a data line, and a gate line on the base substrate.
  • a passivation layer the TFT includes a gate, a source, and a drain, the data line is connected to a source of the TFT, and the gate line is connected to a gate of the TFT;
  • the array substrate further includes a first conductive structure and a second conductive structure connected to the first conductive structure;
  • the first conductive structure is on the passivation layer and over the TFT; the second conductive structure is on the passivation layer and above the data line and/or the gate line.
  • the array substrate further includes a pixel electrode disposed to be isolated from the first conductive structure and the second conductive structure and connected to the drain of the TFT.
  • the first conductive structure and the second conductive structure are made of the same conductive material as the material of the pixel electrode.
  • the first conductive structure, the second conductive structure, and the pixel electrode are both ITO.
  • Embodiments of the present invention also provide a display device including the above array substrate, which is capable of achieving the above object of the embodiment of the present invention.
  • the display device further includes an opposite substrate disposed opposite to the array substrate and a spacer between the array substrate and the opposite substrate;
  • At least a portion of the spacer is in contact with the first electrically conductive structure.
  • an embodiment of the present invention provides a method of fabricating the above-described array substrate, including: forming a pattern of a TFT, a data line, a gate line, and a passivation layer on a substrate, the method further includes:
  • Step S forming a pattern of the first conductive structure on the passivation layer and over the TFT, and forming a pattern of the second conductive structure on the passivation layer and over the data line and/or the gate line, wherein the first conductive structure Connected to the second conductive structure.
  • step S includes:
  • Step S1 depositing a layer of conductive material on the passivation layer
  • Step S2 forming a pattern of the first conductive structure with the conductive material above the TFT by a patterning process, and forming a pattern of the second conductive structure with the conductive material above the data line and/or the gate line.
  • a pattern of pixel electrodes is further formed on the conductive material while performing step S2, wherein the pixel electrodes are disposed to be isolated from the first conductive structure and the second conductive structure.
  • the conductive material deposited in step S1 is ITO.
  • the array substrate provided by the embodiment of the invention and the manufacturing method thereof and the display device having the array substrate can be separated by providing a first conductive structure and a second conductive structure electrically connected to the first conductive structure in the conventional array
  • the charge generated by the friction between the pad and the array substrate is released outward from the release loop formed by the first conductive structure and the second conductive structure.
  • FIG. 1 is a schematic structural view of a conventional array substrate in contact with a spacer
  • Figure 2 is an equivalent schematic diagram generated by pressing a bright spot
  • FIG. 3 is a partial side view showing the structure of the array substrate of the present invention.
  • FIG. 4 is a schematic structural diagram of a charge network release network formed by the array substrate of the present invention. detailed description
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the present embodiment provides an array substrate including a TFT 10, a data line 18, a gate line 19, and a blunt cover on the TFT 10, the data line 18, and the gate line 19.
  • the layer 13 the TFT 10 includes a gate 14, a source 12 and a drain 11, the data line 18 is connected to the source 12 of the TFT 10, and the gate line 19 is connected to the gate 14 of the TFT 10.
  • the array substrate further includes a first a conductive structure 16 and a second conductive structure 17 electrically connected to the first conductive structure; the first conductive structure 16 is located on the passivation layer 13 and above the TFT 10; Structure 17 is located on passivation layer 13 and above data line 18 and/or said gate line 19.
  • the TFTs in the array substrate are arranged in a matrix of TFTs. At least a portion of the first conductive structures 16 are located on the passivation layer 13 and above the TFTs.
  • the data lines 18 and the gate lines 19 are plurality of strips and are distributed in a network.
  • the second conductive structure At least a portion of 17 is located on passivation layer 13 and above data line 18 and/or gate line 19.
  • a pixel electrode 15 which is disposed to be isolated from the first conductive structure 16 and the second conductive structure 17.
  • the TFT includes a gate 14, a source 12 and a drain 11; the gate 14 is electrically connected to the gate line 19, the source 12 is electrically connected to the data line 18, and the drain 11 is electrically connected to the pixel electrode 15 on the array substrate; Whether the line 19 supplies power to the gate 14 to turn the TFT on or off, and charges the pixel electrode 15 from the TFT source 12 to the drain 11 through the data line 18, thereby controlling the display of the display panel.
  • the array substrate further includes a first conductive structure 16 and a second conductive structure 17; the first conductive structure 16 can release the electric charge generated by the friction between the array substrate and the spacer through the second conductive structure 17 in time.
  • the second conductive structure may be disposed above the gate line or above the data line, and may also be disposed above the gate line and the data line. This arrangement satisfies both the purpose of releasing the charge generated by the friction between the spacer and the array substrate, and avoids interference with the structure of the pixel electrode or the like.
  • the array substrate described in this embodiment is widely used, for example, in a liquid crystal panel of various display modes such as a parallel electric field (IPS, FFS) mode, a VA mode, or the like, and can also be applied to an OLED display panel of a box structure.
  • IPS parallel electric field
  • FFS field
  • VA voltage regulation
  • OLED organic light-emitting diode
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the array substrate of the embodiment includes a TFT, a data line, a gate line, and a passivation layer overlying the TFT, the data line, and the gate line.
  • the array substrate further includes a first conductive structure 16 and a second conductive structure. 17.
  • the second conductive structure 17 is connected to the first conductive structure 16;
  • the first conductive structure 16 is on the passivation layer 13 and over the TFT; the second conductive structure 17 is on the passivation layer 13 and above the data lines and/or the gate lines.
  • the array substrate further includes a pixel electrode 15 disposed to be isolated from the first conductive structure 16 and the second conductive structure 17;
  • the first conductive structure 16 and the second conductive structure 17 are made of the same conductive material as that of the pixel electrode 15.
  • the first conductive structure 16 and the second conductive structure 17 are disposed apart from the pixel electrode 15, that is, there is no electrical connection between the first conductive structure 16, the second conductive structure 17, and the pixel electrode 15, whether directly or
  • the indirect electrical connection is such that the charge released by the first conductive structure 16 and the second conductive structure 17 does not enter the pixel electrode 15 to avoid interfering with the display of the pixel.
  • first conductive structure 16 and the second conductive structure 17 may each be a conductive structure formed of any conductive material, and in the embodiment, the same conductive material is used to form the first conductive structure 16, the second conductive structure 17 and The pixel electrode 15 facilitates the formation of these structures.
  • the pixel electrode 15, the first conductive structure 16, and the second conductive structure 17 may be formed on the passivation layer using the same patterning process.
  • the pixel electrode 15 is made of ITO (Indium Tin Oxide, which is a transparent conductive film).
  • ITO Indium Tin Oxide, which is a transparent conductive film.
  • the first conductive structure and the second conductive structure are arranged to have the same material as the pixel electrode, and the waste ITO is used, which increases the cost and increases the manufacturing process. Therefore, it has the advantages of realizing the convenience of the tube and economic benefit.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • this embodiment further cools the distribution position of the first conductive structure 16.
  • the TFT includes at least a source-drain electrode layer; the source-drain electrode layer is divided into a drain 11 and a source 12; and the passivation layer 13 is located on the source-drain electrode layer;
  • the first conductive structure 16 is on the passivation layer 13.
  • the passivation layer 13 is a protective layer of the source and drain electrode layers, and is also an insulating layer.
  • the first conductive structure 16 is disposed on the passivation layer 13 to prevent charges in the first conductive structure 16 from entering the source 12 and the drain 11. In the middle, it interferes with the normal operation of the TFT.
  • the size of the first conductive structure 16 may be larger than the size of the TFT or smaller than the size of the TFT. In the structure shown in FIG. 3, the size of the first conductive structure is larger than the size of the TFT;
  • the second conductive structure 17 is disposed on the passivation layer above the data lines and/or the gate lines to ensure isolation of the second conductive structures 17 from the data lines or gate lines, eliminating the charge pair data derived by the second conductive structures 17.
  • the second conductive structure 17 can be connected to, for example, a ground point on the array substrate to release the charge, thereby avoiding charge accumulation.
  • An electrostatic field is formed between the spacer and the TFT, resulting in the formation of a pressing bright spot.
  • Figure 4 shows the charge formed by the second conductive structure 17 .
  • 21, 22, 23, and 24 are discharge rows of the charge release network
  • 26, 27, 28, and 29 are discharge columns of the charge release network
  • the discharge row isolation is disposed in a region corresponding to the data line
  • discharge The column isolation is set in the region corresponding to the gate line
  • the reference numeral 25 represents the discharge region in which the discharge row and the discharge column are connected.
  • a peripheral discharge region is usually disposed at the periphery of the display region to discharge the charge.
  • the array substrate according to the embodiment by providing the first conductive structure 16 and the second conductive structure 17, prevents the charge accumulation generated by the friction between the spacer and the array substrate from forming an electrostatic field after being assembled into a panel, resulting in an electrostatic field.
  • the TFT is turned off, the off current between the source and the drain is large, forming a pressed bright spot.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the present embodiment provides a display device comprising the array substrate according to any one of Embodiments 1 to 3.
  • the display device can be any product or component having a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet, and the like.
  • the display device further includes an opposite substrate disposed opposite to the array substrate and a spacer between the array substrate and the opposite substrate;
  • At least a portion of the spacer is disposed opposite the first conductive structure.
  • a plurality of spacers are disposed between the opposite substrate and the array substrate, and at least some of the spacers are disposed opposite to the first conductive structure.
  • the opposite substrate may be a color filter substrate, and the spacer is a column spacer disposed in the liquid crystal layer to realize connection and support between the color filter substrate and the array substrate.
  • the opposite substrate is a transparent substrate.
  • the opposite substrate is also a color filter substrate, and the spacer is disposed between the organic light emitting diode materials.
  • the spacer is divided into the main spacer which plays the main supporting role, and the secondary spacer which plays the auxiliary support. According to the size of the panel, the minimum deformation requirement is only relative to the main spacer.
  • the set pixel arrangement may be the array substrate in the embodiment of the invention, or the array substrate described in the embodiment of the invention may be disposed in a form opposite to the spacer, and all the pixels in the array substrate may be The array substrate described in the embodiment of the invention is provided.
  • the display device described in this embodiment is under the action of an external force such as tapping, pressing, and pressing, and the spacer
  • the object is used to prevent excessive deformation of the display device.
  • the spacer and the first conductive structure are rubbed to generate electric charge, the first conductive structure itself and the second conductive structure can be discharged outward in time, thereby effectively avoiding Forming a press highlight to improve the performance of the display device and improve the yield of the display device.
  • Embodiment 5 is a diagrammatic representation of Embodiment 5:
  • the method for fabricating an array matrix of the embodiment includes: a step M of forming a pattern including a TFT, a data line, a gate line, and a passivation layer on the substrate, and a step N,
  • the step N is a pattern of forming a first conductive structure over the TFT on the passivation layer, and forming a pattern of the second conductive structure over the data line and/or the gate line on the passivation layer, and making the first conductive structure A step of connecting to the second electrically conductive structure.
  • the method for fabricating an array substrate of the present embodiment includes: forming a first conductive structure over the TFT on the passivation layer and forming a second conductive structure over the data line and/or the gate line on the passivation layer; In the step of fabricating the array substrate, it is possible to avoid a pressing bright spot due to friction between the spacer and the array substrate.
  • the step N includes:
  • Step N1 depositing a layer of conductive material on the passivation layer
  • Step N2 forming a pattern including the first conductive structure and the second conductive structure by using a patterning process on the conductive material above the TFT; and the first conductive structure is connected to the second conductive structure.
  • the patterning process employed may be a fabrication process of photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the pixel electrode is disposed to be isolated from the first conductive structure and the second conductive structure.
  • first conductive structure and the second conductive structure in the array substrate are interconnected to form a charge release network structure as shown in Fig. 3 for releasing a charge due to friction between the spacer and the TFT.
  • the first conductive structure and the second conductive structure are conductive structures of the same material as the pixel electrodes, and the deposition of the conductive structures corresponding to the first conductive structure and the second conductive structure may be completed while depositing the pixel electrodes. At the same time, the fabrication of the first conductive structure and the second conductive structure is completed while etching the pixel electrode. Compared to the traditional method of fabricating the array substrate, no additional materials and process steps are added.
  • the conductive structure may be ITO
  • the fabrication of the second conductive structure realizes the advantages of turning waste into profit, having a compact structure, making a tube, and the like, and the array substrate produced by the method has less pressing points and good product quality performance, and is particularly suitable for large Pixel production of a small, thin display device.

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Abstract

一种阵列基板（100），包括TFT（10）、数据线（18）、栅线（19）以及覆盖在TFT（10）、数据线（18）以及栅线（19）之上的钝化层（13），还包括第一导电结构（16）以及与第一导电结构（16）相连的第二导电结构（17）；第一导电结构（16）位于钝化层（13）上在TFT（10）上方；第二导电结构（17）位于钝化层（13）上在数据线（18）和/或栅线（19）上方。还提供一种阵列基板（100）的制作方法以及具有这种阵列基板（100）的显示装置。

Description

阵列基板及其制作方法以及显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法， 还涉及具有这种阵列 基板的显示装置。 背景技术
在目前的大型显示面板中， 为了减少面板的形变， 通常在两基板之间设 置隔垫物， 且通常为了避免隔垫物的错位， 例如在液晶面板中通常将彩膜基 板侧的隔垫物与阵列基板侧的薄膜晶体管（ Thin Film Transistor, TFT )相抵 靠。
如图 1所示， 在面板受到震动或敲击等外力作用时， 隔垫物 4与阵列基 板中的钝化层 3之间的相互摩擦会产生静电荷（通常为正电荷） ， 从而形成 电场， 在 TFT的沟道内聚集电荷（通常为电子） ， 使源极 2与漏极 1导通。 而在 TFT的栅极处于低电压， TFT关闭时， 源极 2与漏极 1断开， 若 TFT 的沟道内聚积的电荷足以使源极 2与漏极 1导通， 那么， 漏极 1会向像素电 极 5供电， 从而使面板在显示黑色画面时形成不稳定的按压亮点， 造成面板 的显示不良。
图 2示出了按压亮点形成的等效原理图， 其中虚线表示的是由于隔垫物 与钝化层之间的摩擦而形成的源极 S与漏极 D之间的通路。 当栅极 G与源 极 S之间的电压小于门限电压时， 源极 S与漏极 D之间应当断开， 而在本图 中， 由于聚集的电荷的作用， 源极 S与漏极 D导通， 向电容 Cst充电。 发明内容
本发明的实施例的目的之一在于提供一种能够避免由于隔垫物与 TFT 之间摩擦而形成按压亮点的阵列基板、 该阵列基板的制作方法以及具有该阵 列基板的显示装置。
根据本发明的一个方面，本发明的实施例提供了一种阵列基板，其包括： 位于衬底基板上的 TFT、 数据线、 栅线以及覆盖在 TFT、 数据线以及栅线之 上的钝化层， TFT包括栅极、 源极以及漏极， 数据线与 TFT的源极相连， 栅 线与 TFT的栅极相连；
该阵列基板还包括第一导电结构以及与第一导电结构相连的第二导电结 构；
第一导电结构位于钝化层上且位于 TFT上方；第二导电结构位于钝化层 上且位于数据线和 /或栅线上方。
阵列基板还包括像素电极， 像素电极设置得与第一导电结构以及第二导 电结构隔离， 并与 TFT的漏极相连。
根据本发明的一个实施例， 第一导电结构以及第二导电结构由与所述像 素电极的材料相同的导电材料制成。
根据本发明的一个实施例， 第一导电结构、 第二导电结构以及像素电极 均为 ITO。
本发明的实施例还提供了一种包括上述阵列基板的显示装置， 其能够实 现本发明的实施例的上述目的。
该显示装置还包括与阵列基板相对设置的对置基板以及位于阵列基板与 对置基板之间的隔垫物；
所述隔垫物的至少一部分与第一导电结构接触。
根据本发明的另一方面， 本发明的实施例提供了制作上述阵列基板的方 法， 包括： 在基板上形成有 TFT、 数据线、 栅线及钝化层的图形， 所述制作 方法还包括：
步骤 S: 在钝化层上且在 TFT上方制作第一导电结构的图形， 以及在钝 化层上且在数据线和 /或栅线上方制作第二导电结构的图形， 其中， 第一导电 结构与第二导电结构相连。
例如， 步骤 S包括：
步骤 S1: 在钝化层上沉积一层导电材料；
步骤 S2: 通过构图工艺， 用 TFT上方所述导电材料形成第一导电结构 的图形，以及用数据线和 /或栅线上方的所述导电材料上形成第二导电结构的 图形。
进一步地， 在执行步骤 S2的同时还在导电材料上形成像素电极的图形， 其中， 像素电极设置得与第一导电结构以及第二导电结构隔离。 例如， 在步骤 SI中沉积的导电材料为 ITO。
本发明实施例提供的阵列基板及其制作方法以及具有该阵列基板的显示 装置， 通过在传统的阵列中设置第一导电结构以及与第一导电结构电相连的 第二导电结构， 能够使由于隔垫物与阵列基板之间的摩擦产生的电荷从第一 导电结构以及第二导电结构形成的释放回路向外释放。 从而， 避免了在 TFT 的沟道中形成静电场， 在沟道内不会聚集足够的电荷， 因此， 在 TFT关闭时 TFT的源漏极不会导通产生按压亮点。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。在附图中，用相同的附图标记表示相同或相似的部件。
图 1为惯常的阵列基板与隔垫物接触的结构示意图；
图 2为按压亮点产生的等效原理图；
图 3为本发明阵列基板局部侧视结构示意图；
图 4为本发明阵列基板形成的电荷网络释放网络结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一：
为了克服现有技术中按压亮点， 本实施例提供了一种阵列基板， 该阵列 基板 100包括 TFT 10、 数据线 18、 栅线 19以及覆盖在 TFT 10、 数据线 18、 栅线 19上的钝化层 13, TFT 10包括栅极 14、 源极 12以及漏极 11 , 数据线 18与 TFT 10的源极 12相连， 栅线 19与 TFT 10的栅极 14相连， 该阵列基 板还包括第一导电结构 16以及与第一导电结构电连接的第二导电结构 17; 第一导电结构 16位于钝化层 13上并位于 TFT 10上方； 所述第二导电 结构 17位于钝化层 13上并位于数据线 18和 /或所述栅线 19上方。
阵列基板中的 TFT排成 TFT矩阵， 第一导电结构 16的至少一部分位于 钝化层 13上并位于 TFT上方； 数据线 18以及栅线 19均为多条且呈网状分 布， 第二导电结构 17的至少一部分位于钝化层 13上并位于数据线 18和 /或 栅线 19的上方。
阵列基板中还包括像素电极 15, 所述像素电极 15布置得与第一导电结 构 16以及第二导电结构 17隔离。
TFT包括栅极 14、 源极 12以及漏极 11 ; 栅极 14与栅线 19电连接， 源 极 12与数据线 18电连接， 漏极 11与阵列基板上的像素电极 15电连接； 通 过栅线 19是否向栅极 14供电开启或关闭 TFT, 通过数据线 18由 TFT源极 12至漏极 11向像素电极 15充电， 进而控制显示面板的显示。 在本实施例中 阵列基板还包括第一导电结构 16与第二导电结构 17;第一导电结构 16可以 及时地通过第二导电结构 17将由于阵列基板与隔垫物摩擦而产生的电荷释 放掉，从而避免电荷在 TFT的沟道处形成静电场，使沟道内聚集足够的电荷， 就而导致源极 12和漏极 11之间保持导通，而不再受到栅极 14的控制，形成 按压亮点。
第二导电结构可以设置在栅线上方， 也可以设置在数据线上方， 还可同 时设置在栅线和数据线上方。 这种设置既满足了释放由于隔垫物与阵列基板 之间摩擦产生的电荷的目的， 又避免了对像素电极等结构的干扰。
本实施例所述的阵列基板应用广泛，例如，可以用于平行电场（ IPS, FFS ) 模式、 VA模式等各种显示模式的液晶面板，也可以应用于盒式结构的 OLED 显示面板中。
实施例二：
如图 3所示， 本实施例阵列基板， 包括 TFT、 数据线、 栅线以及覆盖在 TFT、数据线以及栅线上方的钝化层， 阵列基板还包括第一导电结构 16以及 第二导电结构 17, 第二导电结构 17与第一导电结构 16相连；
第一导电结构 16位于钝化层 13上并位于 TFT上方； 第二导电结构 17 位于钝化层 13上并位于数据线和 /或栅线上方。
阵列基板还包括像素电极 15, 该像素电极 15布置得与第一导电结构 16 以及第二导电结构 17隔离； 第一导电结构 16以及第二导电结构 17由与像素电极 15的材质相同的导 电材料制成。
在本实施例中，第一导电结构 16与第二导电结构 17与像素电极 15隔离 设置，即第一导电结构 16、第二导电结构 17与像素电极 15之间没有电连接， 无论是直接或间接的电连接， 这样第一导电结构 16与第二导电结构 17释放 的电荷不会进入像素电极 15, 避免干扰像素的显示。
此外， 第一导电结构 16与第二导电结构 17均可以是任意的导体材料形 成的导电结构，而在本实施例中，使用同一导电材料来形成第一导电结构 16、 第二导电结构 17和像素电极 15, 方便形成这些结构。 可以采用同一构图工 艺在钝化层上形成像素电极 15、 第一导电结构 16以及第二导电结构 17。
通常， 像素电极 15由 ITO ( Indium Tin Oxide, 氧化铟锡， 是一种透明 导电薄膜）制成，在制作像素电极 15时，在整个像素或整个基板上沉积 ITO, 再通过刻蚀 ITO留下有用部分， 而本实施例中将第一导电结构、 第二导电结 构设置成与像素电极具有相同材质的导电结构， 4艮好的利用了废弃的 ITO , 既没有增加成本、 也没有增加制作工艺， 从而具有实现筒便、 经济效益佳的 优点。
实施例三：
如图 3所示， 本实施例进一步筒化了第一导电结构 16的分布位置。
TFT至少包括源漏电极层； 源漏电极层分为漏极 11以及源极 12; 钝化 层 13位于源漏电极层上；
第一导电结构 16位于钝化层 13上。 钝化层 13是源漏电极层的保护层， 同时也是绝缘层， 将第一导电结构 16设置在钝化层 13上， 可以避免第一导 电结构 16中的电荷进入源极 12以及漏极 11中， 干扰 TFT的正常工作。 第 一导电结构 16的尺寸可以大于 TFT的尺寸， 也可以小于 TFT的尺寸， 在图 3所示的结构中， 第一导电结构的尺寸大于 TFT的尺寸；
第二导电结构 17设置在钝化层上在数据线和 /或栅线的上方， 保证了第 二导电结构 17与数据线或栅线的隔离设置， 免除第二导电结构 17导出的电 荷对数据线以及栅线的干扰； 同样，第二导电结构 17的宽度可以大于数据线 或栅线的宽度， 也可以小于数据线或栅线的宽度。 且在设置时可以将第二导 电结构 17连接至例如阵列基板上的接地点，以释放电荷，从而避免电荷聚集 在隔垫物与 TFT之间并形成静电场， 导致形成按压亮点。
图 4示出了由第二导电结构 17形成的电荷! ^放网络。其中，图 4中， 21、 22、 23以及 24为电荷释放网络的放电行， 26、 27、 28以及 29为电荷释放网 络的放电列， 其中放电行隔离设置在对应于数据线的区域， 放电列隔离设置 在对应于栅线的区域，标号 25所代表的为放电行、放电列连接的外围放电区 域。 外围放电区域通常设置在显示区域的外围， 用以释放电荷。
本实施例所述的阵列基板，通过设置第一导电结构 16以及第二导电结构 17, 在组装成面板后防止由于隔垫物与阵列基板之间的摩擦而产生的电荷堆 积形成静电场， 导致在 TFT关闭时， 源漏极之间的关断电流大， 形成按压亮 点。
实施例四：
本实施例提供了一种显示装置， 包括如实施例一至实施例三中的任一个 所述的阵列基板。该显示装置可以是任何具有显示功能的产品或部件，例如， 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等。
进一步地， 显示装置还包括与所述阵列基板相对设置的对置基板以及位 于阵列基板与对置基板之间的隔垫物；
所述隔垫物的至少一部分与第一导电结构相对设置。 对置基板与阵列基 板之间设有多个隔垫物， 这些隔垫物的至少一些与第一导电结构相对设置。
当显示装置为液晶面板时， 对置基板可为彩膜基板， 隔垫物为间杂设置 在液晶层的柱状隔垫物， 用以实现彩膜基板与阵列基板之间的连接与支撑。 当显示装置的阵列基板上设有彩膜片时， 对置基板为透明基板。
当显示装置为 OLED面板时， 对置基板也为彩膜基板， 隔垫物设置在有 机发光二极管材料之间的支撑部件。
在具体的设计中， 隔垫物分为起主要支撑作用的主隔垫物， 以及其辅助 支撑作用的次隔垫物， 可以根据面板的大小， 最小形变的需求仅将与主隔垫 物相对设置的像素设置成本发明实施例中的阵列基板， 也可以是只要是与隔 垫物相对设置的形式均设置成本发明的实施例中所述的阵列基板， 也可以将 阵列基板中所有的像素均设置成本发明实施例中所述的阵列基板。
本实施例中所述的显示装置在敲击、 按压以及挤压等外力作用下， 隔垫 物用以防止显示装置的过度形变， 同时， 在隔垫物与第一导电结构发生摩擦 产生电荷时，可以及时地通过第一导电结构自身以及第二导电结构向外排出， 从而能有效地避免形成按压亮点， 改善显示装置的性能， 提升显示装置的良 率。
实施例五：
本实施例阵列矩阵制作方法包括： 在基板上形成包括有 TFT、 数据线、 栅线及钝化层的图形的步骤 M以及步骤 N,
所述步骤 N为在钝化层上在 TFT上方制作第一导电结构的图形， 以及 在钝化层上在数据线和 /或栅线上方制作第二导电结构的图形，并使第一导电 结构与第二导电结构相连的步骤。
相对于传统的阵列基板制作方法， 本实施例阵列基板制作方法包括在钝 化层上在 TFT上方制作第一导电结构以及在钝化层上在数据线和 /或栅线上 方制作第二导电结构的步骤， 制作出的阵列基板能够避免由于隔垫物与阵列 基板之间的摩擦而产生按压亮点。
所述步骤 N包括：
步骤 N1 : 在钝化层上沉积一层导电材料；
步骤 N2: 在 TFT上方的导电材料上采用构图工艺制作出包含有第一导 电结构、 第二导电结构的图形； 且第一导电结构与第二导电结构相连。
例如， 所采用的构图工艺可以是光刻胶涂敷、 曝光、 显影、 刻蚀、 光刻 胶剥离等的制作工艺。
其中， 像素电极设置得与第一导电结构以及第二导电结构隔离。
例如， 阵列基板中第一导电结构与第二导电结构相互连接形成了如图 3 所示电荷释放网络结构， 用以释放由于隔垫物与 TFT之间的摩擦而产生电 荷。
在本实施例中， 第一导电结构、 第二导电结构是与像素电极同材料的导 电结构， 可以在沉积像素电极的同时， 完成第一导电结构、 第二导电结构所 对应的导电结构的沉积， 同时在刻蚀像素电极的同时完成第一导电结构以及 第二导电结构的制作。 相对于传统的阵列基板制作方法， 没有增加额外的材 质以及工艺步骤。 操作筒单、 实现筒便； 巧妙地利用了在传统的阵列极板制 作方法中废弃的导电结构 （所述导电结构可以为 ITO ) , 实现了第一导电结 构与第二导电结构的制作， 实现了变废为利， 具有结构精巧， 制作筒便等多 重优点， 同时由此方法制作出的阵列基板， 按压亮点少， 产品质量性能好， 尤其适用于大尺寸、 薄型化的显示装置的像素制作。
以上实施方式仅用于说明本发明， 而并非对本发明的限制， 有关技术领 域的普通技术人员， 在不脱离本发明的精神和范围的情况下， 还可以做出各 种变化和变型， 因此所有等同的技术方案也属于本发明的范畴， 本发明的专 利保护范围应由权利要求限定。

Claims

权利要求书
1. 一种阵列基板（100) , 包括位于其上的薄膜晶体管（TFT) ( 10) 、 数据线（ 18 ) 、 栅线（ 19 ) 以及钝化层（ 13 ) , TFT包括栅极（ 14 ) 、 源极 ( 12)以及漏极（ 11 ) , 数据线（ 18 )与 TFT的源极 ( 12 )相连， 栅线（ 19 ) 与 TFT的栅极 ( 14 )相连， 所述钝化层（ 13 )覆盖在所述 TFT ( 10 ) 、 所述 数据线（ 18 ) 以及所述栅线（ 19 )之上，
其中， 所述阵列基板还包括第一导电结构 （16) 以及与所述第一导电结 构相连的第二导电结构 （17) ,
第一导电结构 （ 16)位于钝化层（ 13 )上并位于 TFT ( 10)上方； 第二 导电结构（ 17 )位于钝化层（ 13 )上并位于数据线（ 18 )和 /或栅线（ 19 )上 方。
2. 根据权利要求 1所述的阵列基板， 其中， 第一导电结构（16)通过第 二导电结构 （17)连接至阵列基板上的接地点。
3. 根据权利要求 1或 2所述的阵列基板， 其中， 所述阵列基板还包括设 置在钝化层上的像素电极（ 15 ) 。
4. 根据权利要求 3所述的阵列基板， 其中， 所述像素电极（ 15 )设置得 与第一导电结构 （16) 以及第二导电结构 （17) 隔离。
5. 根据权利要求 3或 4所述的阵列基板， 其中， 所述像素电极（15) 、 第一导电结构 （16)和第二导电结构 （17)是采用同一构图工艺形成的。
6. 根据权利要求 2至 5中任一项所述的阵列基板， 其中， 第一导电结构 (16) 以及第二导电结构 （17) 的材料与像素电极（15) 的材料相同。
7. 根据权利要求 2至 6中任一项所述的阵列基板， 其中， 第一导电结构
(16) 、 第二导电结构 （17) 以及像素电极（15) 的材料均为 ITO。
8. 根据权利要求 1至 7中任一项所述的阵列基板， 其中， 第二导电结构
( 17)形成包括放电行（21, 22, 23, 24)和放电列 （26, 27, 28, 29) 的 电荷释放网络， 所¾ ^电行隔离设置在对应于所述数据线（ 18) 的区域， 所 改电列隔离设置在对应于所述栅线（19) 的区域。
9. 一种显示装置， 包括如权利要求 1至 8中任一项所述的阵列基板。 10. 根据权利要求 9所述的显示装置， 其中， 所述显示装置还包括与所 述阵列基板相对设置的对置基板、 以及位于所述阵列基板与所述对置基板之 间的隔垫物；
所述隔垫物的至少一部分与第一导电结构相对设置。
11. 一种阵列基板的制作方法， 包括： 在基板上形成包括有 TFT、 数据 线、 栅线及钝化层的图形， 其中， 该制作方法还包括：
步骤 S: 在钝化层上在所述 TFT的上方制作第一导电结构的图形， 以及 在钝化层上在所述数据线和 /或栅线上方制作第二导电结构的图形，并使第一 导电结构与第二导电结构相连。
12. 根据权利要求 11所述的阵列基板制作方法， 其中， 所述步骤 S包 括：
步骤 S1 : 在钝化层上沉积一层导电材料；
步骤 S2: 通过构图工艺在位于 TFT的上方的导电材料上形成第一导电 结构的图形，以及位于数据线和 /或栅线上方的导电材料上形成第二导电结构 的图形。
13. 根据权利要求 12所述的阵列基板制作方法， 其中， 在执行步骤 S2 时， 同时还在所述导电材料上形成像素电极的图形，
所述像素电极设置得与所述第一导电结构以及所述第二导电结构隔离。 14. 根据权利要求 12或 13所述的阵列基板制作方法， 其中， 所述步骤 S1中的导电材料为 ITO。
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CN103246099B (zh) 2013-04-27 2016-08-10 京东方科技集团股份有限公司 阵列基板及其制作方法以及显示装置
CN103824876A (zh) * 2014-02-12 2014-05-28 京东方科技集团股份有限公司 一种三维显示面板、其制作方法及三维显示装置
CN107402478B (zh) * 2017-08-17 2021-01-08 惠科股份有限公司 一种显示装置、显示面板及其制作方法
CN107703683A (zh) * 2017-09-26 2018-02-16 武汉华星光电技术有限公司 显示面板及其制作方法
CN107918220A (zh) * 2017-11-16 2018-04-17 京东方科技集团股份有限公司 显示面板和显示装置
CN108169947B (zh) 2018-01-31 2023-04-21 京东方科技集团股份有限公司 阵列基板及其制造方法、触控显示装置

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