WO2014172853A1 - 开关管及其制备方法、显示面板 - Google Patents

开关管及其制备方法、显示面板 Download PDF

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Publication number
WO2014172853A1
WO2014172853A1 PCT/CN2013/074598 CN2013074598W WO2014172853A1 WO 2014172853 A1 WO2014172853 A1 WO 2014172853A1 CN 2013074598 W CN2013074598 W CN 2013074598W WO 2014172853 A1 WO2014172853 A1 WO 2014172853A1
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Prior art keywords
unit volume
protective layer
layer
hydrogen atom
gate insulating
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French (fr)
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江政隆
陈柏林
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/884,299 priority Critical patent/US20140312341A1/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

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  • the invention relates to a switch tube, a preparation method thereof and a display panel.
  • Each pixel of the active matrix screen display is driven by a thin film transistor active device integrated behind the pixel, so that high-speed, high-brightness, high-contrast display screen information can be achieved.
  • Each pixel of the active matrix flat panel display is controlled by a thin film transistor (TFT) integrated on itself, which is an active pixel point.
  • TFT thin film transistor
  • the thin film transistor generally includes a gate electrode, a gate insulating layer, a source/drain layer, a semiconductor layer, and a first protective layer and a second protective layer, and the semiconductor layer is generally preferably IGZO (Indium gallium zinc oxide). O in IGZO is usually combined with external hydrogen, which deteriorates component characteristics and stability.
  • IGZO Indium gallium zinc oxide
  • the technical problem to be solved by the present invention is to provide a switch tube, a preparation method thereof, and a display panel, which can suppress the combination of oxygen atoms of a semiconductor layer in a switch tube and external hydrogen atoms, thereby improving device performance and stability.
  • a technical solution adopted by the present invention is to provide a switching transistor including: a gate electrode; a gate insulating layer covering the gate electrode; and an oxidation formed on the gate insulating layer a semiconductor layer; a first protective layer formed on the oxide semiconductor layer; a source/drain electrode electrically connected to the oxide semiconductor layer; and a second protective layer covering the source/drain electrode;
  • the first protective layer has a hydrogen atom content per unit volume smaller than a hydrogen atom content per unit volume of the gate insulating layer, and a hydrogen atom content per unit volume of the gate insulating layer is smaller than a unit volume of the second protective layer. Hydrogen atom content.
  • the gate insulating layer is an oxide layer of silicon having a hydrogen atom content of more than 5% and less than 10% per unit volume.
  • the first protective layer is an oxide layer of silicon having a unit volume of hydrogen atoms greater than 0 and less than 5%.
  • the second protective layer is a nitride layer of silicon having a unit volume of hydrogen atom content greater than 20%.
  • a display panel including a switch tube, the switch tube including: a gate electrode; a gate insulating layer covering the gate electrode; An oxide semiconductor layer on the gate insulating layer; a first protective layer formed on the oxide semiconductor layer; a source/drain electrode electrically connected to the oxide semiconductor layer; and covering the source/ a second protective layer of the drain electrode; wherein a content of a hydrogen atom per unit volume of the first protective layer is less than a hydrogen atom content per unit volume of the gate insulating layer, and a hydrogen atom content per unit volume of the gate insulating layer is less than The unit volume of the second protective layer is a hydrogen atom content.
  • the gate insulating layer is an oxide layer of silicon having a hydrogen atom content of more than 5% and less than 10% per unit volume.
  • the first protective layer is an oxide layer of silicon having a unit volume of hydrogen atoms greater than 0 and less than 5%.
  • the second protective layer is a nitride layer of silicon having a unit volume of hydrogen atom content greater than 20%.
  • another technical solution adopted by the present invention is to provide a method for preparing a switch tube, comprising: forming a gate electrode on a substrate; forming a gate electrode covering the gate electrode a gate insulating layer; forming an oxide semiconductor layer on the gate insulating layer; forming a first protective layer on the oxide semiconductor layer, and controlling a content of a hydrogen atom per unit volume of the first protective layer to be smaller than a unit volume hydrogen atom content of the gate insulating layer; forming a source/drain electrode on the first protective layer; and forming a second protective layer covering the source/drain electrode on the source/drain electrode And controlling the second protective layer to have a hydrogen atom content per unit volume greater than a hydrogen atom content per unit volume of the gate insulating layer.
  • the step of forming a gate insulating layer covering the gate electrode on the gate electrode comprises: mixing TEOS or SiH 4 with at least one of N 2 O, N 2 , O 2 , O 3 Forming, by the chemical vapor deposition method, the gate insulating layer covering the gate electrode with a hydrogen atom content of more than 5% and less than 10% on the gate electrode; the forming on the oxide semiconductor layer
  • the step of the first protective layer includes: forming a unit volume of hydrogen atoms on the oxide semiconductor layer by chemical vapor deposition using a mixed gas of TEOS or SiH 4 and at least one of N 2 O, N 2 , O 2 , and O 3 The first protective layer having a content greater than 0 and less than 5%.
  • the step of forming a second protective layer covering the source/drain electrodes on the source/drain electrodes comprises: using a mixed gas of SiH 4 , N 2 , and NH 3 by chemical vapor deposition
  • the second protective layer is formed on the source/drain electrodes to cover the source/drain electrodes in a hydrogen atom content of more than 20%.
  • the present invention controls the unit cell volume hydrogen atom content of the first protective layer in the switch tube to be smaller than the unit volume hydrogen atom content of the gate insulating layer, and controls the gate of the switch tube.
  • the content of hydrogen atoms per unit volume of the insulating layer is smaller than the content of hydrogen atoms per unit volume of the second protective layer, so that the content of hydrogen atoms per unit volume of the first protective layer, the gate insulating layer and the second protective layer satisfies the second protective layer>gate insulation
  • the layer>first protective layer enables a significant increase in performance and stability of the display device.
  • FIG. 1 is a schematic structural view of an embodiment of a switch tube according to the present invention.
  • FIG. 2 is a flow chart of one embodiment of a method of manufacturing a switch tube of the present invention.
  • Switching tubes are one of the types of field effect transistors. They are roughly fabricated by depositing various thin films such as a semiconductor active layer, a dielectric layer and a metal electrode layer on a substrate.
  • the switch tube is deposited on the substrate (for example, in a liquid crystal display, where the substrate is mostly glass) as a channel region.
  • a-Si:H hydrogenated amorphous silicon
  • ITO indium tin oxide
  • the oxide semiconductor layer in the switching transistor is usually made of an IGZO material
  • O in the IGZO is combined with external hydrogen, which easily affects the characteristics and stability of the display device. Therefore, how to control the unit volume hydrogen atom content of each structural layer in the switch tube is of great significance for improving device performance and stability.
  • the invention provides a switch tube capable of suppressing the combination of oxygen atoms of a semiconductor layer in a switch tube and external hydrogen atoms, thereby improving device performance and stability.
  • FIG. 1 is a schematic structural diagram of an embodiment of a switch tube according to the present invention.
  • the switch tube includes:
  • a gate electrode 11 a gate insulating layer 12 covering the gate electrode 11; an oxide semiconductor layer 13 formed on the gate insulating layer 12; a first protective layer 14 formed on the oxide semiconductor layer 13; a source/drain electrode 15 electrically connected to the semiconductor layer 13; and a second protective layer 16 covering the source/drain electrode 15; wherein the first protective layer 14 has a hydrogen atom content per unit volume smaller than a unit volume of the gate insulating layer 12. Hydrogen atom content.
  • the gate insulating layer 12 and the first protective layer 14 are both composed of silicon oxide (SiO x ), and the embodiment of the invention is a mixture of TEOS or SiH 4 and N 2 O, N 2 , O 2 , O 3 .
  • the gas is formed by plasma enhanced chemical vapor deposition (PECVD). If the first protective layer 14 and the gate insulating layer 12 contain a high hydrogen atom (H) content, the electrical properties of the switching transistor may be deteriorated.
  • the embodiment of the present invention adopts a higher flow ratio of N 2 O, A mixed gas of N 2 , O 2 , O 3 and TEOS or SiH 4 to reduce the hydrogen atom content per unit volume of the first protective layer 14 formed. Controlling the content of the hydrogen atom per unit volume of the first protective layer 14 to be smaller than the hydrogen atom content per unit volume of the gate insulating layer 12 can improve the performance and stability of the switching tube.
  • the embodiment of the present invention controls the first protective layer 14 to have a hydrogen atom content per unit volume greater than 0 and less than 5%, such as 2% or 4%, and the like.
  • the control gate insulating layer 12 has a hydrogen atom content of more than 5% and less than 10%, such as 6% or 8%.
  • control gate insulating layer 12 has a hydrogen atom content per unit volume smaller than that of the second protective layer 16 unit.
  • the second protective layer 16 is for reducing the influence of ambient moisture and oxygen on the switching tube, and thus is preferably silicon nitride (SiN x ). Embodiments of the present invention are obtained by chemical vapor deposition of a mixed gas of SiH 4 , N 2 , and NH 3 . Therefore, the formed second protective layer 16 has a hydrogen atom content per unit volume much larger than the hydrogen atom content per unit volume of the gate insulating layer 12. In the embodiment of the present invention, the content of the hydrogen atom per unit volume of the second protective layer 16 is controlled to be greater than 20%, such as controlled at 25% or 30%.
  • the present invention can suppress the oxygen concentration of the first protective layer in the switch tube from being smaller than the hydrogen concentration of the gate insulating layer, thereby suppressing the combination of the oxygen atoms of the oxide semiconductor layer in the switch tube and the external hydrogen atoms. Thereby improving device performance and stability.
  • the content of the hydrogen atom per unit volume of the gate insulating layer of the control switch tube is smaller than the hydrogen atom content per unit volume of the second protective layer, so that the first protective layer, the gate insulating layer and the second protective layer have a hydrogen atom per unit volume.
  • the content satisfies the second protective layer>gate insulating layer>first protective layer, so that the performance and stability of the display device can be greatly improved.
  • the invention also provides a method for preparing a diode.
  • FIG. 2 is a flow chart of a method for preparing a diode according to the present invention.
  • the method for preparing a diode includes:
  • Step S101 forming a gate electrode on the substrate
  • a gate electrode is formed on a substrate such as a glass substrate.
  • the gate electrode is an electrode that supplies a gate voltage to the switching transistor.
  • the gate electrode is formed by sputtering, photomask processing from copper, aluminum, molybdenum, titanium or a stacked structure thereof.
  • the thickness of the gate electrode can be controlled between 50 and 200 nm, such as 100 nm or 150 nm.
  • Step S102 forming a gate insulating layer covering the gate electrode on the gate electrode;
  • the gate insulating layer may be made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like.
  • the gate insulating layer is formed by plasma enhanced chemical vapor deposition (PECVD) of a mixed gas of TEOS or SiH 4 and N 2 O, N 2 , O 2 , and O 3 .
  • PECVD plasma enhanced chemical vapor deposition
  • Embodiments of the present invention control the thickness of the gate insulating layer to be between 50 and 200 nm, such as 100 nm or 120 nm.
  • the embodiment of the present invention controls the gate insulating layer to have a hydrogen atom content per unit of more than 5% and less than 10%, such as 6% or 8%.
  • the content of hydrogen atoms per unit volume of the gate insulating layer can be achieved in various ways, which is not strictly limited in the present invention.
  • the hydrogen atom content per unit volume of the gate insulating layer can be controlled by adjusting the flow ratio of N 2 O/SiH 4 .
  • Step S103 forming an oxide semiconductor layer on the gate insulating layer
  • an oxide semiconductor layer is formed by sputtering and a mask process.
  • the oxide semiconductor layer contains at least one of zinc oxide, tin oxide, indium oxide, and gallium oxide.
  • Step S104 forming a first protective layer on the oxide semiconductor layer, and controlling a content of a hydrogen atom per unit volume of the first protective layer to be smaller than a hydrogen atom content per unit volume of the gate insulating layer;
  • a first protective layer is formed by chemical vapor deposition on the oxide semiconductor layer.
  • the first protective layer of the embodiment of the present invention is formed by plasma enhanced chemical vapor deposition (PECVD) of a mixed gas of N 2 O, N 2 , O 2 , O 3 and TEOS or SiH 4 . If the first protective layer and the gate insulating layer contain a high hydrogen atom (H) content, the electrical properties of the switching tube may be deteriorated.
  • PECVD plasma enhanced chemical vapor deposition
  • the embodiment of the invention adopts a higher flow ratio of N 2 O, N 2 , a mixed gas of O 2 , O 3 and TEOS or SiH 4 to reduce the hydrogen atom content per unit volume of the first protective layer formed.
  • Controlling the content of the hydrogen atom per unit volume of the first protective layer is smaller than the content of hydrogen atoms per unit volume of the gate insulating layer, which can improve the performance and stability of the switching tube.
  • the embodiment of the present invention controls the first protective layer to have a hydrogen atom content per unit of more than 0 and less than 5%, such as 2% or 4%, and the like.
  • S105 forming a source/drain electrode on the first protective layer and forming a second protective layer covering the source/drain electrode on the source/drain electrode, and controlling the second protective layer to have a hydrogen atom content per unit larger than the gate insulating layer The unit volume of hydrogen atoms in the layer;
  • the method of fabricating a diode further includes forming a source/drain electrode on the first protective layer; and forming a second protective layer covering the source/drain electrodes on the source/drain electrodes to control the second protective layer
  • the content of hydrogen atoms per unit volume is greater than the content of hydrogen atoms per unit volume of the gate insulating layer.
  • the second protective layer is for reducing the influence of ambient moisture and oxygen on the switching tube, and thus is preferably silicon nitride (SiN x ).
  • Embodiments of the present invention are obtained by chemical vapor deposition of a mixed gas of SiH 4 , N 2 , and NH 3 . Therefore, the hydrogen atom content per unit volume of the formed second protective layer is much larger than the hydrogen atom content per unit volume of the gate insulating layer.
  • the second protective layer has a hydrogen atom content per unit volume of more than 20%, such as 25% or 30%.
  • the above technical solution can suppress the combination of the oxygen atoms of the oxide semiconductor layer in the switch tube and the external hydrogen atoms by controlling the hydrogen concentration of the first protective layer in the switch tube to be smaller than the hydrogen concentration of the gate insulating layer, thereby improving device performance and stability.
  • the content of the hydrogen atom per unit volume of the gate insulating layer of the control switch tube is smaller than the hydrogen atom content per unit volume of the second protective layer, so that the first protective layer, the gate insulating layer and the second protective layer have a hydrogen atom per unit volume.
  • the content satisfies the second protective layer>gate insulating layer>first protective layer, so that the performance and stability of the display device can be greatly improved.

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Abstract

一种开关管及其制备方法、显示面板。开关管包括:栅极电极(11);覆盖栅极电极(11)的栅极绝缘层(12);形成于栅极绝缘层(12)上的氧化物半导体层(13);形成于氧化物半导体层(13)上的第一保护层(14);与氧化物半导体层(13)电连接的源/漏极电极(15);以及覆盖源/漏极电极(15)的第二保护层(16);其中,第一保护层(14)的单位体积氢原子含量小于栅极绝缘层(12)的单位体积氢原子含量。并且栅极绝缘层(12)的单位体积氢原子含量小于第二保护层(16)的单位体积氢原子含量。通过上述方式,能够抑制开关管内半导体层的氧原子与外部氢原子结合,提高器件性能和稳定性。

Description

开关管及其制备方法、显示面板
【技术领域】
本发明涉及一种开关管及其制备方法、显示面板。
【背景技术】
主动矩阵式屏幕显示器每个像素点都是由集成在像素点后面的薄膜晶体管主动装置来驱动,从而可以做到高速度、高亮度、高对比度显示屏幕信息。主动矩阵式平面显示器的每个像素点都是由集成在自身上的薄膜晶体管(TFT)来控制,是有源像素点。
薄膜晶体管通常包括栅极电极、栅极绝缘层、源极/漏极层、半导体层以及第一保护层和第二保护层,而半导体层通常优选IGZO (氧化铟镓锌)。而IGZO中的O通常会与外部的氢进行结合,从而造成元件特性和稳定性劣化。
【发明内容】
本发明主要解决的技术问题是提供一种开关管及其制备方法、显示面板,能够抑制开关管内半导体层的氧原子与外部氢原子结合,提高器件性能和稳定性。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种开关管,包括:栅极电极;覆盖所述栅极电极的栅极绝缘层;形成于所述栅极绝缘层上的氧化物半导体层;形成于所述氧化物半导体层上的第一保护层;与所述氧化物半导体层电连接的源/漏极电极;以及覆盖所述源/漏极电极的第二保护层;其中,所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量,所述栅极绝缘层的单位体积氢原子含量小于所述第二保护层的单位体积氢原子含量。
其中,所述栅极绝缘层为单位体积氢原子含量大于5%小于10%的硅的氧化物层。
其中,所述第一保护层为单位体积氢原子含量大于0小于5%的硅的氧化物层。
其中,所述第二保护层为单位体积氢原子含量大于20%的硅的氮化物层。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种显示面板,包括开关管,所述开关管包括:栅极电极;覆盖所述栅极电极的栅极绝缘层;形成于所述栅极绝缘层上的氧化物半导体层;形成于所述氧化物半导体层上的第一保护层;与所述氧化物半导体层电连接的源/漏极电极;以及覆盖所述源/漏极电极的第二保护层;其中,所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量,所述栅极绝缘层的单位体积氢原子含量小于所述第二保护层的单位体积氢原子含量。
其中,所述栅极绝缘层为单位体积氢原子含量大于5%小于10%的硅的氧化物层。
其中,所述第一保护层为单位体积氢原子含量大于0小于5%的硅的氧化物层。
其中,所述第二保护层为单位体积氢原子含量大于20%的硅的氮化物层。
为解决上述技术问题,本发明采用的还有一个技术方案是:提供一种开关管的制备方法,包括:在基底上形成栅极电极;在所述栅极电极上形成覆盖所述栅极电极的栅极绝缘层;在所述栅极绝缘层上形成氧化物半导体层;在所述氧化物半导体层上形成第一保护层,控制所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量;在所述第一保护层上形成源/漏极电极;以及在所述源/漏极电极上形成覆盖所述源/漏极电极的第二保护层,控制所述第二保护层的单位体积氢原子含量大于所述栅极绝缘层的单位体积氢原子含量。
其中,所述在所述栅极电极上形成覆盖所述栅极电极的栅极绝缘层的步骤包括:使用TEOS或SiH 4 与N 2 O、N 2 、O 2 、O 3 至少一种的混合气体通过化学气相沉积法在所述栅极电极上形成覆盖所述栅极电极单位体积氢原子含量大于5%小于10%的所述栅极绝缘层;所述在所述氧化物半导体层上形成第一保护层的步骤包括:使用TEOS或SiH 4 与N 2 O、N 2 、O 2 、O 3 至少一种的混合气体通过化学气相沉积法在所述氧化物半导体层上形成单位体积氢原子含量大于0小于5%的所述第一保护层。
其中,所述在所述源/漏极电极上形成覆盖所述源/漏极电极的第二保护层的步骤包括:使用SiH 4 、N 2 、NH 3 的混合气体通过化学气相沉积法在所述源/漏极电极上形成覆盖所述源/漏极电极的单位体积氢原子含量大于20%的所述第二保护层。
本发明的有益效果是:区别于现有技术的情况,本发明通过控制开关管内第一保护层的单位体积氢原子含量小于栅极绝缘层的单位体积氢原子含量,并且控制开关管的栅极绝缘层的单位体积氢原子含量小于第二保护层的单位体积氢原子含量,使第一保护层、栅极绝缘层以及第二保护层的单位体积氢原子含量满足第二保护层>栅极绝缘层>第一保护层,从而能够使显示器件的性能和稳定性大幅度提升。
【附图说明】
图1是本发明开关管一个实施方式的结构示意图;
图2是本发明开关管的制备方法一个实施方式的流程图。
【具体实施方式】
开关管是场效应晶体管的种类之一,大略的制作方式是在基板上沉积各种不同的薄膜,如半导体主动层、介电层和金属电极层。
开关管是在基板(如是应用在液晶显示器,则基板大多使用玻璃)上沉积一层薄膜当做通道区。
大部份的开关管是使用氢化非晶硅(a-Si:H)当主要材料,因为它的能阶小于单晶硅(Eg=1.12eV),也因为使用a-Si:H当主要材料,所以TFT大多不是透明的。另外,TFT常在介电、电极及内部接线使用铟锡氧化物(ITO),ITO则是透明的材料。
由于开关管中氧化物半导体层通常采用IGZO材料,IGZO中的O会与外部氢进行结合,容易影响显示器件的特性及稳定性。因此,如何控制开关管内各结构层的单位体积氢原子含量对于提高器件性能及稳定性有重大意义。
本发明提供一种开关管,能够抑制开关管内半导体层的氧原子与外部氢原子结合,提高器件性能和稳定性。
请参阅图1,图1为本发明开关管一个实施方式的结构示意图,开关管包括:
栅极电极11;覆盖栅极电极11的栅极绝缘层12;形成于栅极绝缘层12上的氧化物半导体层13;形成于氧化物半导体层13上的第一保护层14;与氧化物半导体层13电连接的源/漏极电极15;以及覆盖源/漏极电极15的第二保护层16;其中,第一保护层14的单位体积氢原子含量小于栅极绝缘层12的单位体积氢原子含量。
其中,栅极绝缘层12和第一保护层14均为硅的氧化物(SiO x )组成,本发明实施方式是以TEOS或SiH 4 与N 2 O、N 2 、O 2 、O 3 的混合气体进行等离子体增强化学气相沉积法(PECVD)成膜而成。第一保护层14以及栅极绝缘层12如果含有较高的氢原子(H)含量会造成开关管的电性劣化。尤其是在第一保护层14的成膜过程中,氧化物半导体直接暴露于等离子体中,因此第一保护层14在成膜过程中本发明实施方式通过采用较高流量比的N 2 O、N 2 、O 2 、O 3 与TEOS或SiH 4 的混合气体,以减少形成的第一保护层14的单位体积氢原子含量。控制第一保护层14的单位体积氢原子含量小于栅极绝缘层12的单位体积氢原子含量,能够提高开关管的性能及稳定性。
作为一种较优的方案,本发明实施方式控制第一保护层14的单位体积氢原子含量大于0小于5%,比如2%或4%等等。而控制栅极绝缘层12单位体积氢原子含量大于5%小于10%,比如6%或8%等等。
为了更进一步地提高开关管性能,控制栅极绝缘层12单位体积氢原子含量小于第二保护层16单位体积氢原子含量。
第二保护层16是为了减少环境湿气与氧气对于开关管的影响,因此较佳的为硅的氮化物(SiN x )。本发明实施方式是以SiH 4 、N 2 、NH 3 的混合气体通过化学气相沉积成膜得到。因此,形成的第二保护层16单位体积氢原子含量都远大于栅极绝缘层12单位体积氢原子含量。本发明实施方式中,控制第二保护层16单位体积氢原子含量都大于20%,比如控制在25%或30%等。
通过上述实施方式的阐述,可以理解,本发明通过控制开关管内第一保护层的氢浓度小于栅极绝缘层的氢浓度,从而可以抑制开关管内氧化物半导体层的氧原子与外部氢原子结合,从而提高器件性能和稳定性。
更进一步地,控制开关管的栅极绝缘层的单位体积氢原子含量小于第二保护层的单位体积氢原子含量,使第一保护层、栅极绝缘层以及第二保护层的单位体积氢原子含量满足第二保护层>栅极绝缘层>第一保护层,从而能够使显示器件的性能和稳定性大幅度提升。
本发明还提供二极管的制备方法,请参阅图2,为本发明二极管的制备方法的流程图,二极管的制备方法包括:
步骤S101:在基板上形成栅极电极;
在基板上比如玻璃基板上形成栅极电极。栅极电极是给开关管提供栅电压的电极。栅电极由铜、铝、钼、钛或其层叠结构通过溅射及光罩制程形成。栅极电极的厚度可以控制在50-200nm之间,比如100nm或150nm。
步骤S102:在栅极电极上形成覆盖栅极电极的栅极绝缘层;
在栅极电极上,形成覆盖整个栅极电极的栅极绝缘层。栅极绝缘层可以是由氧化硅膜、氮化硅膜、氮氧化硅膜等制成。本发明实施方式中栅极绝缘层是以TEOS或SiH 4 与N 2 O、N 2 、O 2 、O 3 的混合气体进行等离子体增强化学气相沉积法(PECVD)成膜而成。本发明实施方式控制栅极绝缘层的厚度在50-200nm之间,比如100nm或120nm。为了提高显示器件性能及稳定性,本发明实施方式控制栅极绝缘层的单位体积氢原子含量大于5%小于10%,比如6%或8%等等。可以通过多种方式实现栅极绝缘层的单位体积内的氢原子含量,本发明不做严格限定。比如可以通过调节N 2 O/SiH 4 的流量比来实现控制栅极绝缘层的单位体积内的氢原子含量。
步骤S103:在栅极绝缘层上形成氧化物半导体层;
在栅极绝缘层上,通过溅射及光罩制程形成氧化物半导体层。氧化物半导体层包含氧化锌、氧化锡、氧化铟及氧化镓中的至少一种。
步骤S104:在氧化物半导体层上形成第一保护层,控制第一保护层的单位体积氢原子含量小于栅极绝缘层的单位体积氢原子含量;
在氧化物半导体层上通过化学气相沉积形成第一保护层。本发明实施方式的第一保护层是以N 2 O、N 2 、O 2 、O 3 与TEOS或SiH 4 的混合气体进行等离子体增强化学气相沉积法(PECVD)成膜而成。第一保护层以及栅极绝缘层如果含有较高的氢原子(H)含量会造成开关管的电性劣化。尤其是在第一保护层的成膜过程中,氧化物半导体直接暴露于等离子体中,因此第一保护层在成膜过程中本发明实施方式采用较高流量比的N 2 O、N 2 、O 2 、O 3 与TEOS或SiH 4 的混合气体,以减少形成的第一保护层的单位体积氢原子含量。控制第一保护层的单位体积氢原子含量小于栅极绝缘层的单位体积氢原子含量,能够提高开关管的性能及稳定性。
作为一种较优的方案,本发明实施方式控制第一保护层的单位体积氢原子含量大于0小于5%,比如2%或4%等等。
S105:在第一保护层上形成源/漏极电极以及在源/漏极电极上形成覆盖源/漏极电极的第二保护层,控制第二保护层的单位体积氢原子含量大于栅极绝缘层的单位体积氢原子含量;
另一方面,二极管的制备方法还包括在第一保护层上形成源/漏极电极;以及在源/漏极电极上形成覆盖源/漏极电极的第二保护层,控制第二保护层的单位体积氢原子含量大于栅极绝缘层的单位体积氢原子含量。
第二保护层是为了减少环境湿气与氧气对于开关管的影响,因此较佳的为硅的氮化物(SiN x )。本发明实施方式是以SiH 4 、N 2 、NH 3 的混合气体通过化学气相沉积成膜得到。因此,形成的第二保护层的单位体积氢原子含量都远大于栅极绝缘层的单位体积氢原子含量。本发明实施方式情况下,第二保护层的单位体积氢原子含量都大于20%,比如25%或30%。
上述技术方案通过控制开关管内第一保护层的氢浓度小于栅极绝缘层的氢浓度,从而可以抑制开关管内氧化物半导体层的氧原子与外部氢原子结合,从而提高器件性能和稳定性。
更进一步地,控制开关管的栅极绝缘层的单位体积氢原子含量小于第二保护层的单位体积氢原子含量,使第一保护层、栅极绝缘层以及第二保护层的单位体积氢原子含量满足第二保护层>栅极绝缘层>第一保护层,从而能够使显示器件的性能和稳定性大幅度提升。
以上所述仅为本发明的实施方式,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种开关管,其中,包括:
    栅极电极;
    覆盖所述栅极电极的栅极绝缘层;
    形成于所述栅极绝缘层上的氧化物半导体层;
    形成于所述氧化物半导体层上的第一保护层;
    与所述氧化物半导体层电连接的源/漏极电极;以及
    覆盖所述源/漏极电极的第二保护层;
    其中,所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量,所述栅极绝缘层的单位体积氢原子含量小于所述第二保护层的单位体积氢原子含量。
  2. 根据权利要求1所述的开关管,其中,
    所述栅极绝缘层为单位体积氢原子含量大于5%小于10%的硅的氧化物层。
  3. 根据权利要求1所述的开关管,其中,
    所述第一保护层为单位体积氢原子含量大于0小于5%的硅的氧化物层。
  4. 根据权利要求1所述的开关管,其中,
    所述第二保护层为单位体积氢原子含量大于20%的硅的氮化物层。
  5. 一种显示面板,其中,包括开关管,所述开关管包括:
    栅极电极;
    覆盖所述栅极电极的栅极绝缘层;
    形成于所述栅极绝缘层上的氧化物半导体层;
    形成于所述氧化物半导体层上的第一保护层;
    与所述氧化物半导体层电连接的源/漏极电极;以及
    覆盖所述源/漏极电极的第二保护层;
    其中,所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量,所述栅极绝缘层的单位体积氢原子含量小于所述第二保护层的单位体积氢原子含量。
  6. 根据权利要求5所述的显示面板,其中,
    所述栅极绝缘层为单位体积氢原子含量大于5%小于10%的硅的氧化物层。
  7. 根据权利要求5所述的显示面板,其中,
    所述第一保护层为单位体积氢原子含量大于0小于5%的硅的氧化物层。
  8. 根据权利要求5所述的显示面板,其中,
    所述第二保护层为单位体积氢原子含量大于20%的硅的氮化物层。
  9. 一种开关管的制备方法,其中,包括:
    在基底上形成栅极电极;
    在所述栅极电极上形成覆盖所述栅极电极的栅极绝缘层;
    在所述栅极绝缘层上形成氧化物半导体层;
    在所述氧化物半导体层上形成第一保护层,控制所述第一保护层的单位体积氢原子含量小于所述栅极绝缘层的单位体积氢原子含量;
    在所述第一保护层上形成源/漏极电极;以及
    在所述源/漏极电极上形成覆盖所述源/漏极电极的第二保护层,控制所述第二保护层的单位体积氢原子含量大于所述栅极绝缘层的单位体积氢原子含量。
  10. 根据权利要求9所述的制备方法,其中,
    所述在所述栅极电极上形成覆盖所述栅极电极的栅极绝缘层的步骤包括:
    使用TEOS或SiH 4 与N 2 O 、N 2 、O 2 、O 3 至少一种的混合气体通过化学气相沉积法在所述栅极电极上形成覆盖所述栅极电极的单位体积氢原子含量大于5%小于10%的所述栅极绝缘层;
    所述在所述氧化物半导体层上形成第一保护层的步骤包括:
    使用TEOS或SiH 4 与N 2 O 、N 2 、O 2 、O 3 至少一种的混合气体通过化学气相沉积法在所述氧化物半导体层上形成单位体积氢原子含量大于0小于5%的所述第一保护层。
  11. 根据权利要求9所述的制备方法,其中,
    所述在所述源/漏极电极上形成覆盖所述源/漏极电极的第二保护层的步骤包括:
    使用SiH 4 、N 2 、NH 3 的混合气体通过化学气相沉积法在所述源/漏极电极上形成覆盖所述源/漏极电极的单位体积氢原子含量大于20%的所述第二保护层。
PCT/CN2013/074598 2013-04-22 2013-04-24 开关管及其制备方法、显示面板 Ceased WO2014172853A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010067483A1 (ja) * 2008-12-11 2010-06-17 シャープ株式会社 薄膜トランジスタ及びその製造方法
CN101884109A (zh) * 2007-12-04 2010-11-10 佳能株式会社 包含绝缘层的氧化物半导体器件和使用该器件的显示装置
US20110284854A1 (en) * 2010-05-21 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102610618A (zh) * 2011-01-19 2012-07-25 三星电子株式会社 薄膜晶体管阵列面板
CN102800709A (zh) * 2012-09-11 2012-11-28 深圳市华星光电技术有限公司 薄膜晶体管主动装置
CN102856392A (zh) * 2012-10-09 2013-01-02 深圳市华星光电技术有限公司 薄膜晶体管主动装置及其制作方法
CN203225323U (zh) * 2013-03-28 2013-10-02 南京航空航天大学 一种无需匹配网络带有超宽带频道的高隔离微带双工器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017707A (ja) * 2001-07-03 2003-01-17 Toshiba Corp 表示装置用のアレイ基板の製造方法
JP5740270B2 (ja) * 2011-09-27 2015-06-24 株式会社東芝 薄膜トランジスタ、その製造方法、および表示装置
CN203225253U (zh) * 2013-04-22 2013-10-02 深圳市华星光电技术有限公司 开关管及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101884109A (zh) * 2007-12-04 2010-11-10 佳能株式会社 包含绝缘层的氧化物半导体器件和使用该器件的显示装置
WO2010067483A1 (ja) * 2008-12-11 2010-06-17 シャープ株式会社 薄膜トランジスタ及びその製造方法
US20110284854A1 (en) * 2010-05-21 2011-11-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102610618A (zh) * 2011-01-19 2012-07-25 三星电子株式会社 薄膜晶体管阵列面板
CN102800709A (zh) * 2012-09-11 2012-11-28 深圳市华星光电技术有限公司 薄膜晶体管主动装置
CN102856392A (zh) * 2012-10-09 2013-01-02 深圳市华星光电技术有限公司 薄膜晶体管主动装置及其制作方法
CN203225323U (zh) * 2013-03-28 2013-10-02 南京航空航天大学 一种无需匹配网络带有超宽带频道的高隔离微带双工器

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