WO2014169544A1 - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

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WO2014169544A1
WO2014169544A1 PCT/CN2013/080280 CN2013080280W WO2014169544A1 WO 2014169544 A1 WO2014169544 A1 WO 2014169544A1 CN 2013080280 W CN2013080280 W CN 2013080280W WO 2014169544 A1 WO2014169544 A1 WO 2014169544A1
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layer
active layer
insulating layer
forming
interlayer
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French (fr)
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任庆荣
郭炜
卜倩倩
赵磊
王路
姜志强
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • amorphous silicon a-si
  • TFTs thin film transistors
  • Poly-Si polysilicon
  • the conventional polysilicon array substrate includes, in order from bottom to top, a substrate 10, a buffer layer 11 (a laminated structure of SiO x /SiN x ) disposed on the substrate 10, a polysilicon active layer 12, and a gate insulating layer.
  • the layer 13, the gate electrode 14 and the interlayer insulating layer (ILD) 15 further include source and drain metal layer source and drain electrodes (not shown) disposed on the interlayer insulating layer 15, and source and drain metal layer source and drain electrodes.
  • the interlayer via via 100 is in contact with the polysilicon active layer 12 for conduction.
  • the interlayer insulating layer 15 also requires high visible light transmittance.
  • the interlayer insulating layer 15 is mostly made of SiO x and SiN x . Or a laminated structure of SiO x /SiN x as an interlayer insulating layer.
  • a SiO x /SiN x stacked structure is used, in addition to having quite good electrical characteristics, and the working gas for preparing the SiN x layer contains hydrogen, thereby forming a SiN x layer and having an existing film layer. The effect of the hydrogenation treatment is carried out.
  • the prior art has at least the following problems: Since the interlayer insulating layer 15 is generally thick and laminated, in addition to forming the interlayer via 100, the gate insulating layer 13 needs to be etched, and the film layer to be etched is too thick, and the SiO x etching is more difficult than the polysilicon, and the physical etching is performed. Excellent choice of etching process, and the polysilicon of the active layer is relatively thin, often there are areas that are not etched, and some areas are severely over-etched, causing damage to the active layer, seriously affecting product yield, and low temperature. The application of polysilicon technology in large-size displays. Summary of the invention An embodiment of the present invention provides a method of fabricating a thin film transistor, comprising: forming an active layer;
  • An insulating layer is formed on the active layer and the etch barrier layer, and the interlayer via is formed in the insulating layer to expose the etch barrier layer.
  • the forming the insulating layer includes:
  • An interlayer insulating layer is formed over the gate insulating layer.
  • the method further includes:
  • source and drain electrodes are formed on the interlayer insulating layer, and the source and drain electrodes are electrically connected to the active layer through the via holes.
  • the etch barrier layer is a metal film layer or a doped semiconductor film layer.
  • the etch stop layer is made of the same material as the source and drain electrodes.
  • the etch barrier layer is one of a molybdenum metal film, an aluminum metal film, a copper metal film, or a laminated structure of titanium/aluminum/titanium and a laminated structure of molybdenum/aluminum/phase. .
  • the active layer is a polysilicon active layer.
  • the forming the active layer includes:
  • the forming the active layer includes:
  • a portion of the polysilicon layer is doped to form a semiconductor doped region; the doped polysilicon layer is etched to form a polysilicon active layer of the TFT.
  • the etch stop layer has a thickness of 50 ⁇ 300 300 300 ⁇ .
  • An etch stop layer for protecting the active layer when the via is etched between the layers, and is disposed on the active layer to subsequently form an interlayer via
  • the source and drain electrodes, the active layer and the source and drain electrodes are connected through the interlayer via.
  • the thin film transistor further includes:
  • a gate insulating layer disposed on the active layer and the etch barrier layer;
  • a gate electrode disposed on the gate insulating layer
  • An interlayer insulating layer disposed on the gate
  • the interlayer via penetrates through the interlayer insulating layer and the underlying gate insulating layer.
  • the etch barrier layer is a metal film layer or a doped semiconductor film layer.
  • the etch stop layer is made of the same material as the source and drain electrodes.
  • the etch barrier layer is one of a molybdenum metal film, an aluminum metal film, a copper metal film, or a laminated structure of titanium/aluminum/titanium and a laminated structure of molybdenum/aluminum/phase.
  • the active layer is a polysilicon active layer.
  • the etch stop layer has a thickness of 50 ⁇ 300 300 300 ⁇ .
  • Still another embodiment of the present invention provides an array substrate comprising a thin film transistor according to any of the embodiments of the present invention.
  • Yet another embodiment of the present invention provides a display device including a thin film transistor according to any of the embodiments of the present invention.
  • Embodiments of the present invention provide a column substrate and a method for fabricating the same, an array substrate, and a display device, wherein an etch barrier layer is formed on an active layer to form an interlayer via hole, and an interlayer insulating layer is formed to form an interlayer layer
  • an etch barrier layer is formed on an active layer to form an interlayer via hole
  • an interlayer insulating layer is formed to form an interlayer layer
  • the active layer can be protected from being etched, which solves the problems of uneven etching, no etching, excessive etching, etc. during etching of the interlayer insulating layer, and reduces the process defect rate.
  • FIG. 2 is a schematic structural view of an etch barrier layer on a thin film transistor according to Embodiment 1 of the present invention
  • FIG. 3 is a schematic flow chart of forming a polysilicon active layer in Embodiment 2 of the present invention
  • FIG. 4 is a schematic flow chart of forming an etch barrier layer according to Embodiment 2 of the present invention.
  • FIG. 5 is a schematic diagram of a gate insulating layer, a gate electrode, and an interlayer insulating layer according to Embodiment 2 of the present invention
  • FIG. 6 is a schematic view showing formation of interlayer via holes in Embodiment 2 of the present invention
  • FIG. 7 is a schematic diagram of a thin film transistor formed in Embodiment 2 of the present invention. detailed description
  • Embodiments of the present invention provide a column substrate, a method for fabricating the same, and a display device, which can solve the problems of uneven etching, non-etching, over-etching, etc. of the interlayer insulating layer, and reduce the process defect rate.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor. As shown in FIG. 2, the method includes:
  • etch stop layer 16 Form an etch stop layer 16 on the active layer 120 at a position where the interlayer via is formed later, to protect the active layer 120 when the via is etched, the interlayer via (not shown) And is used to connect the active layer 120 and the source and drain electrodes (not shown).
  • an insulating layer may be formed on the active layer 120 and the etch barrier layer 16.
  • the interlayer via is formed in the insulating layer to expose the etch barrier layer.
  • the source-drain electrode may be electrically connected to the active layer 120 through an etch barrier layer exposed in the via hole.
  • the insulating layer described herein may include a gate insulating layer and an interlayer insulating layer which are sequentially stacked.
  • a gate is formed on the gate insulating layer corresponding to a position between two adjacent interlayer via holes.
  • a source electrode and a drain etch barrier layer may be formed at both ends of the active layer, and the two ends may be doped regions. To form a source region and a drain region of the TFT.
  • the interlayer via according to this embodiment is a via hole penetrating all the film layers between the active layer 120 and the source and drain electrodes, and the source electrode and the drain electrode respectively pass through the interlayer via and the doped region of the active layer 120. Electrical connection.
  • the material of the etch barrier layer 16 should be an electrically conductive metal or a doped semiconductor, and the etching is not afraid of residual, so that the active layer 120 can be protected from damage when the via is etched.
  • a metal film layer or a doped semiconductor film layer
  • an etch stop layer 16 is formed by a photolithography process at a position where the interlayer vias are subsequently formed, and the etch barrier layer is formed. 16 is used to protect the active layer 120 when the interlayer via is formed by an etching method, so the area of the etch barrier layer 16 should be larger than the cross-sectional area of the interlayer via.
  • the etch stop layer 16 should have a sufficient thickness to ensure that the interlayer insulating layer on the active layer 120 is completely etched away (for the TFT of the top gate structure, the gate on the active layer 120 is etched away) In the insulating layer and the interlayer insulating layer), the active layer 120 under the gate insulating layer is not damaged, but the thickness of the etch barrier layer 16 is not too thick, so as to prevent the formed step from being too high to affect the deposition of the upper film layer, and the specific implementation
  • the thickness of the etch stop layer 16 is generally selected from 50 ⁇ ⁇ to 300 ⁇ ⁇ .
  • the embodiment of the invention provides a method for preparing a column substrate, wherein an etch barrier layer is formed on the active layer to form an interlayer via hole, and when the etching method is used to form the interlayer via hole, the active layer 120 can be protected. It is not etched, and solves the problems of unevenness, no etching, excessive etching, etc. during etching of the interlayer insulating layer, and reduces the process defect rate.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor. As shown in FIG. 3 to FIG. 5, the method specifically includes:
  • a buffer layer 11 is deposited by chemical vapor deposition (PECVD).
  • PECVD chemical vapor deposition
  • the crystalline silicon layer 121 is then dehydrogenated, and then the amorphous silicon layer 121 is converted into a polysilicon layer (P-Si) 122 by excimer laser crystallization (ELA), and finally the polysilicon layer 122 is subjected to photolithography.
  • Source layer etching using a photoresist as a mask for source-drain doping to form a TFT Active layer 12. It is of course also possible to perform source-drain doping followed by active layer etching (the order of the two steps can be reversed), and then annealing activation to activate the doping ions.
  • the buffer layer 11 has a laminated structure of SiN x /SiO 2 .
  • the interlayer via according to this embodiment is a via hole penetrating the gate insulating layer and the interlayer insulating layer, and the source electrode and the drain electrode in the source/drain electrode respectively pass through the interlayer via and the doped region of the active layer 120. connection.
  • an etch stop layer 16 is formed on the doped polysilicon layer (active layer 12) to protect the active layer when the via is etched.
  • the etch barrier layer 16 is generally made of the same material as the source and drain electrodes, such as molybdenum Mo, aluminum Al, copper Cu, or the like, or a stacked structure of titanium/aluminum/titanium (Ti/Al/Ti), laminated structure molybdenum/ Aluminum bismuth / molybdenum (Mo / AlNd / Mo) and the like.
  • the etching barrier layer 16 selects a metal or metal laminated structure of molybdenum Mo, aluminum Al, copper Cu, etc., and the etching rate is low, and thus the etching barrier layer 16 is not afraid of being over-etched by a small amount, and is not afraid of residue. This avoids poor process due to poor etching uniformity and poor etching selectivity.
  • steps 207-209 continue to deposit the gate insulating layer 13 and the gate metal layer on the active layer 12 provided with the etch barrier layer 16, form the gate electrode 14 by photolithography, and then continue the deposition layer.
  • the gate insulating layer 13 and the interlayer insulating layer 15 are both a SiO x /SiN x stacked structure, and the gate electrode 14 is etched by a Mo metal film.
  • the photoresist 17 is coated on the interlayer insulating layer 15.
  • an etching window 171 in which the photoresist is completely peeled off is formed at a predetermined position of the interlayer via, and then The interlayer insulating layer exposed at the etching window 171 is dry etched to remove the interlayer insulating layer 15 at the etching window 171 and the underlying gate insulating layer 13 to form the interlayer via 100.
  • the subsequent process is continued to form the source and drain electrodes, the pixel electrode (or the pixel electrode and the common electrode), and the passivation protective layer to complete the preparation of the thin film transistor.
  • a source and drain may be formed above the interlayer insulating layer.
  • Electrode 18 The source and drain electrodes 18 are electrically connected to the active layer through the interlayer vias 100.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor, wherein an etch stop layer is formed on a polysilicon active layer at a position where an interlayer via is formed subsequently, and when dry etching is performed to form an interlayer via, the polysilicon can be protected.
  • the source layer is not etched, which solves the problems of unevenness, no etching, excessive etching, etc. during etching of the interlayer insulating layer, and reduces the process defect rate.
  • an embodiment of the present invention further provides a thin film transistor, including: an active layer; an etch stop layer for protecting an active layer when forming interlayer vias, disposed on the active layer The position of the interlayer via is formed by the subsequent layer; the interlayer via is used to connect the active layer and the source and drain electrodes.
  • the thin film transistor further includes:
  • a gate insulating layer disposed on the active layer and the etch barrier layer;
  • a gate electrode disposed on the gate insulating layer
  • An interlayer insulating layer disposed on the gate
  • the interlayer via penetrates through the interlayer insulating layer and the underlying gate insulating layer.
  • the interlayer vias here penetrate the active layer and the insulating layer over the etch stop layer (e.g., including the interlayer insulating layer and the gate insulating layer), so that the source-drain electrodes can be electrically connected to the active layer through the interlayer vias.
  • the embodiment of the invention provides a thin film transistor, wherein an etch stop layer is disposed on the active layer to form an interlayer via hole, and the polysilicon active layer is protected from being formed by dry etching to form an interlayer via. It can solve the problems of unevenness, no etching and over-etching during etching of the interlayer insulating layer, and reduce the process defect rate.
  • the etch barrier layer is a metal film layer or a doped semiconductor film layer.
  • the etch barrier layer is made of the same material as the source and drain electrodes.
  • the etch barrier layer is one of a molybdenum metal film, an aluminum metal film, and a copper metal film, or
  • the active layer is a polysilicon active layer.
  • the etch barrier layer has a thickness of 50 ⁇ 300 ⁇ .
  • the present invention also provides an array substrate comprising any of the thin film transistors described.
  • the present invention also provides a display device comprising any of the thin film transistors described.
  • the array substrate and the display device provided by the present invention successively form interlayer vias on the active layer An etch barrier layer is formed, and when the interlayer via is formed, the active layer can be protected from being etched, thereby solving the problem of unevenness, etching, over-etching, etc. during etching of the interlayer insulating layer, and reducing the process. Bad rate.

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  • Chemical & Material Sciences (AREA)
  • Thin Film Transistor (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

提供了一种薄膜晶体管及其制备方法、阵列基板和显示装置。该薄膜晶体管的制备方法包括：形成有源层；在所述有源层上后继形成层间过孔的位置形成刻蚀阻挡层；在所述有源层和所述刻蚀阻挡层上形成绝缘层，并在所述绝缘层中形成所述层间过孔以露出所述刻蚀阻挡层。

Description

薄膜晶体管及其制备方法、 阵列基板、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板、 显示装 置。 背景技术
现有显示器多基于非晶硅（a-si ) , 即显示面板的薄膜晶体管（Thin Film Transistor, TFT )多采用非晶硅材料。 相比之下， 多晶硅（ Poly-Si )具有更高 的电子迁移率， 被认为是比非晶硅更佳的 TFT制作材料。
如图 1所示， 现有多晶硅阵列基板自下而上依次包括： 基板 10、 设置在 基板 10上的緩沖层 11 ( SiOx/SiNx的叠层结构）、 多晶硅有源层 12、 栅绝缘 层 13、 栅极 14和层间绝缘层（ILD ) 15, 还包括设置在层间绝缘层 15之上 的源漏金属层源漏电极（图中未示出） ， 源漏金属层源漏电极通过层间过孔 100与多晶硅有源层 12接触导通。 层间绝缘层 15除了需要良好的覆盖特性 与绝缘效果外， 还需要高的可见光透过度， 为了达到以上目的及抵挡外来水 汽及机械性刮伤， 层间绝缘层 15 多采用 SiOx、 SiNx或者二者的叠层结构 SiOx/SiNx作为层间绝缘层。 具体实施中多采用 SiOx/SiNx的叠层结构， 除拥 有相当不错的电学特性外， 而且， 制备 SiNx层的工作气体包含氢气， 因此形 成 SiNx层的同时还具有对已有膜层进行氢化处理的效果。
在形成层间过孔 100时， 发明人发现现有技术至少存在如下问题： 由于层间绝缘层 15 —般较厚， 而且是叠层结构， 再加上形成层间过孔 100时， 除刻蚀层间绝缘层 15外还需要刻蚀栅绝缘层 13, 待刻蚀膜层过厚， 并且与多晶硅相比， SiOx刻蚀难度大 4艮多， 物理刻蚀时^ ^调试出二者极佳 的选择刻蚀比工艺， 而且有源层的多晶硅比较薄， 往往出现有的区域没刻蚀 透， 有的区域又严重过刻蚀导致有源层损坏， 严重影响产品良率， 以及低温 多晶硅技术在大尺寸显示上的应用。 发明内容 本发明的一个实施例提供一种薄膜晶体管的制备方法， 包括： 形成有源层；
在所述有源层上后继形成层间过孔的位置形成刻蚀阻挡层；
在所述有源层和所述刻蚀阻挡层上形成绝缘层， 并在所述绝缘层中形成 所述层间过孔以露出所述刻蚀阻挡层。
在一个示例中， 所述形成绝缘层包括：
在设置有刻蚀阻挡层的有源层上形成栅绝缘层；
在所述栅绝缘层之上形成层间绝缘层。
在一个示例中， 该方法还包括：
在形成所述栅绝缘层后且在形成所述层间绝缘层之前， 在所述栅绝缘层 上对应于两个相邻层间过孔之间的位置形成栅极； 以及
在形成所述层间绝缘层之后， 在所述层间绝缘层上形成源漏电极， 所述 源漏极通过所述过孔与所述有源层电连接。
在一个示例中， 所述刻蚀阻挡层为金属膜层或掺杂的半导体膜层。 在一个示例中， 所述刻蚀阻挡层采用与所述源漏电极相同的材质。 在一个示例中， 所述刻蚀阻挡层为钼金属膜、 铝金属膜、 铜金属膜中的 一种， 或者为层叠结构钛 /铝 /钛和层叠结构钼 /铝钕 /相中的一种。
在一个示例中， 所述有源层为多晶硅有源层。
在一个示例中， 所述形成有源层包括：
在基板上形成緩沖层；
在所述緩沖层上形成非晶硅层；
将所述非晶硅层转化为多晶硅层；
刻蚀所述多晶硅层， 形成 TFT的有源层；
对所述有源层的部分区域进行掺杂， 形成半导体掺杂区域；
或者， 所述形成有源层包括：
在基板上形成緩沖层；
在所述緩沖层上形成非晶硅层；
将所述非晶硅层转化为多晶硅层；
对所述多晶硅层的部分区域进行掺杂， 形成半导体掺杂区域； 对掺杂后的多晶硅层进行刻蚀， 形成 TFT的多晶硅有源层。 在一个示例中， 所述刻蚀阻挡层的厚度为 50θΑ~300θΑ。
本发明的另一个实施例提供一种薄膜晶体管， 包括：
有源层；
用以在刻蚀层间过孔时保护有源层的刻蚀阻挡层， 设置在所述有源层上 后继形成层间过孔的位置； 以及
源漏电极， 所述有源层和所述源漏电极通过所述层间过孔连接。
在一个示例中， 该薄膜晶体管还包括：
栅绝缘层， 设置在所述有源层及所述刻蚀阻挡层上；
栅极， 设置在所述栅绝缘层上；
层间绝缘层， 设置在所述栅极之上；
其中， 所述层间过孔贯穿所述层间绝缘层及下方的栅绝缘层。
在一个示例中， 所述刻蚀阻挡层为金属膜层或掺杂的半导体膜层。
在一个示例中， 所述刻蚀阻挡层采用与所述源漏电极相同的材质。
在一个示例中， 所述刻蚀阻挡层为钼金属膜、 铝金属膜、 铜金属膜中的 一种， 或者层叠结构钛 /铝 /钛和层叠结构钼 /铝钕 /相中的一种。
在一个示例中， 所述有源层为多晶硅有源层。
在一个示例中， 所述刻蚀阻挡层的厚度为 50θΑ~300θΑ。
本发明的再一个实施例提供一种阵列基板， 包括根据本发明任一实施例 的薄膜晶体管。
本发明的又一个实施例提供一种显示装置， 包括根据本发明任一实施例 的薄膜晶体管。
本发明实施例提供一种列基板及其制备方法、 阵列基板、 显示装置， 在 有源层上后继形成层间过孔的位置形成刻蚀阻挡层， 在刻蚀层间绝缘层以形 成层间过孔时， 可保护有源层不被刻蚀， 解决了层间绝缘层刻蚀时不均匀、 没刻蚀透、 过度刻蚀等问题， 降低工艺不良率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。 图 1为阵列基板的截面结构示意图；
图 2为本发明实施例一中薄膜晶体管上刻蚀阻挡层的结构示意图； 图 3为本发明实施例二中形成多晶硅有源层的流程示意图；
图 4为本发明实施例二中形成刻蚀阻挡层的流程示意图；
图 5为本发明实施例二中栅绝缘层、 栅极和层间绝缘层的示意图； 图 6为本发明实施例二中形成层间过孔的示意图；
图 7为本发明实施例二中形成的薄膜晶体管的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明的实施例提供一种列基板及其制备方法、 显示装置， 可解决层间 绝缘层刻蚀不均匀、 没刻蚀透、 过度刻蚀等问题， 降低工艺不良率。
实施例一
本发明实施例提供一种薄膜晶体管制备方法，如图 2所示，该方法包括：
101、 形成有源层 120, 在形成有源层 120之后；
102、 在有源层 120上后继形成层间过孔的位置形成刻蚀阻挡层 16, 用 以在刻蚀层间过孔时保护有源层 120, 所述层间过孔（图中未示出 )用以连 接有源层 120和源漏电极（图中未示出 ) 。
在形成刻蚀阻挡层之后，可以在有源层 120和刻蚀阻挡层 16上形成绝缘 层。 上述层间过孔形成在该绝缘层中以露出所述刻蚀阻挡层。 在源漏电极形 例如， 源漏电极可以通过过孔中露出的刻蚀阻挡层与有源层 120电连接。
这里所述的绝缘层可以包括依次层叠的栅极绝缘层以及层间绝缘层。 在 栅极绝缘层上对应于两个相邻层间过孔之间的位置形成栅极。 源极电极和漏 刻蚀阻挡层可以形成在有源层的两个端部，这两个端部可以是掺杂区域， 以形成 TFT的源极区域和漏极区域。
本实施例所述的层间过孔为贯穿有源层 120与源、 漏电极之间所有膜层 的过孔，源电极、漏电极分别通过层间过孔与有源层 120的掺杂区域电连接。
例如，所述刻蚀阻挡层 16的材质应为能导电的金属或掺杂半导体，刻蚀 时不怕有残留， 这样才能在刻蚀层间过孔时保护有源层 120不被损坏。 具体 而言， 本步骤在有源层 120上沉积金属膜层（或掺杂的半导体膜层） ， 通过 光刻工艺在后继形成层间过孔的位置形成刻蚀阻挡层 16, 刻蚀阻挡层 16用 以在采用刻蚀方法形成层间过孔时保护有源层 120, 因此刻蚀阻挡层 16的面 积应大于层间过孔的截面面积。
且， 刻蚀阻挡层 16应具有足够的厚度， 能保证在完全刻蚀掉有源层 120 上的层间绝缘层 (对于顶栅结构的 TFT, 则是刻蚀掉有源层 120上的栅绝缘 层及层间绝缘层） 时， 不损伤栅绝缘层下面的有源层 120, 但是刻蚀阻挡层 16的厚度又不宜太厚， 以免形成的台阶太高影响上面膜层的沉积， 具体实施 中所述刻蚀阻挡层 16的厚度一般选择 50θΑ~300θΑ。
本发明实施例提供一种列基板制备方法， 在有源层上后继形成层间过孔 的位置形成刻蚀阻挡层， 在采用刻蚀方法以形成层间过孔时， 可保护有源层 120 不被刻蚀， 解决了层间绝缘层刻蚀时不均匀、 没刻蚀透、 过度刻蚀等问 题， 降低工艺不良率。
实施例二
进一步地， 本发明实施例还提供一种薄膜晶体管制备方法， 如图 3~5所 示， 该方法具体包括：
201、 在基板 10上形成緩沖层 11;
202、 在所述緩沖层 11上形成非晶硅层 121;
203、 将所述非晶硅层 121转化为多晶硅层 122;
204、 刻蚀所述多晶硅层， 形成 TFT的有源层 12;
205、 对有源层 12的部分区域进行掺杂， 形成半导体掺杂区域； 如图 3所示，可选地，步骤 201~204中首先采用化学气相沉积法（ PECVD ) 沉积緩沖层 11 及非晶硅层 121 , 然后进行脱氢， 再采用准分子激光晶化法 ( ELA )将非晶硅层 121转化为多晶硅层 ( P-Si ) 122, 最后再通过光刻工艺 对多晶硅层 122进行有源层刻蚀，利用光刻胶做掩模进行源漏掺杂，形成 TFT 的有源层 12。 当然也可以先进行源漏掺杂再进行有源层刻蚀 (这两个步骤的 顺序可以调换） ， 然后再进行退火活化， 激活掺杂离子。
例如， 上述緩沖层 11为 SiNx/Si02的叠层结构。
206、 如图 4所示， 沉积金属膜层 160, 通过构图工艺， 在有源层 12上 后继形成层间过孔的位置形成刻蚀阻挡层 16;
本实施例所述的层间过孔为贯穿栅绝缘层和层间绝缘层的过孔， 源漏电 极中的源电极、 漏电极分别通过层间过孔与有源层 120的掺杂区域电连接。
本步骤在掺杂的多晶硅层 (有源层 12 )上形成一层刻蚀阻挡层 16, 用以 在刻蚀层间过孔时保护有源层。例如，该刻蚀阻挡层 16—般采用与源漏电极 相同的材质， 如钼 Mo、铝 Al、铜 Cu等， 或者层叠结构钛 /铝 /钛 ( Ti/Al/Ti ) , 层叠结构钼 /铝钕 /钼（Mo/AlNd/Mo )等。 在刻蚀层间过孔时， 即便刻蚀阻挡 层 16有残留， 也不会影响源、 漏电极与有源层之间的欧姆接触。
刻蚀阻挡层 16选择钼 Mo、 铝 Al、 铜 Cu等金属或金属的层叠结构钛， 刻蚀速率较低，而且这样刻蚀阻挡层 16不怕被少量的过刻蚀，也不怕有残留， 这样就避免了因为刻蚀均一性不好， 以及刻蚀选择比不佳， 而造成的工艺不 良。
207、 在设置有刻蚀阻挡层 16的有源层 12上形成栅绝缘层 13;
208、 在栅绝缘层 13上形成栅极 14;
209、 在栅极 14之上形成层间绝缘层 15;
如图 5所示， 步骤 207~209在设置有刻蚀阻挡层 16的有源层 12上继续 沉积栅绝缘层 13和栅极金属层， 通过光刻工艺形成栅极 14, 然后再继续沉 积层间绝缘层 15。 其中， 栅绝缘层 13和层间绝缘层 15均为 SiOx/SiNx的叠 层结构， 栅极 14为 Mo金属膜刻蚀而成。
210、 刻蚀层间绝缘层 15及下方的栅绝缘层 13, 形成层间过孔。
如图 6所示， 本步骤在层间绝缘层 15涂覆光刻胶 17, 经曝光、 显影后， 在层间过孔的预设位置形成光刻胶完全剥离的刻蚀窗口 171 , 然后再对刻蚀 窗口 171处露出的层间绝缘层进行干法刻蚀， 去除刻蚀窗口 171处的层间绝 缘层 15及下方的栅绝缘层 13,形成层间过孔 100。最后，继续进行后续工序， 形成源、 漏电极、 像素电极（或者像素电极和公共电极）和钝化保护层， 完 成薄膜晶体管的制备。 例如， 如图 7所示， 在层间绝缘层上方可以形成源漏 电极 18。 源漏电极 18通过层间过孔 100与有源层电连接。
本发明实施例提供一种薄膜晶体管制备方法， 在多晶硅有源层上后继形 成层间过孔的位置形成刻蚀阻挡层， 在采用干法刻蚀以形成层间过孔时， 可 保护多晶硅有源层不被刻蚀， 解决了层间绝缘层刻蚀时不均匀、 没刻蚀透、 过度刻蚀等问题， 降低工艺不良率。
实施例三
对应地， 另一方面本发明的实施例还提供一种薄膜晶体管， 包括： 有源 层； 用以在形成层间过孔时保护有源层的刻蚀阻挡层， 设置在所述有源层上 后继形成层间过孔的位置； 所述层间过孔用以连接有源层和源漏电极。
进一步地， 所述的薄膜晶体管， 还包括：
栅绝缘层， 设置在所述有源层及所述刻蚀阻挡层上；
栅极， 设置在所述栅绝缘层上；
层间绝缘层， 设置在栅极之上；
所述层间过孔贯穿所述层间绝缘层及下方的栅绝缘层。
这里的层间过孔贯穿有源层和刻蚀阻挡层上方的绝缘层（例如， 包括层 间绝缘层和栅绝缘层） ， 从而源漏电极能够通过层间过孔与有源层电连接。
本发明实施例提供一种薄膜晶体管， 有源层上后继形成层间过孔的位置 设置有刻蚀阻挡层， 用以在采用干法刻蚀形成层间过孔时保护多晶硅有源层 不被刻独， 可解决层间绝缘层刻蚀时不均匀、 没刻蚀透、 过度刻蚀等问题， 降低工艺不良率。
可选地， 所述刻蚀阻挡层为金属膜层或掺杂的半导体膜层。
可选地， 所述刻蚀阻挡层采用与所述源漏电极相同的材质。
可选地， 所述刻蚀阻挡层为钼金属膜、 铝金属膜、 铜金属膜中的一种， 或者，
层叠结构钛 /铝 /钛和层叠结构钼 /铝钕 /相中的一种。
可选地， 所述有源层为多晶硅有源层。
可选地， 所述刻蚀阻挡层的厚度为 50θΑ~300θΑ。
此外， 本发明还提供一种阵列基板， 包括所述的任一薄膜晶体管。 本发明还提供一种显示装置， 包括所述的任一薄膜晶体管。
本发明提供的阵列基板、 显示装置， 在有源层上后继形成层间过孔的位 置形成刻蚀阻挡层， 在形成层间过孔时， 可保护有源层不被刻蚀， 解决了层 间绝缘层刻蚀时不均匀、 没刻蚀透、 过度刻蚀等问题， 降低工艺不良率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管的制备方法， 包括：
形成有源层；
在所述有源层上后继形成层间过孔的位置形成刻蚀阻挡层；
在所述有源层和所述刻蚀阻挡层上形成绝缘层， 并在所述绝缘层中形成 所述层间过孔以露出所述刻蚀阻挡层。
2、 根据权利要求 1所述的方法， 其中， 所述形成绝缘层包括： 在设置有刻蚀阻挡层的有源层上形成栅绝缘层；
在所述栅绝缘层之上形成层间绝缘层。
3、 根据权利要求 2所述的方法， 还包括：
在形成所述栅绝缘层后且在形成所述层间绝缘层之前， 在所述栅绝缘层 上对应于两个相邻层间过孔之间的位置形成栅极； 以及
在形成所述层间绝缘层之后， 在所述层间绝缘层上形成源漏电极， 所述 源漏极通过所述过孔与所述有源层电连接。
4、 根据权利要求 1-3中任一项所述的方法， 其中，
所述刻蚀阻挡层为金属膜层或掺杂的半导体膜层。
5、 根据权利要求 3所述的方法， 其中，
所述刻蚀阻挡层采用与所述源漏电极相同的材质。
6、 根据权利要求 4所述的方法， 其中， 所述刻蚀阻挡层为钼金属膜、 铝 金属膜、 铜金属膜中的一种， 或者为层叠结构 4 /铝 /钛和层叠结构钼 /铝钕 /钼 中的一种。
7、 根据权利要求 1-6中任一项所述的方法， 其中，
所述有源层为多晶硅有源层。
8、根据权利要求 1-7中任一项所述的方法，其中，所述形成有源层包括： 在基板上形成緩沖层；
在所述緩沖层上形成非晶硅层；
将所述非晶硅层转化为多晶硅层；
刻蚀所述多晶硅层， 形成 TFT的有源层；
对所述有源层的部分区域进行掺杂， 形成半导体掺杂区域； 或者， 所述形成有源层包括：
在基板上形成緩沖层；
在所述緩沖层上形成非晶硅层；
将所述非晶硅层转化为多晶硅层；
对所述多晶硅层的部分区域进行掺杂， 形成半导体掺杂区域；
对掺杂后的多晶硅层进行刻蚀， 形成 TFT的多晶硅有源层。
9、 根据权利要求 1-8中任一项所述的方法， 其中，
所述刻蚀阻挡层的厚度为 50θΑ~300θΑ。
10、 一种薄膜晶体管， 包括：
有源层；
用以在刻蚀层间过孔时保护有源层的刻蚀阻挡层， 设置在所述有源层上 后继形成层间过孔的位置； 以及
源漏电极， 所述有源层和所述源漏电极通过所述层间过孔连接。
11、 根据权利要求 10所述的薄膜晶体管， 还包括：
栅绝缘层， 设置在所述有源层及所述刻蚀阻挡层上；
栅极， 设置在所述栅绝缘层上；
层间绝缘层， 设置在所述栅极之上；
其中， 所述层间过孔贯穿所述层间绝缘层及下方的栅绝缘层。
12、 根据权利要求 10或 11所述的薄膜晶体管， 其中，
所述刻蚀阻挡层为金属膜层或掺杂的半导体膜层。
13、 根据权利要求 10-12中任一项所述的薄膜晶体管， 其中，
所述刻蚀阻挡层采用与所述源漏电极相同的材质。
14、根据权利要求 13所述的薄膜晶体管， 其中， 所述刻蚀阻挡层为钼金 属膜、 铝金属膜、 铜金属膜中的一种， 或者层叠结构 4 /铝 /钛和层叠结构钼 / 铝钕 /相中的一种。
15、 根据权利要求 10-14中任一项所述的薄膜晶体管， 其中，
所述有源层为多晶硅有源层。
16、 根据权利要求 10-15中任一项所述的薄膜晶体管， 其中，
所述刻蚀阻挡层的厚度为 50θΑ~300θΑ。
17、 一种阵列基板， 包括权利要求 10-16中任一项所述的薄膜晶体管。 、 一种显示装置， 包括权利要求 10-16中任一项所述的薄膜晶体管,
PCT/CN2013/080280 2013-04-17 2013-07-29 薄膜晶体管及其制备方法、阵列基板、显示装置 Ceased WO2014169544A1 (zh)

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