WO2014154637A1 - Verfahren zum verbinden von fügepartnern mittels isothermer erstarrungsreaktion zur bildung einer in-bi-ag-verbindungsschicht und entsprechende anordnung von fügepartnern - Google Patents
Verfahren zum verbinden von fügepartnern mittels isothermer erstarrungsreaktion zur bildung einer in-bi-ag-verbindungsschicht und entsprechende anordnung von fügepartnern Download PDFInfo
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- WO2014154637A1 WO2014154637A1 PCT/EP2014/055848 EP2014055848W WO2014154637A1 WO 2014154637 A1 WO2014154637 A1 WO 2014154637A1 EP 2014055848 W EP2014055848 W EP 2014055848W WO 2014154637 A1 WO2014154637 A1 WO 2014154637A1
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- layer
- bismuth
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- sequence
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
- H10P14/44—Physical vapour deposition [PVD]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
- H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
- H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
- H10W72/01333—Manufacture or treatment of die-attach connectors using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
- H10W72/01335—Manufacture or treatment of die-attach connectors using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
- H10W72/01338—Manufacture or treatment of die-attach connectors using blanket deposition in gaseous form, e.g. by CVD or PVD
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/013—Manufacture or treatment of die-attach connectors
- H10W72/01365—Thermally treating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07332—Compression bonding, e.g. thermocompression bonding
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07341—Controlling the bonding environment, e.g. atmosphere composition or temperature
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
- H10W72/07355—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/321—Structures or relative sizes of die-attach connectors
- H10W72/322—Multilayered die-attach connectors, e.g. a coating on a top surface of a core
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/925—Bond pads having a filler embedded in a matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Definitions
- the document DE 102005029246 describes a method for forming a solder joint between a carrier and a semiconductor chip.
- An object to be solved is to provide a method for joining two joining partners, in which a
- connection between the joining partners can be made at a relatively low temperature, wherein the compound thus prepared is particularly temperature-stable.
- firstly a first joining partner and a second joining partner are provided.
- the joining partners may be
- S13N4 or A1N ceramic wafers or the like For example, with the
- an optoelectronic semiconductor chip for example, a light-emitting diode chip, are mounted on a printed circuit board or a metallic lead frame.
- a first layer sequence is applied to the first joining partner.
- the first layer sequence comprises at least one layer which contains at least one metal or consists of a metal. The application of the first layer sequence to the first
- Joining partner can, for example, by physical
- Vapor deposition such as sputtering or vapor deposition
- a second layer sequence is applied to the second joining partner
- the application of the second layer sequence can be carried out by the same method as the application of the first layer sequence.
- Layers can be identical. However, it is also possible for the first and the second layer sequence to differ from one another with regard to their structure, ie the sequence of the layers in the layer sequence and / or with regard to the materials used for the layers of the layer sequence. Furthermore, it is possible that the first and the second layer sequence with different
- the first layer sequence and the second layer sequence are pressed together at their end faces facing away from the first joining partner and the second joining partner, using a joining pressure at a joining temperature for a predetermined joining time. That is to say, the first layer sequence is first brought into contact with its end face facing away from the first joining partner with the end face of the second layer sequence facing away from the second joining partner. Then, a compression of the two layer sequences takes place at the End faces using a joining pressure at a
- the first layer sequence comprises at least one layer which contains silver or which consists of silver.
- the first layer sequence then also consist of this silver layer.
- the second layer sequence comprises at least one layer containing indium and bismuth, or the second layer sequence contains at least one layer containing indium and one layer containing bismuth. In other words, the second layer sequence contains at least indium and bismuth as metals.
- the second layer sequence also contains no other metals.
- the metals indium and bismuth can occur in the second layer sequence in a single common layer, for example as indium-bismuth alloy.
- the second layer sequence contains at least one single layer consisting of indium and a single layer consisting of bismuth.
- the first layer and / or the second layer are free of lead and / or tin.
- the first layer and / or the second layer may be free of gold.
- the joining temperature to which the first layer sequence and the second layer sequence are heated during the joining is at most 120 ° C.
- the first layer sequence and the second layer sequence merge or fuse at this temperature to the connecting layer, which then contains silver, indium and bismuth and melts only at much higher temperatures from about 260 ° C.
- the method comprises
- the first layer sequence comprises at least one layer which contains silver or which consists of silver
- the second layer sequence comprises at least one layer which contains indium and bismuth
- the second layer sequence comprises at least one layer which contains indium and a layer which contains bismuth
- the joining temperature is at most 120 ° C
- the first layer sequence and the second layer sequence merge into a connecting layer, which borders directly on the first joining partner and the second joining partner.
- Soft solder processes are based, for example, on Sn-Ag-Cu (SaC) material systems or on Sn-Pb material systems.
- TLPS Transient Liquid Phase Sintering Pastes
- Fluxes which are intended to ensure the reactivity of the non-noble component of Bi-Sn are embedded in the adhesive matrix.
- the method described here is based inter alia on the idea of using an isothermal solidification process, which on the one hand melts at a lower temperature Component as it is Sn or AuSn uses, and on the other avoids the expensive precious metal gold.
- the first and / or the second layer can thus be free of lead, tin and / or gold, which is normally present at
- connection method find use. Furthermore, thin layers for producing the first and second
- Layer sequence used whereby a particularly simple melting of the layer sequences can be done.
- low-melting component is a mixture of
- the low-melting component can consist of a bismuth-indium alloy or it can be generated in situ during the joining process from the reaction of pure bismuth layers and indium layers with each other.
- the connecting layer has areas containing bismuth or consisting of bismuth, the areas being completely enclosed by a material containing indium and / or silver. It turned out that the
- Bonding layer is particularly stable, in particular thermally stable, if after the joining process, the bismuth component of the bonding layer, in the small amounts of Indium and silver can be dissolved, no coherent, uninterrupted layer forms.
- the bismuth component of the bonding layer in the small amounts of Indium and silver can be dissolved, no coherent, uninterrupted layer forms.
- Melting temperature can be increased significantly compared to the joining temperature.
- the melting temperature in ° C may be at least twice as high as the bonding temperature
- the choice of the joining time can achieve that one in the first or second layer sequence
- the bonding layer then no longer has a continuous bismuth layer, but is free of such a layer consisting of bismuth or the bonding layer is free of a simply continuous layer consisting of bismuth.
- the bismuth layer can then be formed, for example, reticulated, that is, it has holes or openings, with the other metals of the
- Layer sequence or the second layer sequence existing bismuth layer into individual grains, which are surrounded by the material of the other metals of the layer sequences, ie in particular indium and silver.
- the bismuth grains ie the areas that contain bismuth or consist of bismuth, are in a matrix of intermetallic compounds of silver and indium or in a silver-indium alloy with silver grains in which indium is dissolved is a particularly favorable microstructure of the joining zone and thus the connecting layer.
- the proportion of the cross-sectional area consisting of bismuth is at most 50%.
- the cross-sectional area may extend, for example, through the entire connecting layer from the first joining partner to the second joining partner.
- Cross-sectional area is then an arbitrary section through the connecting layer, which runs for example perpendicular to the main extension plane of the two joining partners.
- this cross-sectional area preferably at most half of the area is bismuth with the remainder distributed on silver and indium and any other metals present on average.
- the connecting layer preferably at most half of the area is bismuth with the remainder distributed on silver and indium and any other metals present on average.
- connection layer is electrically conductive. That is, the
- Bonding layer does not just provide a mechanical
- connection between the two joining partners can be connected by the connecting layer and electrically conductive with each other.
- an optoelectronic semiconductor chip can be mechanically fastened and electrically connected to a printed circuit board.
- the electrically conductive connection can in particular be produced by the silver component in the connection layer, which connects the joining partners via paths which are not separated by a
- the bonding layer is free of gold and free of flux.
- the absence of gold in the bonding layer leads to a particularly cost-effective bonding layer, which can be produced at particularly low temperatures.
- the low bonding temperature caused by the choice of a
- Metal alloy is possible, reduces the thermo-mechanical stress in a composite of materials of different thermal expansion behavior and protects
- the method to connect two joining partners, which consist of materials of different thermal expansion behavior.
- the first joining partner may be at least one optoelectronic semiconductor chip, while the second joining partner may be a plastic-encased
- Joining partners include a metal, a ceramic or a plastic, while the second joining partner is formed with at least one other metal, at least one other ceramic or at least one other plastic, wherein the at least one metal, the at least one ceramic or the at least one plastic of the second Joining partner has a different thermal expansion coefficient than the metal, the ceramic or the plastic of the first
- the metals mentioned in the first and in the second layer sequence can be applied very pure, can the use of flux is waived. As a result, the connecting layer is free of flux. But also a low thermal conductivity of a metal-polymer hybrid is avoided. Furthermore, the absence of flux, the risk of corrosion of trapped
- the compound layer is also particularly well suited for dissipating heat loss. It turns out to be
- the connecting layer is free of a continuous layer of bismuth, since bismuth of the said metals has the lowest thermal conductivity.
- the proportion of silver in the connecting layer is as high as possible and the proportion of bismuth is chosen as small as possible.
- the proportion of silver as high as possible and to choose the proportion of bismuth as low as possible.
- the first layer sequence and / or the second layer sequence comprises a layer or a sequence of directly adjoining layers, wherein the layer or the sequence of layers contains only indium and bismuth, wherein the
- Mole fraction of indium is at least 67 at% and at most 85 at%. Optimally, the mole fraction of indium is 78.5 at%. With such an indium content in the range of
- the first layer sequence and / or the second layer sequence comprises at least one layer consisting of indium and at least one layer consisting of bismuth, wherein the layer of indium and the layer of bismuth adjoin one another directly. That is, in this case, the low-melting lies
- Component of bismuth and indium is not present in an alloy, but the low-melting component is during the joining process from the reaction of the immediate
- the second layer sequence consists of a layer which is provided with a Bismuth-indium alloy is formed.
- the low-melting component is thus carried out directly as an alloy and not in individual separate bismuth layers and indium layers on top of each other
- the first layer sequence and / or the second layer sequence comprises a layer which consists of titanium and which directly adjoins a layer of indium or a layer of bismuth, wherein the layer of titanium is intended to mix Delaying silver with indium and / or bismuth.
- a portion of the layer sequence containing indium and bismuth may pass through the titanium layer during the process
- the titanium layer breaks open, for example, and allows penetration of silver in the area with indium and bismuth and thus the isothermal solidification to form the bonding layer.
- the first layer sequence and / or the second layer sequence comprises a sequence of layers of indium and layers
- Bismuth the sequence being covered at their faces by a layer of titanium. That is, a region in the layer sequences formed with indium and bismuth may exist through titanium layers at both ends
- At least half of the layers are of titanium or each
- Layer of titanium which is used in the layer sequences, while a thickness of at most 10 nm. That is, to protect the layers of indium and bismuth, extremely thin titanium layers are sufficient.
- At least half of the layers of indium or each layer of indium is thicker than at least half of the indium
- Layers of bismuth or each layer of bismuth in the layer sequences wherein at least half of the layers of indium or each layer of indium has a thickness of at least 150 nm and at most 850 nm, and
- each layer of bismuth has a thickness of at least 50 nm and at most 300 nm.
- Layers of indium and bismuth can then be adjusted to the indium content in the indium-bismuth system, with an optimal indium content between 67 at% and 85 at% being aimed at as described above.
- At least some layers, in particular all layers, of the first and the second layer sequence are produced by means of at least one of the following deposition techniques: physical vapor deposition such as sputtering or vapor deposition. With these techniques, especially thin layers can be used for
- the arrangement comprises a first joining partner and a second joining partner, and a connecting layer which directly adjoins the first joining partner and the second joining partner, wherein the connecting layer comprises regions, the bismuth
- FIGS 4, 5 show embodiments of methods described herein.
- FIG. 6 shows an arrangement of joining partners produced by means of the method described here
- a first joining partner 1 is shown, which may be, for example, a light-emitting diode chip.
- the first joining partner 1 is connected to the second joining partner 2, which may be, for example, a copper conductor frame encased in plastic.
- the first layer sequence 10 is applied, which in this case consists of a
- the silver layer 11 exists.
- the silver layer 11 has
- a thickness of 1825 nm for example, a thickness of 1825 nm.
- a second layer sequence 20 is applied, which in the present case comprises a 270 nm thick bismuth layer 22, a 730 nm thick indium layer 23 and a 135 nm thick silver layer 25.
- the first layer sequence 10 and the second layer sequence 20 are pressed together at their first joining partner 1 and the second joining partner 2 respectively facing end faces under the pressure p, wherein the assembly is compressed at a bonding temperature of 100 ° C for 0.5 s.
- Silver layers 11, 25 form a sufficient protection against oxidation and especially in sulfur-free atmosphere
- FIG. 2 An exemplary embodiment is described in connection with FIG. 2, in which the first layer sequence 10 having a 2560 nm thick silver layer 11, a 161 nm thick bismuth layer 12, an 804 nm thick indium layer 13, a 147 nm thick bismuth layer 14 and a 74 nm thick silver layer 15 is sputtered on.
- the second layer sequence 20 is applied with the same sequence of layers as follows: a 2560 nm thick silver layer 21, a 161 nm thick
- Bismuth layer 22 an 804 nm thick indium layer 23, a 147 nm thick bismuth layer 24 and a 74 nm thick
- the joining partners 1, 2 After the end-side merging of the layer sequences, the joining partners 1, 2 for a joining time of about 5 minutes at a bonding temperature of 85 ° C and a
- Joining partners 1, 2 are, for example, a ceramic board and a metal core board.
- the second layer sequence 20 on the second joining partner 2 comprises a 428 nm thick indium layer 23, a 72 nm thick bismuth layer 24 and a 190 nm thick silver layer 25, each by vapor deposition be applied.
- a joining temperature of 115 ° C and a joining pressure of 10 bar the two joining partners 1, 2 are pressed together for 120 minutes and in this way
- the indium bismuth layer 29 consists of an indium-bismuth alloy with 33.3 mass percent bismuth deposited by sputtering or plasma spraying and having a thickness of 775 nm.
- Bonding temperature of 95 ° C over a joining time of 30 minutes.
- FIG. 5 An exemplary embodiment is described in conjunction with FIG. 5, in which a silver layer 11 with a thickness of at least 160 nm and at most 1500 nm, for example 1350 nm, is applied to the first joining partner as the first layer sequence 10.
- On the second joining partner 2 is a layer stack of five pairs of 187 nm thick indium layer 23 and 63 nm thicker over a 1000 nm thick silver layer 21
- the bismuth layer 24 is vapor-deposited, which is covered by an 8 nm-thick titanium layer 26 separated by a 260 nm-thick silver layer 25.
- the titanium layer 26 protects against premature mixing of bismuth or indium on the one hand and silver on the other.
- Titanium layer can also be introduced between the silver layer 21 and the layer stack of indium and bismuth. Furthermore, it is possible to introduce such a titanium layer also between each pair of indium and bismuth layers, if mixing is to be delayed for a particularly long time.
- the bonding layer 30 shown to an arrangement of joining partners described here, which is produced by a method described herein.
- the bonding layer 30 comprises regions 32 containing bismuth or consisting of bismuth. For example, the areas 32 are around
- Bismuth grains in which small amounts of silver and / or indium may be dissolved.
- the bismuth regions 32 are
- the area fraction of the areas of bismuth in the cross section shown here is preferably at most 15%.
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- Die Bonding (AREA)
- Led Device Packages (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016504616A JP6184582B2 (ja) | 2013-03-26 | 2014-03-24 | In−bi−ag接合層を形成するための等温凝固反応を用いた接合パートナーの接合方法及び対応する複数の接合パートナーの配置構成 |
| KR1020157030358A KR102172348B1 (ko) | 2013-03-26 | 2014-03-24 | In-bi-ag 연결 층을 형성하기 위해 등온 응고 반응을 이용한 접합부들의 연결 방법, 및 접합부들의 상응하는 배열체 |
| US14/773,970 US9502376B2 (en) | 2013-03-26 | 2014-03-24 | Process for connecting joining parts |
| DE112014001708.6T DE112014001708A5 (de) | 2013-03-26 | 2014-03-24 | Verfahren zum Verbinden von Fügepartnern mittels isothermer Erstarrungsreaktion zur Bildung einer In-Bi-Ag-Verbindungsschicht und entsprechende Anordnung von Fügepartnern |
| CN201480018514.8A CN105103287B (zh) | 2013-03-26 | 2014-03-24 | 借助于等温凝固反应来连接接合配对件以形成In‑Bi‑Ag 连接层的方法和接合配对件的相应装置 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102013103081.5 | 2013-03-26 | ||
| DE102013103081.5A DE102013103081A1 (de) | 2013-03-26 | 2013-03-26 | Verfahren zum Verbinden von Fügepartnern und Anordnung von Fügepartnern |
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| DE (2) | DE102013103081A1 (de) |
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| DE102015114088B4 (de) * | 2015-08-25 | 2022-02-03 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Bauelement und Verfahren zur Herstellung eines Bauelements |
| EP3226282A1 (de) | 2016-03-31 | 2017-10-04 | Techni Holding AS | Nicht eutektisches verbindungsverfahren mit bildung eines mischkristalls mit poröser struktur mit darin dispergierter zweiter phase und entsprechende verbindung |
| DE102017107961B4 (de) * | 2017-04-12 | 2022-10-13 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung einer Beleuchtungseinrichtung und Beleuchtungseinrichtung |
| TWI622653B (zh) * | 2017-05-25 | 2018-05-01 | 綠點高新科技股份有限公司 | 焊料合金及焊料組成 |
| US10700036B2 (en) * | 2018-10-19 | 2020-06-30 | Toyota Motor Engineering & Manufacturing North America, Inc. | Encapsulated stress mitigation layer and power electronic assemblies incorporating the same |
| WO2020148626A1 (fr) * | 2019-01-16 | 2020-07-23 | Patek Philippe Sa Geneve | Procédé de brasage de composants horlogers |
| JP7021792B2 (ja) * | 2019-05-07 | 2022-02-17 | ライトメッド (ユーエスエー) インク | 半導体デバイスと熱拡散マウントとの銀-インジウム過渡液相接合方法および銀-インジウム過渡液相接合ジョイントを有する半導体構造 |
| US20220304186A1 (en) * | 2021-03-17 | 2022-09-22 | Amulaire Thermal Technology, Inc. | Heat-dissipating substrate with coating structure |
| US20230235978A1 (en) * | 2021-03-17 | 2023-07-27 | Amulaire Thermal Technology, Inc. | Heat-dissipating substrate with coating structure |
| FI20245066A1 (en) * | 2024-01-23 | 2025-07-24 | Teknologian Tutkimuskeskus Vtt Oy | Elevations connected with indium |
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Also Published As
| Publication number | Publication date |
|---|---|
| DE102013103081A1 (de) | 2014-10-02 |
| JP2016515763A (ja) | 2016-05-30 |
| KR20150135419A (ko) | 2015-12-02 |
| KR102172348B1 (ko) | 2020-10-30 |
| US20160027759A1 (en) | 2016-01-28 |
| CN105103287B (zh) | 2018-03-23 |
| DE112014001708A5 (de) | 2015-12-24 |
| JP6184582B2 (ja) | 2017-08-23 |
| US9502376B2 (en) | 2016-11-22 |
| CN105103287A (zh) | 2015-11-25 |
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