WO2014154000A1 - 一种封装基板及其制作方法和基板组件 - Google Patents

一种封装基板及其制作方法和基板组件 Download PDF

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Publication number
WO2014154000A1
WO2014154000A1 PCT/CN2013/090743 CN2013090743W WO2014154000A1 WO 2014154000 A1 WO2014154000 A1 WO 2014154000A1 CN 2013090743 W CN2013090743 W CN 2013090743W WO 2014154000 A1 WO2014154000 A1 WO 2014154000A1
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WO
WIPO (PCT)
Prior art keywords
substrate unit
shielding
groove
copper foil
foil layer
Prior art date
Application number
PCT/CN2013/090743
Other languages
English (en)
French (fr)
Inventor
高成志
徐艺林
郑仰存
谷新
黄良松
Original Assignee
深南电路有限公司
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Application filed by 深南电路有限公司 filed Critical 深南电路有限公司
Publication of WO2014154000A1 publication Critical patent/WO2014154000A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of circuit board processing technologies, and in particular, to a package substrate, a method for fabricating the same, and a substrate assembly.
  • the conventional buried circuit board is usually formed by slotting a circuit board, embedding an electronic component such as a chip or the like in the opened slot, and fixing it.
  • the electronic components buried in this type of circuit board are subject to external electromagnetic interference and cannot work optimally.
  • a shield is added to the circuit board to avoid electromagnetic interference.
  • the shield increases the thickness of the board and reduces the versatility of the product, which is not conducive to miniaturization, and the shield is not reliable enough, and there is a risk of failure such as displacement or shedding. Summary of the invention
  • Embodiments of the present invention provide a package substrate, a manufacturing method thereof, and a substrate assembly, which solve the defects caused by electromagnetic shielding of a circuit board by using a shield cover in the prior art.
  • a first aspect of the present invention provides a method of fabricating a package substrate, including: processing a shielding groove around a periphery of each package substrate unit on a substrate; metallizing a sidewall of the shielding groove; filling the shielding groove with a resin And filling the opening of the shielding groove after filling; removing the copper foil layer in the central region of the package substrate unit; and processing the receiving groove for fixing the electronic component in the central region where the copper foil layer is removed.
  • a second aspect of the present invention provides a package substrate unit, wherein a central portion of the package substrate unit is provided with a receiving groove for fixing the electronic component and insulating the electronic component from the package substrate unit, and the package substrate unit a shielding groove is formed in the periphery, and the shielding groove is filled with a resin, and a metallization layer for electromagnetically shielding the electronic component is processed on a sidewall of the shielding groove, and an opening portion of the shielding groove is processed for sealing The metallization layer of the resin.
  • a third aspect of the present invention provides a substrate assembly, comprising: a package substrate unit as described above, an electronic component buried in a receiving groove formed by the package substrate unit, and respectively press-fitted in the package
  • the upper and lower substrates on both sides of the substrate unit are electrically connected to the circuit patterns on the upper substrate or the lower substrate.
  • the shielding groove is processed on the periphery of the package substrate unit, the sidewall of the shielding groove is metallized, the electronic component is buried in the central region of the package substrate, and the copper foil layer on the surface of the package substrate unit and the sidewall of the shielding groove are utilized.
  • the single tube reliably realizes electromagnetic shielding of the electronic components without additional shielding, does not increase the thickness of the packaging substrate, does not reduce the versatility of the product, and has a reliable structure and reduces failure. Risk, and production costs are also cheaper.
  • FIG. 1 is a flow chart of a method for fabricating a package substrate according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a package substrate unit planned on the board
  • FIG. 3 is a schematic view of a package substrate unit in which a shielded groove has been processed
  • FIG. 4 is a schematic view of a package substrate unit having processed through holes
  • FIG. 5 is a schematic view of a package substrate unit in which a shielded groove and a through hole have been processed
  • FIG. 6 is a cross-sectional view of a packaged substrate unit after metallization
  • FIG. 7 is a schematic view of a package substrate unit filled with a resin in a shield groove
  • Figure 8 is a cross-sectional view of a package substrate unit in which a dry film is provided
  • Figure 9 is a cross-sectional view of a package substrate unit that has been etched
  • Figure 10 is a cross-sectional view of a package substrate unit having a processing receiving groove
  • Figure 11 is a schematic view of a separate package substrate unit
  • Figure 12 is a schematic illustration of a substrate assembly including a package substrate unit.
  • Embodiment 1 provides a method for fabricating a package substrate, which can solve the defects of the existing electromagnetic shielding technology for the circuit board.
  • Embodiments of the present invention also provide corresponding package substrates. The details are described below separately.
  • an embodiment of the present invention provides a method for fabricating a package substrate, including:
  • the processing of the package substrate unit is performed from a larger substrate, such as a double-sided copper clad laminate.
  • a larger substrate such as a double-sided copper clad laminate.
  • a plurality of regularly arranged package substrate units are planned on the larger substrate.
  • the plurality of package substrate units are arranged in an array, horizontally and vertically.
  • the shielding groove 203 may be processed on the periphery of the package substrate unit 202, and specifically, four shielding grooves 203 respectively located around the periphery may be processed. In practical applications, the shielding groove 203 may be processed by a slot drill bit so that the side wall of the shielding groove is wavy.
  • each of the package substrate units 202 is connected at a corner or the like, and can be processed as a whole to improve the processing efficiency. In this case, a plurality of package substrate units are planned on the substrate, and the respective units are adjacent to each other, which can improve the utilization ratio of the substrate and reduce the production cost.
  • the method before the step, further includes the following steps: processing the through hole 204 in the top corner portion of each of the package substrate units 202.
  • the through holes 204 are respectively processed at the four corner portions. , As shown in Figure 4.
  • These processed vias 204 can be used later as vias, alignment holes or tool holes between the layers.
  • the method of machining the through holes 204 may be a mechanical drilling process.
  • the through hole 204 may be processed first, and the shielding groove 203 may be processed.
  • the semi-finished product after the two steps are processed is as shown in FIG. 5.
  • the sidewall of the shielding groove is metallized by a metallization process. If the through hole is previously machined, the through hole is also metallized at the same time.
  • a cross-sectional view of a metallized package substrate unit is shown in Fig. 6, and it can be seen that a metallization layer 205 is attached to the sidewall of the shield trench 203.
  • the metallized sidewalls are then used as a shielding layer to provide electromagnetic shielding for the electronic components embedded in the package substrate unit.
  • the metallized sidewalls can also be used for interlayer conduction.
  • the metal layer formed during the metallization of the sidewall is electroplated with the copper foil layer on the surface of the substrate, and the reliability is very good, and no detachment or displacement occurs during use.
  • the shield groove 203 is filled with a resin 210.
  • the filled resin 210 can have a higher bonding force with the shielding groove 203 and is more firm.
  • the resin may be cured by baking, and after curing, the uneven resin may be leveled by using a grinding plate or a brush plate.
  • the opening of the shielding groove is metallized to form a metallization layer connected to the copper foil layer on the surface of the package substrate unit, and the resin 210 is enclosed inside the shielding groove 203, thereby improving reliability.
  • a pattern transfer process is used to open a window in the central portion of the package substrate unit, i.e., the copper foil layer in the central region is removed.
  • the process of etching the copper foil layer includes:
  • a dry film 206 is disposed on the package substrate unit 202 except for the central region, so that the dry film 206 covers the shielding trench 203; and then, a chemical etching process is used.
  • the copper foil layer 207 of the central region is removed.
  • the dry film is removed, and as shown in Fig. 9, the insulating core layer 208 in the central region is exposed.
  • the step of plating the gold may further include: plating nickel or nickel palladium on the uncopied copper foil layer 207 of the package substrate unit 202 to protect the exposed copper.
  • the foil layer provides good solderability.
  • the receiving groove 209 can be processed in the central region by a process such as mechanical milling or laser cutting.
  • the receiving groove 209 penetrates the substrate up and down, and the side wall is made of an insulating material, which can be used for subsequent embedding of electronic components.
  • the processing may be accommodated according to a size slightly smaller than the central region, that is, slightly smaller than the size of the window opening region on the copper foil layer.
  • the groove 209 has a certain size range of the edge of the receiving groove 209, for example, no copper foil layer in the range of 0.5 mm, thereby achieving good insulation performance between the chip and the package substrate unit.
  • the following steps may be further included: cutting along the outer edge of the shielding groove 203 to cut the substrate 201 into a plurality of independent package substrate units 202.
  • the individual package substrate unit 202 after cutting is as shown in FIG.
  • the electronic component can be fixed in the receiving groove. Since the electronic component and the metallized sidewall are separated by the insulating substrate, the insulating property is very reliable, and the electronic component and the copper around the receiving groove can be ensured.
  • the foil layer and the side walls of the shielding groove are completely insulated.
  • the upper and lower sides of the package substrate unit 202 in which the electronic component 301 is embedded can be respectively pressed on both sides, and the upper and lower substrates 302 are respectively processed with circuit patterns, and the electronic component 301 can be electrically connected with the circuit patterns on the upper substrate or the lower substrate, thereby forming a practical application.
  • Substrate assembly
  • the embodiment of the present invention provides a method for fabricating a package substrate by processing a shield groove around a package substrate unit, metallizing a sidewall of the shield trench, embedding an electronic component in a central region of the package substrate, and using the package substrate
  • the copper foil layer on the surface of the unit and the peripheral metallized sidewalls serve as a metal shielding layer.
  • the cartridge can reliably shield the electronic components without adding additional shields, which will not increase the thickness of the package substrate. Reduce product versatility, and reliable structure, reducing the risk of failure.
  • the method of the embodiment of the present invention only needs to use common equipment such as an image transfer device and an electroplating device, and does not need to add special equipment, and has good versatility.
  • Embodiment 2 Embodiment 2
  • an embodiment of the present invention provides a package substrate unit 202 .
  • the central portion of the package substrate unit 202 is provided with a receiving slot 209 for fixing electronic components.
  • the periphery of the package substrate unit 202 is processed with a shielding slot 203 .
  • the shielding groove 203 is filled with a resin 210, and a metallization layer for electromagnetically shielding the electronic component is processed on a sidewall of the shielding groove 203, and an opening portion of the shielding groove 203 is also processed for sealing.
  • the metallization layer of the resin 210 is filled with a resin 210, and a metallization layer for electromagnetically shielding the electronic component is processed on a sidewall of the shielding groove 203, and an opening portion of the shielding groove 203 is also processed for sealing.
  • the metallization layer of the resin 210 is also processed for sealing.
  • the top corner portion of the package substrate unit 202 may be processed with a metallized via 204.
  • the copper foil layer on the sealing substrate unit 202 may be plated with nickel gold or nickel palladium gold.
  • an embodiment of the present invention further provides a substrate assembly, including: a package substrate unit 202 as described above, an electronic component 301 embedded in a receiving slot formed by the package substrate unit 202, and respectively pressed On the upper and lower substrates 302 on both sides of the package substrate unit 202, the electronic component 301 is electrically connected to a circuit pattern on the upper substrate or the lower substrate.
  • the embodiment of the present invention provides a package substrate unit, the periphery of the package substrate unit is processed with a shielding groove, and the shielding groove is filled with a resin, and the sidewall of the shielding groove is metalized, and the central portion of the package substrate can be
  • the embedded electronic components are electromagnetically shielded.
  • the structure of the product is reliable, does not increase the thickness of the package substrate, does not reduce the versatility of the product, and has a low risk of failure.
  • the package substrate unit of the embodiment of the present invention only needs to use common equipment such as an image transfer device and an electroplating device during processing, and does not need to add special equipment, and has good versatility.

Abstract

一种封装基板的制作方法，包括：在基板（201）上的每个封装基板单元（202）的周边加工屏蔽槽（203）；将屏蔽槽（203）的侧壁金属化；在屏蔽槽（203）内填充树脂（210），并在填充后将屏蔽槽（203）的开口金属化；将封装基板单元（202）的中央区域的铜箔层（207）去除；在去除铜箔层的中央区域加工用于固定电子元件（301）的容纳槽（209）。本发明还提供相应的封装基板单元和基板组件。本发明采用在封装基板单元的周边加工屏蔽槽，将屏蔽槽的侧壁金属化，简单可靠地实现了对电子元件进行电磁屏蔽，而不必另外增加屏蔽罩，不会增加封装基板厚度，不会降低产品的通用性，且结构可靠，降低了失效风险，同时成本低廉。

Description

一种封装基板及其制作方法和基板组件
本申请要求于 2013 年 3 月 29 日提交中国专利局、 申请号为 201310108741.7、 发明名称为 "一种封装基板及其制作方法和基板组件" 的中 国专利申请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电路板加工技术领域，具体涉及一种封装基板及其制作方法和 基板组件。
背景技术
现有的埋入式电路板通常采用在电路板上开槽，将电子元件例如芯片等嵌 入所开的槽中并固定等方法制成。该种电路板中埋入的电子元件会受到外界电 磁干扰， 不能工作在最佳状态。现有技术中一般采用在电路板上增加一个屏蔽 罩的方式来避免电磁干扰。 但是， 屏蔽罩会增加电路板的厚度， 降低产品的通 用性， 不利于向小型化发展， 且屏蔽罩不够可靠， 有移位或脱落等失效风险。 发明内容
本发明实施例提供一种封装基板及其制作方法和基板组件，以解决现有技 术中采用屏蔽罩对电路板进行电磁屏蔽带来的缺陷。
本发明第一方面提供一种封装基板的制作方法， 包括： 在基板上的每个封 装基板单元的周边加工屏蔽槽； 将所述屏蔽槽的侧壁金属化； 在所述屏蔽槽内 填充树脂， 并在填充后将所述屏蔽槽的开口金属化； 将所述封装基板单元的中 央区域的铜箔层去除；在去除铜箔层的所述中央区域加工用于固定电子元件的 容纳槽。
本发明第二方面提供一种封装基板单元，所述封装基板单元的中央区域开 设有用于固定电子元件， 并使所述电子元件与所述封装基板单元绝缘的容纳 槽， 所述封装基板单元的周边加工有屏蔽槽且所述屏蔽槽被树脂填充， 所述屏 蔽槽的侧壁上加工有用于对所述电子元件进行电磁屏蔽的金属化层，所述屏蔽 槽的开口部位加工有用于封闭所述树脂的金属化层。
本发明第三方面提供一种基板组件， 包括： 如上文所述的封装基板单元， 埋入所述封装基板单元开设的容纳槽中的电子元件，以及分別压合在所述封装 基板单元两面的上、 下基板， 所述电子元件与所述上基板或下基板上的电路图 形电连接。
本发明实施例采用在封装基板单元的周边加工屏蔽槽，将屏蔽槽的侧壁金 属化，在封装基板的中央区域埋入电子元件， 利用封装基板单元表面的铜箔层 和屏蔽槽的侧壁作为金属屏蔽层的技术方案，筒单可靠的实现了对电子元件进 行电磁屏蔽， 而不必另外增加屏蔽罩， 不会增加封装基板厚度， 不会降低产品 的通用性， 且结构可靠， 降低了失效风险， 同时制作成本也更低廉。
附图说明
图 1是本发明实施例提供的封装基板的制作方法的流程图；
图 2^ ^板上规划的封装基板单元的示意图；
图 3是已加工屏蔽槽的封装基板单元的示意图；
图 4是已加工通孔的封装基板单元的示意图；
图 5是已加工屏蔽槽和通孔的封装基板单元的示意图；
图 6是金属化后的封装基板单元的截面图；
图 7是屏蔽槽中填充了树脂的封装基板单元的示意图；
图 8是设置了干膜的封装基板单元的截面图；
图 9是已经过蚀刻的封装基板单元的截面图；
图 10是已加工容纳槽的封装基板单元的截面图；
图 11是独立的封装基板单元的示意图；
图 12是包括封装基板单元的基板组件的示意图。
具体实施方式
本发明实施例提供本发明实施例提供一种封装基板的制作方法，可以解决 现有的对电路板电磁屏蔽技术的缺陷。 本发明实施例还提供相应的封装基板。 以下分別进行详细说明。 实施例一、
请参考图 1 , 本发明实施例提供一种封装基板的制作方法， 包括：
101、 在基板上的每个封装基板单元的周边加工屏蔽槽。
本实施例中，对封装基板单元的加工从一张较大的基板， 例如双面覆铜板 开始。该较大的基板上规划出若干个规则排列的封装基板单元。所述的若干个 封装基板单元呈阵列式排列， 横成行， 竖成列。
图 2示出了基板 201上的一个封装基板单元 202, 图中的虚线方框为该封装 基板单元 202的边界。 本步骤中， 如图 3所示， 可以在封装基板单元 202的周边 加工屏蔽槽 203 ,具体可以为加工四个分別位于四周的屏蔽槽 203。实际应用中， 可以采用槽钻钻头加工屏蔽槽 203 , 使所述屏蔽槽的侧壁呈波浪形。 加工完毕 后， 各个封装基板单元 202在顶角等部位连接， 仍然可以作为一个整体进行后 续加工， 以提高加工效率。 该种在基板上规划多个封装基板单元， 各个单元紧 邻， 可以提高基板的板材利用率， 降低生产成本。
一种实施方式中， 在本步骤之前， 还可以包括如下步骤： 在每个封装基板 单元 202的顶角部位加工通孔 204,本实施例中在四个顶角部位都分別加工有通 孔 204, 如图 4所示。 这些加工的通孔 204可以在后续作为层间的导通孔、 对位 孔或工具孔使用。 加工通孔 204的方法可以是机械钻工艺。 本实施方式中， 可 以先加工完通孔 204,再加工屏蔽槽 203 , 这两个步骤加工完毕之后的半成品如 图 5所示。
102、 将所述屏蔽槽的侧壁金属化。
本步骤中采用金属化工艺将所述屏蔽槽的侧壁金属化。如果之前加工了通 孔， 则同时将通孔也金属化。金属化后的一个封装基板单元的截面图如 6所示， 可以看出，屏蔽槽 203的侧壁上附着了一金属化层 205。该被金属化的侧壁后续 将作为屏蔽层， 为封装基板单元内埋入的电子元件提供电磁屏蔽作用， 当然， 该金属化的侧壁也可用于层间导通。本步骤中，侧壁金属化时形成的金属层与 基板表面的铜箔层电镀相连， 可靠性非常好，使用过程中完全不会发生脱离或 者移位现象。
103、在所述屏蔽槽内填充树脂， 并在填充后将所述屏蔽槽的开口金属化。 如图 7所示， 本步骤中在所述屏蔽槽 203内填充树脂 210。 当所述屏蔽槽 203 的侧壁被加工成波浪形时， 填充的树脂 210可以与屏蔽槽 203具有更高的结合 力， 更加牢固。 实际应用中， 可以通过烘烤使所述树脂固化， 固化后还可以采 用磨板或刷板将不平整的树脂铲平。 然后， 需要再次执行沉铜和电镀步骤， 对 屏蔽槽的开口进行金属化， 形成与封装基板单元表面铜箔层相连的金属化层， 将树脂 210封闭在屏蔽槽 203内部， 从而提高可靠性。
104、 将所述封装基板单元的中央区域的铜箔层去除。
本步骤中采用图形转移工艺在所述封装基板单元的中央区域开窗， 即，将 中央区域的铜箔层去除。以便于后续在中央区域加工用于埋入电子元件的容纳 槽。 蚀刻铜箔层的工艺包括：
如图 8所示，在所述封装基板单元 202上除所述中央区域以外的其它部位设 置一层干膜 206, 使所述干膜 206覆盖所述屏蔽槽 203; 然后， 采用化学腐蚀工 艺将所述中央区域的铜箔层 207去除。 蚀刻完毕后， 去除干膜， 如图 9所示， 中 央区域的绝缘芯板层 208已暴露出来。
一种实施方式中， 步骤 104之后， 还可以包括镀金步骤， 具体包括： 在所 述封装基板单元 202的未被去除的铜箔层 207上镀镍金或镍钯金，以便保护棵露 的铜箔层并提供良好的可焊性。
105、 在去除铜箔层的所述中央区域加工容纳槽。
如图 10所示， 中央区域的铜箔层 207被去除后， 可以采用机械铣或者激光 切割等工艺在中央区域加工容纳槽 209。该容纳槽 209上下贯穿基板， 其侧壁为 绝缘材料， 可用于后续嵌入电子元件。 实际应用中， 为了避免后续嵌入的电子 元件接触中央区域周围的铜箔层 207造成短路， 可以按照略小于所述中央区域 的尺寸， 也就是略小于铜箔层上开窗区域的尺寸， 加工容纳槽 209, 使所述容 纳槽 209边缘一定尺寸范围， 例如 0.5mm范围内没有铜箔层， 从而实现芯片与 封装基板单元之间的良好绝缘性能。
本步骤之后， 还可以包括以下步骤： 沿所述屏蔽槽 203的外边缘一定距离 进行切割，将所述基板 201切割成为多个独立的封装基板单元 202。切割后独立 的封装基板单元 202, 如图 11所示。
后续， 可以将电子元件固定在所述容纳槽中， 由于电子元件与金属化侧壁 之间是由绝缘基材隔离， 绝缘性能非常可靠， 可以保证所述电子元件与所述容 纳槽周围的铜箔层和所述屏蔽槽的侧壁完全绝缘。
如图 12所示， 实际应用中，埋入了电子元件 301的封装基板单元 202的上下 两面可以分別压合上、 下基板 302, 上、 下基板 302上分別加工有电路图形， 所 述电子元件 301可以和所述上基板或下基板上的电路图形电连接， 从而构成可 实际应用的基板组件。
以上， 本发明实施例提供了一种封装基板的制作方法， 采用在封装基板单 元的周边加工屏蔽槽，将屏蔽槽的侧壁金属化，在封装基板的中央区域埋入电 子元件，利用封装基板单元表面的铜箔层和周边金属化的侧壁作为金属屏蔽层 的技术方案， 筒单可靠的实现了对电子元件进行电磁屏蔽， 而不必另外增加屏 蔽罩， 不会增加封装基板厚度， 不会降低产品的通用性， 且结构可靠， 降低了 失效风险。 另外， 本发明实施例方法只需要采用图像转移设备、 电镀设备等常 用设备即可， 无需新增特殊的设备， 通用性好。 实施例二、
请参考图 11 , 本发明实施例提供一种封装基板单元 202, 所述封装基板单 元 202的中央区域开设有用于固定电子元件的容纳槽 209 , 所述封装基板单元 202的周边加工有屏蔽槽 203且所述屏蔽槽 203被树脂 210填充， 所述屏蔽槽 203 的侧壁上加工有用于对所述电子元件进行电磁屏蔽的金属化层， 所述屏蔽槽 203的开口部位也加工有用于封闭所述树脂 210的金属化层。
其它实施方式中， 所述封装基板单元 202的顶角部分可以加工有金属化通 孔 204。 所述封转基板单元 202上的铜箔层上可以镀有镍金或镍钯金。
请参考图 12, 本发明实施例还提供一种基板组件， 包括： 如上文所述的封 装基板单元 202, 埋入所述封装基板单元 202开设的容纳槽中的电子元件 301 , 以及分別压合在所述封装基板单元 202两面的上、下基板 302,所述电子元件 301 与所述上基板或下基板上的电路图形电连接。
以上， 本发明实施例提供了一种封装基板单元， 该封装基板单元的周边加 工有屏蔽槽且所述屏蔽槽被树脂填充， 所述屏蔽槽的侧壁被金属化， 可以对封 装基板中央区域埋入的电子元件进行电磁屏蔽， 该产品结构筒单可靠， 不会增 加封装基板厚度， 不会降低产品的通用性， 失效风险低。 另外， 本发明实施例 的封装基板单元在加工时只需要采用图像转移设备、 电镀设备等常用设备即 可， 无需新增特殊的设备， 通用性好。 以上对本发明实施例所提供的封装基板及其制作方法和基板组件进行了 详细介绍， 但以上实施例的说明只是用于帮助理解本发明的方法及其核心思 想， 不应理解为对本发明的限制。本技术领域的技术人员在本发明揭露的技术 范围内， 可轻易想到的变化或替换， 都应涵盖在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种封装基板的制作方法， 其特征在于， 包括：
在基板上的每个封装基板单元的周边加工屏蔽槽；
将所述屏蔽槽的侧壁金属化；
在所述屏蔽槽内填充树脂， 并在填充后将所述屏蔽槽的开口金属化； 将所述封装基板单元的中央区域的铜箔层去除；
在去除铜箔层的所述中央区域加工用于固定电子元件的容纳槽。
2、根据权利要求 1所述的方法， 其特征在于， 所述的在基板上的每个封装 基板单元的周边加工屏蔽槽之前还包括：
在每个封装基板单元的顶角部位加工通孔。
3、根据权利要求 1所述的方法， 其特征在于， 所述的在基板上的每个封装 基板单元的周边加工屏蔽槽包括：
采用槽钻钻头加工屏蔽槽， 使所述屏蔽槽的侧壁呈波浪形。
4、根据权利要求 1所述的方法， 其特征在于， 所述的将所述封装基板单元 的中央区域的铜箔层去除包括：
在所述封装基板单元上除所述中央区域以外的其它部分设置一层干膜，使 所述干膜覆盖所述屏蔽槽；
采用化学腐蚀工艺将所述中央区域的铜箔层去除。
5、根据权利要求 1所述的方法， 其特征在于， 所述的将所述封装基板单元 的中央区域的铜箔层去除之后， 还包括：
在所述封装基板单元的未被去除的铜箔层上镀镍金或镍钯金。
6、根据权利要求 1所述的方法， 其特征在于， 所述的在去除铜箔层的所述 中央区域加工用于固定电子元件的容纳槽包括：
按照略小于所述中央区域的尺寸加工容纳槽，使所述容纳槽边缘一定尺寸 范围内没有铜箔层。
7、根据权利要求 1所述的方法， 其特征在于， 所述的在去除铜箔层的所述 中央区域加工用于固定电子元件的容纳槽之后还包括：
沿所述屏蔽槽的外边缘一定距离，将所述基板切割成为多个独立的封装基 板单元。
8、 一种封装基板单元， 其特征在于： 所述封装基板单元的中央区域开设 有用于固定电子元件， 并使所述电子元件与所述封装基板单元绝缘的容纳槽， 所述封装基板单元的周边加工有屏蔽槽且所述屏蔽槽被树脂填充，所述屏蔽槽 的侧壁上加工有用于对所述电子元件进行电磁屏蔽的金属化层，所述屏蔽槽的 开口部位加工有用于封闭所述树脂的金属化层。
9、 根据权利要求 7所述的封装基板， 其特征在于：
所述封装基板单元的顶角部分加工有金属化通孔。
10、 一种基板组件， 其特征在于， 包括： 如权利要求 8或 9所述的封装基 板单元，埋入所述封装基板单元开设的容纳槽中的电子元件， 以及分別压合在 所述封装基板单元两面的上、 下基板， 所述电子元件与所述上基板或下基板上 的电路图形电连接。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017093281A1 (en) * 2015-11-30 2017-06-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108770210A (zh) * 2018-06-14 2018-11-06 生益电子股份有限公司 一种pcb的制作方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10326993A (ja) * 1997-05-23 1998-12-08 Mitsubishi Electric Corp 電子回路シールド装置
JP2000208947A (ja) * 1999-01-08 2000-07-28 Kyocera Corp 配線基板
JP2001345651A (ja) * 2000-06-01 2001-12-14 Mitsubishi Electric Corp 高周波増幅器モジュール
CN1474642A (zh) * 1997-10-14 2004-02-11 Ҿ쳵���ʽ���� 多层印制线路板及其制造方法,填充通孔的树脂组合物
CN1891023A (zh) * 2003-12-09 2007-01-03 阿斯波康普科技公司 用于绕嵌在电路中的部件构造电磁干扰屏蔽的方法
CN101331814A (zh) * 2005-12-16 2008-12-24 揖斐电株式会社 多层印刷线路板及其制造方法
CN101416567A (zh) * 2006-04-10 2009-04-22 松下电器产业株式会社 中继基板、其制造方法及使用其的立体电路装置
US20120020044A1 (en) * 2010-07-23 2012-01-26 Imbera Electronics Oy Electronic module with vertical connector between conductor patterns
CN102802364A (zh) * 2012-09-11 2012-11-28 岳长来 一种在印刷电路板的导电层中设置金属钯层的方法及其层状结构
US20130087895A1 (en) * 2011-10-05 2013-04-11 Suresh Kumar Upadhyayula Radiation-shielded semiconductor device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10326993A (ja) * 1997-05-23 1998-12-08 Mitsubishi Electric Corp 電子回路シールド装置
CN1474642A (zh) * 1997-10-14 2004-02-11 Ҿ쳵���ʽ���� 多层印制线路板及其制造方法,填充通孔的树脂组合物
JP2000208947A (ja) * 1999-01-08 2000-07-28 Kyocera Corp 配線基板
JP2001345651A (ja) * 2000-06-01 2001-12-14 Mitsubishi Electric Corp 高周波増幅器モジュール
CN1891023A (zh) * 2003-12-09 2007-01-03 阿斯波康普科技公司 用于绕嵌在电路中的部件构造电磁干扰屏蔽的方法
CN101331814A (zh) * 2005-12-16 2008-12-24 揖斐电株式会社 多层印刷线路板及其制造方法
CN101416567A (zh) * 2006-04-10 2009-04-22 松下电器产业株式会社 中继基板、其制造方法及使用其的立体电路装置
US20120020044A1 (en) * 2010-07-23 2012-01-26 Imbera Electronics Oy Electronic module with vertical connector between conductor patterns
US20130087895A1 (en) * 2011-10-05 2013-04-11 Suresh Kumar Upadhyayula Radiation-shielded semiconductor device
CN102802364A (zh) * 2012-09-11 2012-11-28 岳长来 一种在印刷电路板的导电层中设置金属钯层的方法及其层状结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017093281A1 (en) * 2015-11-30 2017-06-08 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage
US10643953B2 (en) 2015-11-30 2020-05-05 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic component packaged in component carrier serving as shielding cage

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