WO2014139291A1 - 多晶硅层的制作方法和多晶硅薄膜晶体管及其制造方法 - Google Patents

多晶硅层的制作方法和多晶硅薄膜晶体管及其制造方法 Download PDF

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WO2014139291A1
WO2014139291A1 PCT/CN2013/086884 CN2013086884W WO2014139291A1 WO 2014139291 A1 WO2014139291 A1 WO 2014139291A1 CN 2013086884 W CN2013086884 W CN 2013086884W WO 2014139291 A1 WO2014139291 A1 WO 2014139291A1
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layer
polysilicon
buffer layer
photoresist
amorphous silicon
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French (fr)
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王祖强
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to US14/348,699 priority Critical patent/US9269820B2/en
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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Definitions

  • Embodiments of the present invention relate to a method of fabricating a polysilicon layer and a polysilicon thin film transistor and a method of fabricating the same. Background technique
  • amorphous silicon amorphous silicon
  • TFTs thin film transistors
  • Poly-Si polysilicon
  • an amorphous silicon layer is usually prepared first; and an amorphous silicon layer is converted into a polycrystalline silicon layer by an excimer laser crystallization (ELA) method; finally, a thin film transistor is formed according to a conventional process.
  • ELA excimer laser crystallization
  • the inventors have found that the prior art has at least the following problems: defects in the formation of polysilicon (such as grain boundary defects, grain inhomogeneities, etc.) are more, and the uniformity of the formed polysilicon layer is poor, resulting in electrical properties of the polysilicon thin film transistor. And the reliability is not good. Summary of the invention
  • Embodiments of the present invention provide a method for fabricating a polysilicon layer, a polysilicon thin film transistor, and a method of fabricating the same, which have a high crystallization rate, uniform crystal grains, and few grain boundary defects, thereby improving electrical performance of the polysilicon thin film transistor. Improve the reliability of polysilicon thin film transistors.
  • the embodiment of the present invention adopts the following technical solutions:
  • a method for fabricating a polysilicon layer comprising:
  • the amorphous silicon layer is converted into a polysilicon layer by a heat treatment process.
  • the plurality of trenches respectively intersect the first direction and the first direction Arranged in the second direction to form a staggered groove pattern.
  • At least one of the seed crystals is disposed on a buffer layer of a region adjacent to the trench.
  • Etching removing the first polysilicon layer and a portion of the buffer layer exposed by the first window region to form the trench
  • the first amorphous silicon layer has a thickness of 10 to 20 nm.
  • the method for fabricating the polysilicon layer further includes:
  • the polysilicon layer directly above the trench is passivated to reduce grain boundary defects.
  • the polysilicon layer directly over the trench is passivated to reduce grain boundary defects, including:
  • the grooves have a width of 5 to 10 meters and the grooves have a pitch of 10 to 20 microns.
  • the heat treatment process is a solid phase crystallization method or an excimer laser crystallization method.
  • the method before the forming the buffer layer, the method further includes:
  • a barrier layer is formed on the substrate.
  • the amorphous silicon layer is formed on the buffer layer and the seed crystal provided with the trench, before the converting the amorphous silicon layer into the polysilicon layer by the heat treatment process, :
  • the amorphous silicon layer is subjected to annealing treatment and surface treatment.
  • Embodiments of the present invention also provide a method of fabricating a polysilicon thin film transistor, which is formed by any of the fabrication methods of the present invention, wherein the polysilicon layer is used to form an active layer of a polysilicon thin film transistor.
  • the embodiment of the invention further provides a polysilicon thin film transistor, wherein the active layer of the polysilicon thin film transistor is formed by forming the polysilicon layer by using the polysilicon layer fabrication method.
  • Embodiments of the present invention also provide an array substrate including the polysilicon thin film transistor. Embodiments of the present invention also provide a display device including the array substrate.
  • Embodiments of the present invention provide a method of fabricating a polysilicon layer, a method of fabricating a polysilicon thin film transistor, a polysilicon thin film transistor formed by the method of the embodiment of the present invention, and an array substrate and a display device provided with the polysilicon thin film transistor,
  • the polysilicon layer is formed by previously providing a trench and a seed crystal in the buffer layer, then forming an amorphous silicon layer on the buffer layer, and converting the amorphous silicon layer into a polysilicon layer by a heat treatment process.
  • the grooves in the buffer layer can provide an extension space for the growth of the amorphous silicon in the molten state and lower the grain boundary height; and the seed crystal can provide the growth of the amorphous silicon.
  • the crystal nucleus is crystallized, thereby accelerating or promoting the growth of the specific crystal form. Therefore, in the fabrication method of the embodiment of the invention, the polycrystalline silicon has a high crystallization rate, uniform crystal grains, and few grain boundary defects, thereby improving the electrical properties of the polysilicon thin film transistor. The performance improves the reliability of the thin film transistor, thereby improving the reliability and display effect of the array substrate and the display device.
  • FIG. 1 is a flow chart of a method for fabricating a polysilicon layer according to an embodiment of the present invention
  • FIGS. 2( a ) to ( e ) are schematic cross-sectional views of respective film layers on the substrate in steps 11 to 15 of the polysilicon layer fabrication process in the embodiment of the present invention
  • FIGS. 5(a) and (b) are schematic cross-sectional views showing respective film layers on the substrate after completing steps 1031 and 1032, respectively;
  • Figure 6 (a) ⁇ (e) are schematic cross-sectional views of the film layers on the substrate after completion of steps 1033-1037;
  • Embodiments of the present invention provide a method for fabricating a polysilicon layer. As shown in FIG. 1 and FIG. 2, the method includes:
  • This step performs a cleaning process on the substrate 100, which may be a glass substrate or other substrate.
  • a barrier layer 110 and a buffer layer 120 are sequentially formed on the substrate 100.
  • the barrier layer 110 is disposed between the substrate 100 and the buffer layer 120, and then blocks when the buffer layer 120 forms a trench.
  • the layer 110 can be used to prevent the substrate 100 from being etched.
  • the buffer layer 120 can also be formed directly on the substrate 100, and the barrier layer 110 is omitted.
  • a plurality of trenches 121 are disposed in the buffer layer 120 by a patterning process, and seed crystals 132 are formed on the buffer layer;
  • the buffer layer 120 is provided with a plurality of trenches 121, which are used when the amorphous silicon is melted and recrystallized.
  • the growth of amorphous silicon in the molten state provides an extension space to lower the grain boundary height; and the seed crystal 132 is disposed on the surface of the buffer layer 120 to provide a crystal nucleus for the growth of the amorphous silicon, thereby accelerating or promoting the growth of the specific crystal form.
  • the plurality of trenches 121 of the present embodiment are respectively arranged in a first direction (lateral direction) and a second direction (longitudinal direction) perpendicular to the first direction to form a crisscross groove pattern.
  • at least one seed crystal 132 is disposed on the buffer layer of the region surrounded by the adjacent trenches 121.
  • two longitudinally adjacent trenches and two laterally adjacent trenches enclose a lattice region 20, and a seed crystal 132 is disposed on the buffer layer in each of the lattice regions 20. .
  • the trench has a width d of 5 to 10 micrometers, and a pitch L of the trenches is 10 to 20 micrometers.
  • the step 13 may provide a plurality of trenches in the buffer layer 120 by a patterning process, and form a seed crystal 132 on the surface of the buffer layer 120.
  • the method may include:
  • the barrier layer 110, the buffer layer 120, and the first amorphous silicon layer 130 may be continuously deposited on the substrate 100 by a plasma enhanced chemical vapor deposition method (PECVD).
  • PECVD plasma enhanced chemical vapor deposition method
  • the first amorphous silicon layer 130 has a thickness of 10-20 nm.
  • the first amorphous silicon layer 130 is converted into the first polysilicon layer 131; this step can use the existing low temperature poly-Silicon (LTPS) technology, An amorphous silicon layer 130 is annealed and crystallized.
  • LTPS low temperature poly-Silicon
  • An amorphous silicon layer 130 is annealed and crystallized.
  • excimer laser crystallization (ELA) is preferably used for crystallization, and of course, solid phase crystallization may be selected.
  • the multi-step exposure described in this step refers to exposure using a multi-tone mask (MTM, Multi Tone Mask) after coating the photoresist, and the intensity of light transmitted through each part of the multi-tone mask is different.
  • MTM Multi Tone Mask
  • the corresponding portions of the photoresist may have less exposure intensity, and after development, a photoresist pattern having different thicknesses of the photoresist may be obtained.
  • etching ie, the first etching
  • the photoresist is etched (Ash) by using a plasma (Plasma), and the photoresist of the first thickness of the photoresist (B region) is removed, and the second thickness corresponding region (B region) The photoresist will also become thinner.
  • etching ie, a second etching
  • the first polysilicon layer 131 of the corresponding region (C region) of the first thickness photoresist is removed, and the polysilicon layer is retained only in the photoresist capping region (B region).
  • the seed layer 132 is disposed on the buffer layer 120.
  • the grooves 121 and the seed crystals 132 are distributed on the buffer layer 120 as shown in FIG. 3, and the grooves 121 are criss-crossed and surrounded.
  • a plurality of lattice regions 20 are provided with a seed crystal 132 on the buffer layer in each of the lattice regions 20, and preferably, the seed crystal 132 is disposed at a central position of the lattice region 20.
  • an amorphous silicon layer 140 is formed;
  • the amorphous silicon layer 140 is converted into the polysilicon layer 141 by a heat treatment process.
  • Step 14 forms an amorphous silicon layer 140 on the buffer layer 120 and the seed crystal 132, and forms a second polysilicon layer 141 by a heat treatment process, as shown in FIG. 2(e).
  • Corresponding to the buffer layer trench 121 is an amorphous silicon recessed strip 122.
  • the polycrystalline silicon seed crystal ie, the seed crystal 132
  • the trench 121 of the buffer layer acts as a buffer during crystallization, which provides space for the polysilicon to provide extension during the formation process, effectively reduces grain boundary defects, reduces the roughness of the polysilicon surface, and improves the uniformity thereof. Sex.
  • the atomic force microscopy analysis of the surface of the polycrystalline silicon produced by the conventional method (a) and the method (b) of the embodiment of the present invention is clearly shown: the surface of the polycrystalline silicon layer produced by the method (b) of the embodiment of the present invention Roughness and grain uniformity are significantly improved.
  • the manufacturing method of the polysilicon layer in this embodiment further includes: 16. Passivation of the polysilicon layer 120 directly above the trenches 121 to reduce grain boundary defects. Specifically, as shown in FIG. 8, this step includes:
  • Steps 161 to 163 apply a photoresist 150 on the polysilicon layer 120, perform a stripe patterning process, form a second window region corresponding to the buffer layer trench 121, and then perform ion implantation to form a grain boundary passivation region 123. As shown in FIG. 8, the grain boundary passivation region 123 is formed right above the buffer layer trench 121.
  • a grain boundary is formed at a corresponding position of the trench 121 of the buffer layer.
  • the grain boundary may be directionally passivated, and the passivation region 123 is formed by ion implantation to be controlled. Reducing the adverse effects of weakening grain boundary defects on the electrical performance of thin film transistors.
  • the embodiment of the present invention further provides a method for fabricating a polysilicon thin film transistor, which is different from the conventional polysilicon thin film transistor manufacturing process in that a polysilicon layer is formed on the front end, and a polysilicon layer is formed by using any of the fabrication methods described in this embodiment. An active layer of a polysilicon thin film transistor is formed.
  • a seed crystal, a buffer layer trench, and a grain boundary passivation region are introduced in the process of forming polysilicon at the front end, and the process of forming a thin film transistor at the rear end is the same, and details are not described herein again.
  • embodiments of the present invention can be used to fabricate top gate (or bottom gate) type polysilicon thin film transistors.
  • the conventional excimer laser crystallization technology forms a grain size uneven, the polycrystalline silicon film has poor Roughness, the grain boundary defect density is high, and the electrical performance and reliability of the thin film transistor are poor, and the embodiment of the present invention is carried out. Improvement, introduction of seed crystal, buffer layer trench and grain boundary passivation region, improve grain uniformity and crystallization rate, reduce grain boundary defects, and improve the electrical properties of thin film transistors.
  • the embodiment of the present invention further provides a polysilicon thin film transistor, wherein the polysilicon thin film transistor preparation process comprises forming a polysilicon layer by using the polysilicon layer fabrication method of the embodiment, and the polysilicon layer is used to form an active layer of the polysilicon thin film transistor.
  • an embodiment of the present invention further provides an array substrate including the polysilicon film Transistor.
  • an embodiment of the present invention further provides a display device including the array substrate.
  • a display device including the array substrate.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

一种多晶硅层的制作方法和多晶硅薄膜晶体管的制造方法。该多晶硅层的制作方法，包括：提供一基底（100）；在所述基底（100）上依次形成阻挡层（110）和缓冲层（120）；通过构图工艺在所述缓冲层（120）中设置多个沟槽（121），并在所述缓冲层（120）之上形成籽晶（132）；在设置有沟槽（121）的所述缓冲层（120）及所述籽晶上，形成非晶硅层（140）；采用热处理工艺将所述非晶硅层（140）转化为多晶硅层。

Description

多晶硅层的制作方法和多晶硅薄膜晶体管及其制造方法 技术领域
本发明的实施例涉及一种多晶硅层的制作方法和多晶硅薄膜晶体管及其 制造方法。 背景技术
现有显示器多基于非晶硅（ a-si ) ,即显示面板上的薄膜晶体管（ Thin Film Transistor , TFT ) 多采用的是非晶硅半导体材料， 但相比之下， 多晶硅 ( Poly-Si )具有更高的电子迁移率，被认为是比非晶硅更佳的 TFT制作材料。
目前， 制备多晶硅 TFT时， 通常先制备一层非晶硅层； 再采用准分子激 光晶化（ELA )方法， 将非晶硅层转化为多晶硅层； 最后再按常规流程形成 薄膜晶体管。 发明人发现现有方法至少存在如下问题： 在多晶硅形成过程中 产生的缺陷 （诸如晶界缺陷、 晶粒不均匀等）较多， 形成的多晶硅层均匀性 较差， 导致多晶硅薄膜晶体管的电学性能及可靠性欠佳。 发明内容
本发明的实施例提供一种多晶硅层的制作方法和多晶硅薄膜晶体管及其 制造方法， 形成的多晶硅层晶化率高、 晶粒均匀、 晶界缺陷少， 从而可改善 多晶硅薄膜晶体管的电学性能， 提高多晶硅薄膜晶体管的可靠性。
为解决上述技术问题， 本发明的实施例采用如下技术方案：
一种多晶硅层的制作方法， 包括：
提供一基底；
在基底上形成緩沖层；
通过构图工艺在所述緩沖层中设置多个沟槽， 并在所述緩沖层之上形成 軒晶；
在设置有沟槽的所述緩沖层及所述籽晶上， 形成非晶硅层；
采用热处理工艺将所述非晶硅层转化为多晶硅层。
在一个示例中， 所述多个沟槽分别沿第一方向和与所述第一方向交叉的 第二方向排列， 形成交错设置的沟槽图案。
在一个示例中， 相邻所述沟槽所围区域的緩沖层上， 设置有至少一块所 述籽晶。
在一个示例中， 所述通过构图工艺在所述緩沖层中设置多个沟槽， 并在 所述緩沖层之上形成籽晶， 包括：
在所述緩沖层上形成第一非晶硅层；
将所述第一非晶硅层转化为第一多晶硅层；
在所述第一多晶硅层上涂覆光刻胶， 经过多阶或半色调曝光、 显影后， 在后续形成所述沟槽的预设位置形成光刻胶完全剥离的第一窗口区域， 在后 续形成所述籽晶的预设位置形成第二厚度的光刻胶， 其余区域形成第一厚度 的光刻胶， 且所述第二厚度大于所述第一厚度；
进行刻蚀， 去除所述第一窗口区域露出的第一多晶硅层及部分緩沖层， 形成所述沟槽；
进行灰化处理， 去除第一厚度的光刻胶；
进行刻蚀， 去除露出的第一多晶硅层；
进行灰化处理， 去除第二厚度对应区域剩余的光刻胶， 形成籽晶。
在一个示例中， 所述第一非晶硅层的厚度为 10~20nm。
在一个示例中， 所述多晶硅层的制作方法， 还包括：
对所述沟槽正上方的多晶硅层进行钝化， 以减少晶界缺陷。
在一个示例中， 对所述沟槽正上方的多晶硅层进行钝化， 以减少晶界缺 陷， 包括：
在所述多晶硅层上涂覆光刻胶， 经过曝光、 显影后， 在所述沟槽对应位 置形成光刻胶完全剥离的第二窗口区域；
进行离子注入， 对所述第二窗口区域露出的所述多晶硅层进行钝化； 去除剩余的光刻胶。
在一个示例中， 所述沟槽的宽度为 5~10 米， 所述沟槽的间距为 10~20 微米。
在一个示例中， 所述热处理工艺为固相结晶法或者准分子激光晶化法。 在一个示例中， 在所述形成緩沖层之前， 还包括：
在所述基底上形成阻挡层。 在一个示例中， 在设置有沟槽的所述緩沖层及所述籽晶上， 形成非晶硅 层之后， 在所述采用热处理工艺将所述非晶硅层转化为多晶硅层之前， 还包 括：
对所述非晶硅层进行退火处理和表面处理。
本发明实施例还提供一种多晶硅薄膜晶体管的制造方法， 采用本发明所 述的任一制作方法形成多晶硅层， 所述多晶硅层用以形成多晶硅薄膜晶体管 的有源层。
本发明实施例还提供一种多晶硅薄膜晶体管， 所述多晶硅薄膜晶体管的 有源层采用所述多晶硅层制作方法形成多晶硅层形成。
本发明实施例还提供一种阵列基板， 包括所述的多晶硅薄膜晶体管。 本发明实施例还提供一种显示装置， 包括所述的阵列基板。
本发明的实施例提供一种多晶硅层的制作方法， 多晶硅薄膜晶体管的制 造方法， 本发明实施例的方法形成的多晶硅薄膜晶体管， 以及设置有所述多 晶硅薄膜晶体管的阵列基板和显示装置， 所述多晶硅层的制作方法预先在緩 沖层设置沟槽和籽晶， 然后在緩沖层上形成非晶硅层， 采用热处理工艺使非 晶硅层转化为多晶硅层。 当非晶硅在热处理工艺作用下熔融再结晶时， 緩沖 层中的沟槽可为熔融状态下非晶硅的生长提供延伸空间， 降低晶界高度； 而 籽晶可为非晶硅的生长提供结晶晶核， 从而加快或促进特定晶型的生长， 因 此， 本发明实施例所述制作方法， 形成的多晶硅晶化率高、 晶粒均匀、 晶界 缺陷少， 从而可改善多晶硅薄膜晶体管的电学性能， 提高薄膜晶体管的可靠 性， 进而提高阵列基板和显示装置的可靠性和显示效果。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例中多晶硅层的制作方法流程图；
图 2 ( a ) ~ ( e )分别为本发明实施例多晶硅层制作过程步骤 11~15中基 底上各膜层的截面示意图；
图 3为本发明实施例中设置有沟槽的緩沖层及其上籽晶的正面俯视图； 图 4为本发明实施例步骤 103形成緩沖层沟槽及籽晶的流程图； 图 5 (a)和（b)分别为完成步骤 1031和 1032后基底上各膜层的截面 示意图；
图 6 (a) ~ (e)分别为完成步骤 1033-1037后基底上各膜层的截面示意 图；
图 7 (a)和（b)分别为传统方法（a)与本发明实施例方法 (b)制造的多 晶硅表面原子力显微镜分析图；
图 8为步骤 106对多晶硅层进行界面钝化的示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例
本发明实施例提供一种多晶硅层的制作方法， 如图 1和图 2所示， 该方 法包括：
11、 提供一基底 100;
本步骤对基底 100进行清洗处理， 基底 100可以是玻璃基板或者其它基 板。
12、 如图 2 (b )所示， 在基底 100上依次形成阻挡层 110和緩沖层 120; 阻挡层 110设置在基底 100和緩沖层 120之间， 后续在緩沖层 120形成 沟槽时， 阻挡层 110可用于避免基底 100受到刻蚀， 具体实施时， 亦可直接 在基底 100上形成緩沖层 120, 省略阻挡层 110。
可选地， 本步骤在基底 100上用等离子体增强化学气相沉积（PECVD) 方法， 连续沉积阻挡层 110和緩沖层 120。
13、 如图 2 (c)所示， 通过构图工艺在緩沖层 120中设置多个沟槽 121, 并在緩沖层之上形成籽晶 132;
本步骤緩沖层 120设置有多个沟槽 121, 在非晶硅熔融再结晶时用以为 熔融状态下非晶硅的生长提供延伸空间， 降低晶界高度； 同时在緩沖层 120 表面布设籽晶 132, 用以为非晶硅的生长提供结晶晶核， 从而加快或促进特 定晶型的生长。
如何在緩沖层 120中设置沟槽 121 , 以及所述沟槽 121如何排列， 沟槽 121的宽度 d、 间距 L的具体取值等， 可以在具体实施时的根据实际情况进 行选择， 本实施例仅举出一种优选的实施方式作为范例， 具体如下所述。
优选地，如图 3所示，本实施例所述的多个沟槽 121分别沿第一方向（横 向）和与第一方向垂直的第二方向（纵向）排列， 形成纵横交错的沟槽图案。 进一步优选地，相邻沟槽 121所围区域的緩沖层上,设置有至少一个籽晶 132。 具体而言， 一种优选的实施方式中， 两个纵向相邻沟槽和两个横向相邻沟槽 围城一个格子区域 20,每一格子区域 20内的緩沖层上均设置有一个籽晶 132。
可选地， 所述沟槽的宽度 d为 5~10微米， 所述沟槽的间距 L为 10~20 微米。
具体而言，步骤 13可通过构图工艺在緩沖层 120中设置多个沟槽，并在 緩沖层 120表面形成籽晶 132, 如图 4所示， 具体可包括：
131、 在緩沖层 120上形成第一非晶硅层 130;
具体实施时， 如图 5 ( a )所示， 可在基底 100上用等离子体增强化学气 相沉积方法（PECVD ) , 连续沉积阻挡层 110、 緩沖层 120以及第一非晶硅 层 130。 其中， 可选地， 第一非晶硅层 130的厚度为 10~20nm。
132、 如图 5 ( b )所示， 将第一非晶硅层 130转化为第一多晶硅层 131; 本步骤可采用现有低温多晶硅（ Low Temperature Poly-Silicon , LTPS ) 技术， 对第一非晶硅层 130进行退火、 晶化。 其中， 晶化时优先选择准分子 激光晶化法（ELA )进行晶化， 当然也可选择固相结晶法。
以下步骤（133~137 )参照图 6 ( a ) ~(e)所示。
133、 在第一多晶硅层 131上涂覆光刻胶 1311 , 经过多阶曝光、 显影后， 在后续形成沟槽的预设位置形成光刻胶完全剥离的第一窗口区域（ A区域）， 在后续形成籽晶的预设位置（B区域）形成第二厚度的光刻胶， 其余区域（C 区域）形成第一厚度的光刻胶， 且所述第二厚度大于所述第一厚度；
本步骤所述的多阶调曝光，指涂覆光刻胶后，利用多阶调掩模板（MTM, Multi Tone Mask )进行曝光， 由于多阶调掩模板各个部分透过的光强不同， 会导致光刻胶相应的各个部分曝光强度也不多， 再经过显影， 可得到光刻胶 厚度不一的光刻胶图样。
134、 进行刻蚀（即第一次刻蚀）， 去除第一窗口区域（ A区域）露出的 第一多晶硅层 131及部分緩沖层 120, 形成緩沖层沟槽 121;
135、 进行灰化处理， 去除第一厚度的光刻胶；
可选地， 本步骤利用等离子体（Plasma )对光刻胶进行刻蚀（Ash ) , 将 第一厚度的光刻胶 (B区域)的光刻胶去除， 同时第二厚度对应区域 (B区域)光 刻胶也会变薄。
136、 进行刻蚀（即第二次刻蚀） ， 去除露出的第一多晶硅层 131;
本步骤去除第一厚度光刻胶对应区域（C 区域） 的第一多晶硅层 131 , 只在光刻胶覆盖区域（B区域）保留多晶硅层。
137、 进行灰化处理， 去除第二厚度对应区域（B区域）剩余的光刻胶， 形成籽晶。 此时， 緩沖层 120上布设有籽晶 132, —种优选的实施方式中， 沟槽 121及籽晶 132在緩沖层 120上的分布方式如图 3所示， 沟槽 121纵横 交错， 围成多个格子区域 20, 每一格子区域 20内的緩沖层上均设置有一个 籽晶 132, 且优选地， 籽晶 132布设于格子区域 20的中央位置。
14、 如图 2 ( d )所示， 在设置有沟槽 121的緩沖层 120及籽晶 132上， 形成非晶硅层 140;
15、 如图 2 ( e )所示， 采用热处理工艺将非晶硅层 140转化为多晶硅层 141。
步骤 14在上述緩沖层 120及籽晶 132上形成非晶硅层 140,采用热处理 工艺形成第二多晶硅层 141 , 如图 2 ( e )所示。 与緩沖层沟槽 121对应的是 在非晶硅凹陷带 122, 在晶化过程中， 多晶硅籽晶（即籽晶 132 )起到了诱导 硅原子重新生长的作用 （如图中箭头所示） ， 可以提高晶化效率； 緩沖层的 沟槽 121在晶化时起到緩沖作用， 即为多晶硅在形成过程中提供延展提供空 间， 有效减少了晶界缺陷， 降低多晶硅表面的粗糙度和提高其均匀性。
如图 7所示， 为传统方法（a )与本发明实施例方法 (b)制造的多晶硅表 面的原子力显微镜分析图， 4艮明显： 本发明实施例方法 (b) 制出的多晶硅层 的表面粗糙度和晶粒均匀性明显改善。
进一步地， 本实施例所述多晶硅层的制作方法， 还包括： 16、 对沟槽 121正上方的多晶硅层 120进行钝化， 以减少晶界缺陷。 具体而言， 如图 8所示， 本步骤包括：
161、在多晶硅层 141上涂覆光刻胶 150,经过曝光、显影后，在沟槽 121 对应位置形成光刻胶完全剥离的第二窗口区域（D区域） ；
162、 进行离子注入， 对第二窗口区域（D区域）露出的多晶硅层进行钝 化；
163、 去除剩余的光刻胶。
步骤 161~163在多晶硅层 120上涂覆光刻胶 150, 进行条纹构图工艺， 形成与緩沖层沟槽 121对应的第二窗口区域， 然后进行离子注入， 形成晶界 钝化区 123。 如图 8所示， 所述晶界钝化区 123形成于緩沖层沟槽 121的正 上方。
步骤 105中非晶硅定向诱导晶化后， 在緩沖层的沟槽 121对应位置形成 晶界， 步骤 106中可对该晶界进行定向钝化， 通过离子注入形成钝化区 123 进行调控， 从而减少削弱晶界缺陷对薄膜晶体管电学性能的不良影响。
本发明实施例还提供一种多晶硅薄膜晶体管的制造方法， 与传统多晶硅 薄膜晶体管制造工艺区别在于前端形成多晶硅的工艺， 采用本实施例所述的 任一制作方法形成多晶硅层， 该多晶硅层用以形成多晶硅薄膜晶体管的有源 层。
本发明实施例在前端形成多晶硅的工艺中引入籽晶、 緩沖层沟槽和晶界 钝化区， 后端形成薄膜晶体管的工艺相同， 在此不再赘述。
还需要指出， 本发明实施例可用于制造顶栅（或底栅）型多晶硅薄膜晶 体管
传统的准分子激光晶化技术形成的晶粒尺寸不均匀， 多晶硅薄膜平整度 ( Roughness )较差， 晶界缺陷密度较高， 薄膜晶体管的电学性能及可靠性欠 佳， 本发明实施例进行了改进， 引入籽晶、 緩沖层沟槽和晶界钝化区， 提高 了晶粒均匀性和晶化率、 减少了晶界缺陷， 改善了薄膜晶体管的电学性能。
本发明实施例还提供一种多晶硅薄膜晶体管， 所述多晶硅薄膜晶体管制 备过程包括采用本实施例所述多晶硅层制作方法形成多晶硅层， 所述多晶硅 层用以形成多晶硅薄膜晶体管的有源层。
进一步地， 本发明实施例还提供一种阵列基板， 包括所述的多晶硅薄膜 晶体管。
更进一步地，本发明实施例还提供一种显示装置， 包括所述的阵列基板。 虽然本发明实施例中以 LTPS背板中的多晶硅层制备为例， 但应理解， 本发明的应用并不限于此， 本发明还适用于所有需要多晶硅膜层的场景。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种多晶硅层的制作方法， 包括：
提供一基底；
在所述基底上形成緩沖层；
通过构图工艺在所述緩沖层中设置多个沟槽， 并在所述緩沖层之上形成 軒晶；
在设置有沟槽的所述緩沖层及所述籽晶上， 形成非晶硅层；
采用热处理工艺将所述非晶硅层转化为多晶硅层。
2、 根据权利要求 1所述的制作方法， 其中，
所述多个沟槽分别沿第一方向和与所述第一方向交叉的第二方向排列， 形成交错设置的沟槽图案。
3、 根据权利要求 1或 2所述的制作方法， 其中，
相邻所述沟槽所围区域的緩沖层上， 设置有至少一块所述籽晶。
4、 根据权利要求 1-3中任一项所述的制作方法， 其中， 所述通过构图工 艺在所述緩沖层中设置多个沟槽， 并在所述緩沖层之上形成籽晶， 包括： 在所述緩沖层上形成第一非晶硅层；
将所述第一非晶硅层转化为第一多晶硅层；
在所述第一多晶硅层上涂覆光刻胶， 经过多阶或半色调曝光、 显影后， 在后续形成所述沟槽的预设位置形成光刻胶完全剥离的第一窗口区域， 在后 续形成所述籽晶颗粒籽晶的预设位置形成第二厚度的光刻胶， 其余区域形成 第一厚度的光刻胶， 且所述第二厚度大于所述第一厚度；
进行刻蚀， 去除所述第一窗口区域露出的第一多晶硅层及部分緩沖层， 形成所述沟槽；
进行灰化处理， 去除第一厚度的光刻胶；
进行刻蚀， 去除露出的第一多晶硅层；
进行灰化处理， 去除剩余的第二厚度的光刻胶， 形成籽晶。
5、 根据权利要求 4所述的制作方法， 其中，
所述第一非晶硅层的厚度为 10~20nm。
6、 根据权利要求 1-5中任一项所述的制作方法， 还包括： 对所述沟槽正上方的多晶硅层进行钝化， 以减少晶界缺陷。
7、根据权利要求 6所述的方法， 其中， 对所述沟槽正上方的多晶硅层进 行钝化， 以减少晶界缺陷， 包括：
在所述多晶硅层上涂覆光刻胶， 经过曝光、 显影后， 在所述沟槽对应位 置形成光刻胶完全剥离的第二窗口区域；
进行离子注入， 对所述第二窗口区域露出的所述多晶硅层进行钝化； 去除剩余的光刻胶。
8、 根据权利要求 1-7中任一项所述的制作方法， 其中，
所述沟槽的宽度为 5~10微米，
所述沟槽的间距为 10~20微米。
9、 根据权利要求 1-8中任一项所述的制作方法， 其中，
所述热处理工艺为固相结晶法或者准分子激光晶化法。
10、 根据权利要求 1-9中任一项所述的制作方法， 其中， 所述形成緩沖 层之前， 还包括：
在所述基底上形成阻挡层。
11、 根据权利要求 1所述的制作方法， 其中， 在设置有沟槽的所述緩沖 层及所述籽晶上， 形成非晶硅层之后， 在所述采用热处理工艺将所述非晶硅 层转化为多晶硅层之前， 所述方法还包括：
对所述非晶硅层进行退火处理和表面处理。
12、 一种多晶硅薄膜晶体管的制作方法， 包括： 形成多晶硅层， 该多晶 硅层用于形成多晶硅薄膜晶体管的有源层， 其中， 所述多晶硅层采用权利要 求 1-11中任一项所述的制作方法形成。
13、 一种多晶硅薄膜晶体管， 其中， 所述多晶硅薄膜晶体管的有源层采 用权利要求 1所述的制作方法形成的多晶硅层形成。
14、 一种阵列基板， 包括权利要求 13所述的多晶硅薄膜晶体管。
15、 一种显示装置， 包括权利要求 14所述的阵列基板。
PCT/CN2013/086884 2013-03-11 2013-11-11 多晶硅层的制作方法和多晶硅薄膜晶体管及其制造方法 Ceased WO2014139291A1 (zh)

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