WO2014133293A1 - Finfet utilisant du ge et/ou un semi-conducteur composé du groupe iii-v et procédé de fabrication associé - Google Patents

Finfet utilisant du ge et/ou un semi-conducteur composé du groupe iii-v et procédé de fabrication associé Download PDF

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Publication number
WO2014133293A1
WO2014133293A1 PCT/KR2014/001487 KR2014001487W WO2014133293A1 WO 2014133293 A1 WO2014133293 A1 WO 2014133293A1 KR 2014001487 W KR2014001487 W KR 2014001487W WO 2014133293 A1 WO2014133293 A1 WO 2014133293A1
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WO
WIPO (PCT)
Prior art keywords
layer
compound semiconductor
semiconductor layer
group iii
substrate
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PCT/KR2014/001487
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English (en)
Korean (ko)
Inventor
고대홍
김병주
Original Assignee
연세대학교 산학협력단
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Publication of WO2014133293A1 publication Critical patent/WO2014133293A1/fr

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present invention relates to FinFET (Fin Field Effect Transistor) using Ge (germanium) or group III-V compound semiconductor and a method of manufacturing the same.
  • CMOS processes have been reported (eg, MM Heyns et al ., IEDM Tech. Dig. , P. 12.1.1 (2011)). This makes it possible to implement blocks on the same platform that use logic, high-frequency devices, input / output circuitry, etc. by using Si substrates.
  • the present invention is to solve the problems in the prior art, a three-dimensional FinFET structure made of a Ge or group III-V compound semiconductor of a new structure having a fast mobility and at the same time have the advantages of FinFET and a method of manufacturing the same It aims to provide.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un dispositif de FinFET tridimensionnel, qui comprend les étapes consistant à : (a) fournir un substrat ; (b) former, sur le substrat, une couche composite de film sacrificiel constituée de multiples couches de film sacrificiel au moyen de plusieurs types de matières, chaque matière formant les couches de film sacrificiel étant constituée de substances qui ont des facteurs de morsure différents et des réactions différentes à un agent de gravure ; (c) former une structure de tranchée par modelage de la couche composite de film sacrificiel ; (d) former une couche de canal actif en faisant croître du Ge et/ou des semi-conducteurs composés du groupe III-V à l'intérieur de la structure de la tranchée ; (e) mettre à nu une partie de la couche de canal actif en effectuant une attaque chimique sélective et en enlevant la couche de film sacrificiel du dessus de la couche composite de film sacrificiel ; (f) former séquentiellement un film diélectrique de porte et une porte métallique afin d'entourer la couche de canal actif à découvert ; (g) former une source et un drain en n'attaquant qu'une zone spécifique de la porte métallique ; et (h) former, sur les zones de source et de drain, un film de Ge et un film du groupe III-V comprenant des impuretés de type p et de type n.
PCT/KR2014/001487 2013-02-26 2014-02-25 Finfet utilisant du ge et/ou un semi-conducteur composé du groupe iii-v et procédé de fabrication associé WO2014133293A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020130020219A KR101401274B1 (ko) 2013-02-26 2013-02-26 Ge 및/또는 III-V족 화합물 반도체를 이용한 FinFET 및 그 제조방법
KR10-2013-0020219 2013-02-26

Publications (1)

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WO2014133293A1 true WO2014133293A1 (fr) 2014-09-04

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016043770A1 (fr) * 2014-09-19 2016-03-24 Intel Corporation Appareil et procédés permettant de créer un tampon pour réduire une fuite dans des transistors micro-électroniques
US9385198B2 (en) 2013-03-12 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for semiconductor devices and methods of forming the same
US9412871B2 (en) 2013-03-08 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with channel backside passivation layer device and method
CN107924944A (zh) * 2015-09-11 2018-04-17 英特尔公司 磷化铝铟子鳍状物锗沟道晶体管
EP3238267A4 (fr) * 2014-12-23 2018-09-05 Intel Corporation Région de canal mince sur sous-ailette large
WO2019066772A1 (fr) * 2017-09-26 2019-04-04 Intel Corporation Formation de contacts de source/drain cristallins sur des dispositifs à semi-conducteur
US10290709B2 (en) 2014-09-19 2019-05-14 Intel Corporation Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces
CN113104806A (zh) * 2021-03-11 2021-07-13 中国电子科技集团公司第五十四研究所 一种mems器件复合金属牺牲层的制备方法
US11276755B2 (en) 2016-06-17 2022-03-15 Intel Corporation Field effect transistors with gate electrode self-aligned to semiconductor fin

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3238262A4 (fr) * 2014-12-22 2018-12-19 Intel Corporation Prévention des courants de fuite des sous-canaux
KR102318743B1 (ko) 2014-12-23 2021-10-28 인텔 코포레이션 비평면 반도체 디바이스의 서브핀에 사용하기 위한 iii-v족 반도체 합금 및 그 형성 방법
US10930738B2 (en) 2017-06-29 2021-02-23 Intel Corporation Sub-fin leakage control in semicondcutor devices
KR102104376B1 (ko) * 2018-12-26 2020-04-27 (재)한국나노기술원 도펀트 확산을 이용한 반도체 소자의 제조 방법

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US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
KR20110031072A (ko) * 2009-09-18 2011-03-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 결정 물질의 개선된 제조 및 구조들
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US20120319211A1 (en) * 2011-06-16 2012-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel field effect transistor

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JP2010129974A (ja) 2008-12-01 2010-06-10 Toshiba Corp 相補型半導体装置とその製造方法

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US7799592B2 (en) * 2006-09-27 2010-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-gate field-effect transistors formed by aspect ratio trapping
KR20110031072A (ko) * 2009-09-18 2011-03-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 결정 물질의 개선된 제조 및 구조들
KR20120091993A (ko) * 2010-12-29 2012-08-20 글로벌파운드리즈 싱가포르 피티이. 엘티디. Finfet
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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412871B2 (en) 2013-03-08 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with channel backside passivation layer device and method
US9385198B2 (en) 2013-03-12 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for semiconductor devices and methods of forming the same
US10164024B2 (en) 2013-03-12 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Heterostructures for semiconductor devices and methods of forming the same
US10290709B2 (en) 2014-09-19 2019-05-14 Intel Corporation Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces
US10559683B2 (en) 2014-09-19 2020-02-11 Intel Corporation Apparatus and methods to create a buffer to reduce leakage in microelectronic transistors
WO2016043770A1 (fr) * 2014-09-19 2016-03-24 Intel Corporation Appareil et procédés permettant de créer un tampon pour réduire une fuite dans des transistors micro-électroniques
EP3238267A4 (fr) * 2014-12-23 2018-09-05 Intel Corporation Région de canal mince sur sous-ailette large
CN107924944A (zh) * 2015-09-11 2018-04-17 英特尔公司 磷化铝铟子鳍状物锗沟道晶体管
CN107924944B (zh) * 2015-09-11 2021-03-30 英特尔公司 磷化铝铟子鳍状物锗沟道晶体管
US11476338B2 (en) 2015-09-11 2022-10-18 Intel Corporation Aluminum indium phosphide subfin germanium channel transistors
US11276755B2 (en) 2016-06-17 2022-03-15 Intel Corporation Field effect transistors with gate electrode self-aligned to semiconductor fin
US11996447B2 (en) 2016-06-17 2024-05-28 Intel Corporation Field effect transistors with gate electrode self-aligned to semiconductor fin
WO2019066772A1 (fr) * 2017-09-26 2019-04-04 Intel Corporation Formation de contacts de source/drain cristallins sur des dispositifs à semi-conducteur
US11430787B2 (en) 2017-09-26 2022-08-30 Intel Corporation Forming crystalline source/drain contacts on semiconductor devices
CN113104806A (zh) * 2021-03-11 2021-07-13 中国电子科技集团公司第五十四研究所 一种mems器件复合金属牺牲层的制备方法
CN113104806B (zh) * 2021-03-11 2024-05-03 中国电子科技集团公司第五十四研究所 一种mems器件复合金属牺牲层的制备方法

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