WO2014115578A1 - プリント配線基板、電子機器及び配線接続方法 - Google Patents
プリント配線基板、電子機器及び配線接続方法 Download PDFInfo
- Publication number
- WO2014115578A1 WO2014115578A1 PCT/JP2014/050148 JP2014050148W WO2014115578A1 WO 2014115578 A1 WO2014115578 A1 WO 2014115578A1 JP 2014050148 W JP2014050148 W JP 2014050148W WO 2014115578 A1 WO2014115578 A1 WO 2014115578A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ground
- signal
- hole
- layer
- wiring
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/081—Microstriplines
- H01P3/082—Multilayer dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/026—Coplanar striplines [CPS]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0224—Patterned shielding planes, ground planes or power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0245—Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09718—Clearance holes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
- Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path
Definitions
- the present invention relates to a printed wiring board, an electronic device, and a wiring connection method mainly used for transmission of a high-frequency differential signal.
- wiring layers a printed wiring board in which a plurality of insulating layers and a plurality of conductive layers (wiring layers) are stacked to improve the degree of circuit integration.
- the wiring formed in each wiring layer is usually connected by a hole penetrating all layers of the substrate and a conductor plated on the inner surface (hereinafter referred to as “through hole”).
- Ethernet registered trademark
- differential signals have been used to increase the transmission speed of electrical signals. This is a device for reducing the influence of external noise and maintaining the integrity of the high-frequency electrical signal propagating through the transmission line.
- the electrical signal becomes more susceptible to impedance discontinuities in the transmission line (wiring).
- the electrical signal becomes more susceptible to impedance discontinuities in the transmission line (wiring).
- the through hole formed in the printed wiring board described above penetrates all of the printed wiring board. For this reason, a parasitic stub is formed at a connection point with the signal wiring formed in the wiring layer. It is known that this parasitic stub causes an impedance discontinuity in the transmission line and causes a signal loss or the like.
- 10 Gbase-KR defined in IEEE 802.3ap is Ethernet (registered trademark) via a backplane. In the case of 10 Gbase-KR, it has been found that the loss due to the stub parasitic to the through-hole for mounting the backplane connector is particularly large.
- FIG. 9 is a first diagram showing a structure of a printed wiring board related to the embodiment of the present invention.
- the printed wiring board 2 is configured by stacking a large number of ground layers and wiring layers stacked via an insulating layer.
- the ground layer and the wiring layer are conductor layers.
- the insulating layer is omitted in FIG. 9 for convenience of explanation, actually, an insulating layer made of a dielectric material such as resin exists between the conductor layers.
- the ground layer is provided with a ground plane 202 formed as a conductor pattern.
- the ground plane 202 functions as a ground.
- the wiring layer is provided with a signal wiring 203 that is also formed as a conductor pattern.
- the signal wiring 203 functions as a transmission line that propagates a predetermined electric signal based on the conductor pattern.
- the printed wiring board 2 is provided with grounding through holes 200a to 200c that penetrate the board 2 and are connected to all the ground planes 202 provided in a plurality of ground layers.
- the grounding through holes 200a to 200c are collectively referred to as a grounding through hole 200.
- the printed wiring board 2 is provided with signal through holes 201a to 201c that penetrate through the board 2 and are connected to at least one of the signal wirings 203 provided in the plurality of wiring layers.
- the signal through holes 201a to 201c are collectively referred to as a signal through hole 201.
- the signal through hole 201 functions as a carrier line that is connected to the signal wiring 203 and carries the propagation of an electric signal.
- the signal through-holes 201a and 201b are connected to a differential signal signal wiring for carrying an electrical signal whose phases are reversed with each other. As shown in FIG. 9, the grounding through holes 200a and 200b are juxtaposed so as to form a pair with the signal through holes 201a and 201b, respectively.
- the clearance 204 is formed by cutting out the conductor plane 202 of the ground layer.
- the clearance 204 is a non-conductive pattern for configuring a state in which the ground plane 202 and the signal through hole 201 are physically separated. As shown in FIG. 9, the clearance 204 is formed around the signal through holes 201a and 201b for propagating differential signals. On the other hand, since the ground plane 202 and the grounding through hole 200 are in physical contact with each other, the clearance 204 is not formed around the grounding through hole 200 in all layers.
- FIG. 10 is a second view showing the structure of the printed wiring board 2 related to the embodiment of the present invention.
- 10 is a schematic cross-sectional view of the printed wiring board 2 shown in FIG.
- a corresponding signal pin of an IC Integrated Circuit
- the insulating layer 205 exists between the conductor layers and electrically insulates the conductor layers.
- the signal through holes 201a and 201b penetrate the printed wiring board 2 from the upper surface to the lower surface.
- the signal through holes 201a and 201b are connected to the signal wiring 203 of the first wiring layer from the top in the printed wiring board 2, and are not connected to the wiring layers of the second and lower layers at all. Therefore, the signal through holes 201a and 201b form a “stub St” as shown in FIG.
- the stub St increases the “parasitic capacitance Pc” as shown in FIG.
- the presence of the stub St increases the parasitic capacitance Pc.
- the impedance of the transmission line is locally reduced. This causes an impedance mismatch that is not intended by the designer, leading to a reduction in the quality of the high-frequency signal propagating through the transmission line.
- the back drill method is a method of removing a parasitic stub portion in a through hole by scraping with a drill. By this back drilling method, the parasitic stub can be physically removed.
- Patent Document 1 discloses a method of connecting a ground plane to a grounding through hole that connects the ground planes of the respective ground layers to equalize the potential.
- Patent Document 1 discloses a method of connecting a grounding through hole only to a ground plane of a ground layer adjacent to a wiring layer as one of connection methods.
- the back drill method described above can effectively remove the parasitic stubs in the through holes.
- the back drilling method requires a precise drilling process, which increases the cost of the substrate.
- the ground planes in all the ground layers are formed in the same lattice shape. Further, ground planes other than the ground layer adjacent to the wiring layer are not connected to the ground through hole, but extend to the wall surface of the ground through hole. In such a configuration, the effect of reducing the influence of the parasitic stub due to the fact that the ground plane other than the ground layer adjacent to the wiring layer is not connected to the ground through-hole is limited.
- An example of an object of the present invention is to provide a printed wiring board, an electronic device, and a wiring connection method that can solve the above-described problems.
- a printed wiring board includes a wiring layer, a first ground layer, a second ground layer, a grounding through hole, a signal through hole, a first clearance, and a second clearance.
- the wiring layer has signal wiring.
- the first ground layer has a first ground plane.
- the second ground layer is located between the wiring layer and the first ground layer, and has a second ground plane.
- the grounding through hole penetrates the wiring layer and the first and second grounding layers and is connected to the second grounding plane.
- the signal through hole penetrates the wiring layer and the first and second ground layers and is connected to the signal wiring.
- the first clearance is formed in the first ground layer, is located around the signal through hole and the ground through hole, and the first ground plane is formed as the signal through hole and the ground through. Separate from the hall.
- a second clearance is formed in the second ground layer, is located around the signal through hole, and separates the second ground plane from the signal through hole.
- An electronic apparatus includes the printed wiring board described above.
- a wiring connection method is located between a wiring layer having a signal wiring, a first ground layer having a first ground plane, and the wiring layer and the first ground layer. And a second ground layer having a second ground plane.
- a grounding through hole penetrating the wiring layer and the first and second ground layers is connected to the second ground plane, and the wiring layer and the first and second ground layers are connected.
- a signal through hole penetrating a ground layer is connected to the signal wiring, and the first ground layer is positioned so that a first clearance is located around the signal through hole and the ground through hole.
- the first ground plane is separated from the signal through hole and the ground through hole, and a second clearance is positioned around the signal through hole. Forming in the formation and separating the second ground plane from the signal through-hole.
- impedance discontinuity of the transmission line due to the parasitic stub can be reduced.
- the printed wiring board which enables higher-speed data communication can be provided at low cost.
- FIG. 1 is a first view showing the structure of a printed wiring board according to an embodiment of the present invention.
- the printed wiring board 1 is formed by stacking a large number of ground layers and wiring layers stacked via an insulating layer.
- the ground layer and the wiring layer are conductor layers.
- an insulating layer is omitted for convenience of explanation, but actually, an insulating layer exists between the conductor layers (see FIG. 3).
- the insulating layer is made of a dielectric material such as resin.
- the ground layer has a ground plane 102 formed as a conductor pattern. This ground plane 102 functions as a ground.
- the wiring layer has a signal wiring 103 formed as a conductor pattern.
- the signal wiring 103 functions as a transmission line for propagating a predetermined electric signal by the conductor pattern.
- the printed wiring board 1 has grounding through holes 100a to 100c that penetrate the board 1 and are connected to at least one of the ground planes 102 of the plurality of ground layers.
- the grounding through holes 100a to 100c are collectively referred to as a grounding through hole 100.
- the plurality of wiring layers have signal wirings 103.
- the printed wiring board 1 has signal through holes 101 a to 101 c that penetrate the board 1 and are connected to at least one of the signal wirings 103.
- the signal through holes 101a to 101c transmit differential signals.
- the signal through holes 101a to 101c are collectively referred to as a signal through hole 101.
- the signal through hole 101 is connected to the signal wiring 103 and functions as a carrier line that carries electric signal propagation.
- the signal through holes 101a and 101b are connected to a signal wiring for differential signals that carries electrical signals whose phases are reversed. As shown in FIG. 1, the grounding through hole 100a is juxtaposed so as to form a pair with the signal through hole 101a. The grounding through hole 100b is juxtaposed so as to form a pair with the signal through hole 101b.
- the clearance 104 is formed by cutting out the conductor plane 102 of the ground layer.
- the clearance 104 is a non-conductive pattern for forming a state in which the ground plane 102 and the signal through hole 101 are physically separated.
- the clearance 104 according to the present embodiment is formed around one or both of the signal through hole 101 and the grounding through hole 100.
- the clearance 104 according to the present embodiment separates the signal through hole 101 and the ground plane 102, or separates the ground through hole 100 and the ground plane 102.
- the clearance 104 is formed around the signal through holes 101a and 101b and the ground through holes 100a and 100b.
- the grounding through hole 100 is juxtaposed so as to form a pair with the signal through hole 101.
- the grounding through hole 100a is paired with the signal through hole 101a.
- the grounding through hole 100b is paired with the signal through hole 101b.
- the grounding through holes 100a and 100b are juxtaposed so as to sandwich the signal through holes 101a and 101b.
- the grounding through hole 100b may also serve as a pair with another signal through hole 101c installed therebelow.
- the grounding through hole 100 according to the present embodiment is connected to a ground plane 102 formed in an “adjacent ground layer” adjacent to a specific wiring layer among a plurality of ground layers.
- the grounding through hole 100 according to the present embodiment is separated from the ground plane 102 formed in the ground layer other than the adjacent ground layer by the clearance 104.
- the “adjacent ground layer” refers to a ground layer that exists at a position through only the wiring layer and one insulating layer (that is, “adjacent” to the wiring layer through only one insulating layer).
- FIG. 2A is a top view of the wiring layer A ′ and the ground layer A (adjacent ground layer A) of the printed wiring board 1.
- FIG. 2A shows a state in which the wiring layer A ′ is present on the front side of the paper, and the ground layer A is present from the wiring layer A ′ to the back side of the paper through one insulating layer. That is, the ground layer A is an “adjacent ground layer” that is “adjacent” to the wiring layer A ′.
- a signal wiring 103A is formed in the wiring layer A '.
- a ground plane 102A and a clearance 104A are formed in the ground layer A.
- the grounding through holes 100a and 100b according to the present embodiment are connected to the ground plane 102A of the adjacent ground layer A. That is, the clearance 104A is formed around the signal through hole 101 (101a, 101b), so that the ground plane 102A and the signal through hole 101 are separated. On the other hand, the clearance 104 ⁇ / b> A is not formed around the grounding through hole 100.
- FIG. 2B is a top view of the ground layer B of the printed wiring board 1.
- the ground layer B is not an adjacent ground layer.
- Such a ground layer B other than the adjacent ground layer may be referred to as a non-adjacent ground layer.
- a clearance 104B is formed in the non-adjacent ground layer B.
- the clearance 104B is formed around the signal through hole 101 (101a, 101b) and around the grounding through hole 100 so as to communicate with each other. Therefore, the grounding through hole 100 is separated from the ground plane 102B of the non-adjacent ground layer B by the clearance 104B.
- FIG. 3 is a third view showing the structure of the printed wiring board according to the embodiment of the present invention.
- FIG. 3 is a schematic cross-sectional view of the printed wiring board 1 shown in FIGS. 1, 2A, and 2B.
- a corresponding signal pin of an IC is inserted into each through hole 100a, 100b, 101a, 101b.
- the insulating layer 105 exists between the conductor layers and electrically insulates the conductor layers.
- the signal through holes 101a and 101b penetrate the printed wiring board 1 from the upper surface to the lower surface.
- the signal through holes 101a and 101b are connected to the signal wiring 103A of the first wiring layer (wiring layer A ′) from the top, and are completely connected to the second and lower wiring layers (wiring layer B ′ and the like). Not done. Therefore, the signal through holes 101a and 101b form a stub ST as shown in FIG.
- ground plane 102B In the ground layer B, a ground plane 102B is formed. In the ground layer C, a ground plane 102C is formed. In the ground layer D, a ground plane 102D is formed.
- the ground planes 102A and 102C shown in FIG. 3 are connected to the ground through holes 100a and 100b because the ground layers A and C in which they are formed are adjacent ground layers.
- the ground planes 102B and 102D are not connected to the ground through holes 100a and 100b because the ground layers B and D in which they are formed are not adjacent ground layers.
- the clearance 104B is formed around the grounding through hole 100a and the grounding through hole 100b so as to communicate with each other.
- the distance between the ground plane 102B and the signal through hole 101 is increased (see FIG. 3).
- the parasitic capacitance Pc generated by the stub St and the ground plane 102B shown in FIG. 3 can be reduced. Since the relationship between the ground plane 102D and the clearance 104D is the same, the parasitic capacitance Pc generated by the stub St and the ground plane 102D can be reduced.
- the impedance discontinuity generated in the portion of the stub St is also improved in the transmission line constituted by the signal wiring 103 and the signal through hole 101. .
- the grounding through holes 100a and 100b are connected to the ground planes 102A and 102C (see FIG. 3).
- the grounding through holes 100a and 100b are separated from the ground planes 102B and 102D by clearances 104B and 104D.
- FIG. 4 is a fourth view showing the structure of the printed wiring board according to the embodiment of the present invention.
- the printed wiring board 1 is different from the through hole shown in FIG. 3 in that the grounding through hole 100 c and the signal through hole 101 c are paired, and the grounding through hole 100 d and the signal through hole 101 d. Having a pair.
- the wiring layer B ′ is located between the ground layer B and the ground layer D and has a signal wiring 103B.
- the signal wiring 103B is connected to the signal through holes 101c and 101d.
- the grounding through holes 100c and 100d are connected to the ground planes 102B and 102D formed in the adjacent ground layers B and D adjacent to the wiring layer B ′ (see FIG. 4).
- the grounding through holes 100c and 100d are separated from the ground planes 102A and 102C formed in the non-adjacent ground layers A and C not adjacent to the wiring layer B ′ by the clearances 104A and 104C.
- the clearance 104A is formed around the grounding through hole 100c and around the 100d so as to communicate with each other.
- the distance between the ground plane 102A and the signal through hole 101 is increased (see FIG. 4).
- the parasitic capacitance Pc generated by the stub St and the ground plane 102A shown in FIG. 4 can be reduced. Since the relationship between the ground plane 102C and the clearance 104C is the same, the parasitic capacitance Pc generated by the stub St and the ground plane 102C can be reduced.
- FIG. 5 is a graph showing electrical characteristics of the printed wiring board according to the embodiment of the present invention and the printed wiring board related to the embodiment of the present invention.
- the horizontal axis represents the frequency (Freq [GHz]) of the electric signal
- the vertical axis represents the transmission characteristic (Sdd21 [dB]) of the differential signal propagating through the signal through hole.
- the solid line indicates the electrical characteristics of the printed wiring board 1 shown in FIG.
- a broken line shows the electrical characteristics of the printed wiring 2 shown in FIG.
- the transmission characteristic Sdd21 [dB] shown on the vertical axis is an index indicating that the differential signal is transmitted to the transmission destination without attenuation as the value is closer to 0 (zero). As the value of Sdd21 decreases, the differential signal attenuates, indicating that the transmission characteristics deteriorate.
- the attenuation of the differential signal is significant from the frequency band of 7 GHz or more.
- the differential signal is not attenuated even at 8 GHz. That is, according to the transmission characteristics shown in FIG. 5, the frequency of the differential signal of the printed wiring board 1 can be set higher than that of the printed wiring board 2 by about 1 GHz.
- the parasitic capacitance Pc generated between the stub St portion of the signal through hole 101 (201) and the ground plane 102 (202) is reduced as shown in FIGS. That is, by reducing the parasitic capacitance component “C”, the resonance frequency determined based on the product of the parasitic capacitance component “C” and the parasitic induction component “L” existing in the wiring or the stub St (shown in FIG. 5). The frequency giving the attenuation peak) can be shifted to the high frequency side as a whole.
- FIG. 6 is a diagram showing LSI terminals formed on the printed wiring board according to the embodiment of the present invention.
- the printed wiring board 1 according to the present embodiment includes an LSI (Large Scale Integration) terminal 3 as shown in FIG. 6, for example.
- the LSI terminal 3 is constituted by a large number of through holes corresponding to the signal pins of the LSI to be connected.
- the partial LSI terminal 3a shown in FIG. 6 is an area in which a part of the LSI terminal 3 is enlarged.
- the LSI terminal 3 has a plurality of grounding through holes 100 and a plurality of signal through holes 101.
- the grounding through hole 100a and the signal through hole 101a make a pair
- the grounding through hole 100b and the signal through hole 101b make a pair. Yes.
- FIG. 7 is a diagram showing a layer structure of an LSI terminal according to an embodiment of the present invention.
- the layer structure of each through hole 100, 101 formed in the partial LSI terminal 3a shown in FIG. 6 will be described with reference to FIG.
- the ground layer A and the wiring layer A ′ shown in FIG. 7 will be described (see the upper left of FIG. 7).
- the ground layer A exists on the lower surface (back side of the drawing) of the wiring layer A ′ and is adjacent to the wiring layer A ′.
- the signal through hole 101b is connected to the signal wiring 103A formed in the wiring layer A ′. Therefore, the grounding through hole 100b paired with the signal through hole 101b is connected to the ground plane 102A formed in the ground layer A.
- the clearance 104Ab formed in the ground layer A is formed around the signal through hole 101b but not around the ground through hole 100b (see the upper left in FIG. 7).
- the signal through hole 101a is not connected to the wiring formed in the wiring layer A '. Further, the signal through hole 101a is not connected to the signal wiring (not shown) of the wiring layer adjacent to the lower surface (back side of the paper) of the ground layer A. In this case, the grounding through hole 100a paired with the signal through hole 101a is not connected to the ground plane 102A formed in the ground layer A. That is, the clearance 104Aa formed in the ground layer A is formed around the signal through hole 101a and the ground through hole 100a (see the upper left in FIG. 7).
- the ground layer B shown in FIG. 7 will be described (see the center of FIG. 7).
- the ground layer B does not have the wiring through-hole 101 connected to the signal wiring of the wiring layer adjacent to the upper surface (front side of the paper) and the lower surface (back side of the paper).
- the grounding through holes 100a and 100b paired with the signal through holes 101a and 101b are not connected to the ground plane 102B formed in the ground layer B (see the center of FIG. 7).
- the ground layer C shown in FIG. 7 will be described (see the lower right of FIG. 7).
- the ground layer C exists on the lower surface (back side in the drawing) of the wiring layer C ′ and is adjacent to the wiring layer C ′.
- the signal through hole 101a is connected to the signal wiring 103C formed in the wiring layer C '. Therefore, the grounding through hole 100a paired with the signal through hole 101a is connected to the ground plane 102C formed in the ground layer C.
- the clearance 104Ca formed in the ground layer C is formed around the signal through hole 101a but is not formed around the ground through hole 100a (see the lower right in FIG. 7).
- the signal through hole 101b is not connected to the wiring formed in the wiring layer C '. Further, the signal through hole 101b is not connected to the signal wiring (not shown) of the wiring layer adjacent to the lower surface (back side of the paper) of the ground layer C. In this case, the grounding through hole 100b paired with the signal through hole 101b is not connected to the ground plane 102C formed in the ground layer C. That is, the clearance 104Cb formed in the ground layer C is formed around the signal through hole 101b and the ground through hole 100b (see the lower right in FIG. 7).
- the embodiment of the present invention can be applied by performing the connection as described above.
- FIG. 8 shows a through-hole design for connecting an AC coupling capacitor according to an embodiment of the present invention.
- the left side of FIG. 8 shows a cross-sectional structure of the printed wiring board 1.
- the capacitor 4 is an AC coupling capacitor.
- the capacitor 4 is disposed on the transmission line in order to remove the DC component of the high frequency signal.
- the right side of FIG. 8 shows a top view of each conductor layer constituting the printed wiring board 1.
- the cross section taken along the dotted line XY in the top view corresponds to the cross section shown on the left side of FIG.
- ground layer A In the ground layer A, a ground plate 102A and clearances 104Aa and 104Ab are formed.
- the ground layer A is not adjacent to the wiring layer in the illustrated region. For this reason, the grounding through holes 100a and 100b are not connected to the ground plane 102A (see the upper right in FIG. 8).
- ground layer B In the ground layer B, a ground plate 102B and clearances 104Ba and 104Bb are formed.
- the ground layer B is an adjacent ground layer adjacent to the wiring layer B '.
- the signal wiring 103B formed in the wiring layer B ' is connected to the signal through hole 101a. Therefore, the grounding through hole 100a that forms a pair with the signal through hole 101a is connected to the ground plane 102B of the ground layer B (see the right center in FIG. 8).
- the ground layer D existing on one layer of the wiring layer B ' is also an adjacent ground layer of the wiring layer B'. For this reason, the ground plane 102D is similarly connected to the grounding through hole 100a.
- the signal through hole 101b is not connected to the wiring formed in the wiring layer B '. Therefore, the grounding through hole 100b that forms a pair with the signal through hole 101b is separated from the ground plane 102B of the ground layer B by the clearance 104Bb (see the right center in FIG. 8).
- ground layer C In the ground layer C, a ground plate 102C and clearances 104Ca and 104Cb are formed.
- the ground layer C is an adjacent ground layer adjacent to the wiring layer C ′.
- the signal wiring 103C formed in the wiring layer C ' is connected to the signal through hole 101b. Therefore, the grounding through hole 100b paired with the signal through hole 101b is connected to the ground plane 102C of the ground layer C (see the lower right in FIG. 8).
- the ground layer E existing on one layer of the wiring layer C ′ is also an adjacent ground layer of the wiring layer C ′. For this reason, the ground plane 102E is similarly connected to the grounding through hole 100b.
- the signal through hole 101a is not connected to the wiring formed in the wiring layer C '. Therefore, the grounding through hole 100a that forms a pair with the signal through hole 101a is separated from the ground plane 102C of the ground layer C by the clearance 104Ca (see the lower right in FIG. 8).
- the ground plane 102B connected to the ground through hole 100a paired with the signal through hole 101a connected to the signal wiring 103B on the upper and lower surfaces of the signal wiring 103B. And 102D.
- the ground planes 102C and 102E connected to the grounding through hole 100b paired with the signal through hole 101b connected to the signal wiring 103C exist on the upper and lower surfaces of the signal wiring 103C.
- the grounding through hole 100 is connected to the ground plane 102 formed in the ground layer adjacent to the upper and lower surfaces of the wiring layer on which the signal wiring 103 connected to the signal through hole 101 forming a pair is formed.
- the signal wiring 103 extends while being sandwiched between the ground planes 102 formed in the ground layer adjacent to the upper and lower surfaces thereof.
- the parasitic capacitance Pc generated in the stub St is reduced. For this reason, the grounding through hole 100 is not connected to all the ground planes 102 but is connected only to some of the ground planes 102. In such a case, since the electrical coupling between the ground planes 102 is weakened, the ground potential cannot be maintained as a whole, and as a result, there is a concern that the ground plane 102 cannot shield electromagnetic interference between the signal wirings.
- the grounding through hole 100 is connected to the ground plane 102 adjacent to at least the upper and lower surfaces of the wiring layer.
- a ground potential is effectively applied to the ground plane 102 closest to each signal wiring through the grounding through hole 100. Therefore, the grounding through-hole 100 can sufficiently obtain a shielding effect for each signal wiring 103 with only a minimum connection. Therefore, according to the present embodiment, even if the grounding through hole 100 is not connected to some of the ground planes 102 in order to reduce the parasitic capacitance Pc, the signal wirings 103 do not interfere with each other.
- the present invention can be applied to printed wiring boards, electronic devices, and wiring connection methods.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Waveguides (AREA)
Abstract
Description
以下、上述した寄生スタブについて簡単に説明する。図9に示すようにプリント配線基板2は、絶縁層を介して積層された接地層及び配線層を多数重ねて構成されている。接地層及び配線層は、導体層である。図9では説明の便宜上絶縁層を省略して図示しているが、実際には各導体層の間には樹脂などの誘電体で構成される絶縁層が存在している。
この接地プレーン202はグラウンドとして機能する。上記配線層には、同じく導体パターンとして形成された信号配線203が設けられている。この信号配線203は、その導体パターンに基づき、所定の電気信号を伝搬する伝送線路として機能する。
図10は、図9に示したプリント配線基板2の断面模式図を示した図である。図10に示す通り、各スルーホール201、202にはIC(Integrated Circuit)の対応する信号ピンが挿入される。絶縁層205は、各導体層の間に存在し、導体層同士を電気的に絶縁する。
図1は本発明の実施形態によるプリント配線基板の構造を示す第一の図である。
本実施形態による接地用スルーホール100は、複数の接地層のうち特定の配線層に隣接する「隣接接地層」に形成される接地プレーン102と接続する。また、本実施形態による接地用スルーホール100は、隣接接地層以外の接地層に形成される接地プレーン102からクリアランス104によって分離される。「隣接接地層」とは、配線層と絶縁層一層のみを介した位置に存在する(すなわち、絶縁層一層のみを介して配線層に「隣接」する)接地層のことを指す。
図3は、図1、図2Aおよび2Bに示したプリント配線基板1の断面模式図を示す。
各スルーホール100a、100b、101a、101bにはIC(Integrated Circuit)の対応する信号ピンが挿入される。絶縁層105は、各導体層の間に存在し、導体層同士を電気的に絶縁する。
図4に示ように、プリント配線基板1は、図3に示すスルーホールとは別に、接地用スルーホール100cと信号用スルーホール101cの対、及び、接地用スルーホール100dと信号用スルーホール101dの対を有する。本実施形態において、配線層B’は、接地層Bと接地層Dの間に位置し、信号配線103Bを有する。信号配線103Bは、信号用スルーホール101c、101dと接続している。この場合、接地用スルーホール100c、100dはその配線層B’に隣接する隣接接地層B、Dに形成された接地プレーン102B、102Dと接続する(図4参照)。一方、接地用スルーホール100c、100dは、配線層B’と隣接していない非隣接接地層A、Cに形成された接地プレーン102A、102Cからクリアランス104A、104Cによって分離されている。
図5に示すグラフは横軸に電気信号の周波数(Freq[GHz])を、縦軸に信号用スルーホールを伝搬する差動信号の伝送特性(Sdd21[dB])を示している。図5おいて、実線は、図3に示すプリント配線基板1の電気特性を示す。破線は、図10に示すプリント配線2の電気特性を示す。縦軸に示す伝送特性Sdd21[dB]は、値が0(ゼロ)に近いほど差動信号が減衰することなく伝送先に伝わることを表す指標となる。Sdd21の値が低下するほど差動信号が減衰し、伝送特性が悪化していることを示す。
本実施形態によるプリント配線基板1は、例えば図6のようなLSI(Large Scale Integration)端子3を備えている。LSI端子3は、図6に示すように、接続されるLSIの信号ピンに対応する多数のスルーホールによって構成される。
図6に示した部分LSI端子3aに形成された各スルーホール100、101の層構造について、図7を参照しながら説明する。
まず図7に示す接地層Aおよび配線層A’について説明する(図7左上参照)。接地層Aは、配線層A’の下面(紙面奥側)に存在し、配線層A’と隣接している。信号用スルーホール101bは配線層A’に形成された信号配線103Aと接続している。したがって、信号用スルーホール101bと対を成す接地用スルーホール100bは接地層Aに形成される接地プレーン102Aと接続する。接地層Aに形成されるクリアランス104Abは、信号用スルーホール101bの周囲には形成されるが接地用スルーホール100bの周囲には形成されない(図7左上参照)。
図8の左側は、プリント配線基板1の断面構造を示している。コンデンサ4はACカップリング用のコンデンサである。コンデンサ4は伝送線路上において高周波信号のDC成分を除去するために配置される。図8の右側は、プリント配線基板1を構成する各導体層の上面図を示している。上面図における点線X-Yの断面が図8の左側に示す断面図に対応している。
同様に、信号配線103Cの上面及び下面に、信号配線103Cに接続する信号用スルーホール101bと対を成す接地用スルーホール100bに接続された接地プレーン102C及び102Eが存在する。
以上、実施形態を参照して本願発明を示し説明したが、本願発明は上記実施形態に限定されない。当業者であれば、請求項によって画定される本願発明の範囲を逸脱しないで、構成や詳細に様々な変更をすることができることが理解されるであろう。
100、200・・・接地用スルーホール
101、201・・・信号用スルーホール
102、202・・・接地用プレーン
103、203・・・信号配線
104、204・・・クリアランス
3・・・LSI端子
4・・・ACカップリング用コンデンサ
Claims (6)
- 信号配線を有する配線層と、
第1の接地プレーンを有する第1の接地層と、
前記配線層と前記第1の接地層との間に位置し、第2の接地プレーンを有する第2の接地層と、
前記配線層と前記第1および第2の接地層とを貫通し、前記第2の接地プレーンと接続する接地用スルーホールと、
前記配線層と前記第1および第2の接地層とを貫通し、前記信号配線と接続する信号用スルーホールと、
前記第1の接地層に形成され、前記信号用スルーホールおよび前記接地用スルーホールの周囲に位置し、前記第1の接地プレーンを前記信号用スルーホールおよび前記接地用スルーホールから分離する第1のクリアランスと、
前記第2の接地層に形成され、前記信号用スルーホールの周囲に位置し、前記第2の接地プレーンを前記信号用スルーホールから分離する第2クリアランスと
を備えるプリント配線基板。 - 前記第2の接地層は、前記配線層と前記第2の接地層との間に絶縁層のみを挟んで、前記配線層と隣接する請求項1に記載のプリント配線基板。
- 前記接地用スルーホールは、前記信号用スルーホールと対を成すように並置される請求項2に記載のプリント配線基板。
- 前記配線層に対して前記第2の接地層とは反対側に位置し、第3の接地プレーンを有する第3の接地層と、
前記第3の接地層に形成され、前記信号用スルーホールの周囲に位置し、前記第3の接地プレーンを前記信号用スルーホールから分離する第3クリアランスと、
さらに備え、
前記第3の配線層は、前記配線層と前記第3の接地層との間に絶縁層のみを挟んで、前記配線層と隣接し、
前記信号配線は、前記第2接地プレーンと前記第3接地プレーンとに挟まれながら延伸している
請求項3に記載のプリント配線基板。 - プリント配線基板を備える電子機器であって、前記プリント配線基板は、
信号配線を有する配線層と、
第1の接地プレーンを有する第1の接地層と、
前記配線層と前記第1の接地層との間に位置し、第2の接地プレーンを有する第2の接地層と、
前記配線層と前記第1および第2の接地層とを貫通し、前記第2の接地プレーンと接続する接地用スルーホールと、
前記配線層と前記第1および第2の接地層とを貫通し、前記信号配線と接続する信号用スルーホールと、
前記第1の接地層に形成され、前記信号用スルーホールおよび前記接地用スルーホールの周囲に位置し、前記第1の接地プレーンを前記信号用スルーホールおよび前記接地用スルーホールから分離する第1のクリアランスと、
前記第2の接地層に形成され、前記信号用スルーホールの周囲に位置し、前記第2の接地プレーンを前記信号用スルーホールから分離する第2クリアランスと、
を備える電子機器。 - 信号配線を有する配線層と、第1の接地プレーンを有する第1の接地層と、前記配線層と前記第1の接地層との間に位置し、第2の接地プレーンを有する第2の接地層とを備えるプリント配線基板に用いられる配線接続方法であって、
前記配線層と前記第1および第2の接地層とを貫通する接地用スルーホールを、前記第2の接地プレーンと接続し、
前記配線層と前記第1および第2の接地層とを貫通する信号用スルーホールを、前記信号配線と接続し、
第1のクリアランスを、前記信号用スルーホールおよび前記接地用スルーホールの周囲に位置するように、前記第1の接地層に形成して、前記第1の接地プレーンを前記信号用スルーホールおよび前記接地用スルーホールから分離し、
第2クリアランスを、前記信号用スルーホールの周囲に位置するように、前記第2の接地層に形成して、前記第2の接地プレーンを前記信号用スルーホールから分離する
ことを含む配線接続方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/762,321 US9859603B2 (en) | 2013-01-24 | 2014-01-08 | Printed wiring board, electronic device, and wiring connection method |
CN201480005938.0A CN104937767B (zh) | 2013-01-24 | 2014-01-08 | 印刷线路板、电子器件和线路连接方法 |
JP2014558518A JP5983780B2 (ja) | 2013-01-24 | 2014-01-08 | プリント配線基板、電子機器及び配線接続方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013-010899 | 2013-01-24 | ||
JP2013010899 | 2013-01-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014115578A1 true WO2014115578A1 (ja) | 2014-07-31 |
Family
ID=51227370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2014/050148 WO2014115578A1 (ja) | 2013-01-24 | 2014-01-08 | プリント配線基板、電子機器及び配線接続方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9859603B2 (ja) |
JP (1) | JP5983780B2 (ja) |
CN (1) | CN104937767B (ja) |
WO (1) | WO2014115578A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017201680A (ja) * | 2016-05-06 | 2017-11-09 | 明泰科技股▲分▼有限公司 | 伝送路のインピーダンス整合構造 |
JP2019096691A (ja) * | 2017-11-21 | 2019-06-20 | 日本オクラロ株式会社 | プリント回路基板及び当該プリント回路基板を備える光送受信器 |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9769926B2 (en) * | 2015-04-23 | 2017-09-19 | Dell Products L.P. | Breakout via system |
MY172393A (en) * | 2015-12-23 | 2019-11-22 | Intel Corp | Through-hole interconnect network and method of making same |
US10178761B2 (en) * | 2016-04-28 | 2019-01-08 | Hewlett Packard Enterprise Development Lp | Defected ground structure to minimize EMI radiation |
CN106358364B (zh) * | 2016-11-24 | 2023-04-28 | 湖南长城银河科技有限公司 | 一种印刷电路板及Fanout布线方法 |
US10499489B2 (en) | 2017-07-14 | 2019-12-03 | Hewlett Packard Enterprise Development Lp | Defected ground structure with void having resistive material along perimeter to improve EMI suppression |
US10194524B1 (en) * | 2017-07-26 | 2019-01-29 | Cisco Technology, Inc. | Anti-pad for signal and power vias in printed circuit board |
CN108684139B (zh) * | 2018-06-01 | 2020-10-09 | 华为技术有限公司 | 一种电路板 |
US11234325B2 (en) * | 2019-06-20 | 2022-01-25 | Infinera Corporation | Printed circuit board having a differential pair routing topology with negative plane routing and impedance correction structures |
US10674598B1 (en) * | 2019-10-08 | 2020-06-02 | Cisco Technology, Inc. | Measuring effective dielectric constant using via-stub resonance |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107830A1 (ja) * | 2003-06-02 | 2004-12-09 | Nec Corporation | プリント回路基板用コンパクトビア伝送路およびその設計方法 |
JP2007035710A (ja) * | 2005-07-22 | 2007-02-08 | Toshiba Corp | 多層プリント配線板 |
WO2007046271A1 (ja) * | 2005-10-18 | 2007-04-26 | Nec Corporation | 垂直信号経路、それを有するプリント基板及びそのプリント基板と半導体素子とを有する半導体パッケージ |
JP2008507858A (ja) * | 2004-07-23 | 2008-03-13 | 日本電気株式会社 | 多層印刷回路基板の複合ビア構造およびこれを用いたフィルタ |
JP2008130976A (ja) * | 2006-11-24 | 2008-06-05 | Nec Corp | プリント配線基板 |
JP2010073891A (ja) * | 2008-09-18 | 2010-04-02 | Nec Corp | プリント配線基板及びその製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1721496A2 (en) | 2004-02-13 | 2006-11-15 | Molex Incorporated | Preferential ground and via exit structures for printed circuit boards |
CN100544559C (zh) * | 2004-03-09 | 2009-09-23 | 日本电气株式会社 | 用于多层印刷电路板的通孔传输线 |
JP4430976B2 (ja) * | 2004-05-10 | 2010-03-10 | 富士通株式会社 | 配線基板及びその製造方法 |
CN101176391A (zh) * | 2005-01-10 | 2008-05-07 | 圣米纳-Sci公司 | 具有改善的差分信号对的信号完整性的印刷电路板等 |
JP4452232B2 (ja) * | 2005-11-15 | 2010-04-21 | 日本特殊陶業株式会社 | プリント配線基板及びその製造方法 |
JP4763491B2 (ja) | 2006-03-24 | 2011-08-31 | 三菱電機株式会社 | 半田付け方向の設計支援装置および半田付け方向の設計支援方法 |
US20080112037A1 (en) | 2006-11-10 | 2008-05-15 | Spatial Photonics, Inc. | Hermetic sealing of micro devices |
-
2014
- 2014-01-08 CN CN201480005938.0A patent/CN104937767B/zh not_active Expired - Fee Related
- 2014-01-08 JP JP2014558518A patent/JP5983780B2/ja active Active
- 2014-01-08 WO PCT/JP2014/050148 patent/WO2014115578A1/ja active Application Filing
- 2014-01-08 US US14/762,321 patent/US9859603B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004107830A1 (ja) * | 2003-06-02 | 2004-12-09 | Nec Corporation | プリント回路基板用コンパクトビア伝送路およびその設計方法 |
JP2008507858A (ja) * | 2004-07-23 | 2008-03-13 | 日本電気株式会社 | 多層印刷回路基板の複合ビア構造およびこれを用いたフィルタ |
JP2007035710A (ja) * | 2005-07-22 | 2007-02-08 | Toshiba Corp | 多層プリント配線板 |
WO2007046271A1 (ja) * | 2005-10-18 | 2007-04-26 | Nec Corporation | 垂直信号経路、それを有するプリント基板及びそのプリント基板と半導体素子とを有する半導体パッケージ |
JP2008130976A (ja) * | 2006-11-24 | 2008-06-05 | Nec Corp | プリント配線基板 |
JP2010073891A (ja) * | 2008-09-18 | 2010-04-02 | Nec Corp | プリント配線基板及びその製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017201680A (ja) * | 2016-05-06 | 2017-11-09 | 明泰科技股▲分▼有限公司 | 伝送路のインピーダンス整合構造 |
JP2019096691A (ja) * | 2017-11-21 | 2019-06-20 | 日本オクラロ株式会社 | プリント回路基板及び当該プリント回路基板を備える光送受信器 |
US11057986B2 (en) | 2017-11-21 | 2021-07-06 | Lumentum Japan, Inc. | Printed circuit board and optical transceiver with the printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
CN104937767B (zh) | 2018-01-19 |
CN104937767A (zh) | 2015-09-23 |
JP5983780B2 (ja) | 2016-09-06 |
JPWO2014115578A1 (ja) | 2017-01-26 |
US9859603B2 (en) | 2018-01-02 |
US20150359084A1 (en) | 2015-12-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5983780B2 (ja) | プリント配線基板、電子機器及び配線接続方法 | |
US9986634B2 (en) | Circuit board via configurations for high frequency signaling | |
JP4371065B2 (ja) | 伝送線路、通信装置及び配線形成方法 | |
US7505285B2 (en) | Main board for backplane buses | |
JP5194440B2 (ja) | プリント配線基板 | |
US6614325B1 (en) | RF/IF signal distribution network utilizing broadside coupled stripline | |
US6388208B1 (en) | Multi-connection via with electrically isolated segments | |
US8309863B2 (en) | Printed wiring board | |
US20060237227A1 (en) | Circuit board via structure for high speed signaling | |
JP6388667B2 (ja) | 差動データ信号を送信するための装置及び方法 | |
US8748753B2 (en) | Printed circuit board | |
JP2010506380A (ja) | 多層基板 | |
WO2014022688A1 (en) | Multi-layer transmission lines | |
US20070194434A1 (en) | Differential signal transmission structure, wiring board, and chip package | |
EP1568099B1 (en) | A circuit that taps a differential signal | |
CN112153806A (zh) | 可挠电路板 | |
US7196906B1 (en) | Circuit board having segments with different signal speed characteristics | |
CN113453415B (zh) | 信号传输电路以及印刷电路板 | |
TWM599507U (zh) | 使用串列環形地平面結構之寬頻共模抑制濾波裝置 | |
CN211702518U (zh) | 电路板结构 | |
JP6452332B2 (ja) | プリント回路板 | |
US8952260B1 (en) | Circuit boards defining regions for controlling a dielectric constant of a dielectric material | |
TWM596427U (zh) | 寬頻步階式地平面結構之雜訊濾波裝置 | |
JPH0265197A (ja) | 多層プリント基板 | |
JP2017045863A (ja) | 印刷配線板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 14743286 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2014558518 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 14762321 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 14743286 Country of ref document: EP Kind code of ref document: A1 |