WO2014080649A1 - 標本化レート変換装置 - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/132—Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/0642—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being arbitrary or irrational
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- H—ELECTRICITY
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- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/117—Filters, e.g. for pre-processing or post-processing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/164—Feedback from the receiver or from the transmission channel
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/167—Position within a video image, e.g. region of interest [ROI]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/182—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
Definitions
- the present invention relates to a sampling rate conversion device used for a digital image size conversion device, digital audio, or the like.
- a sampling rate converter is used to convert an input digital signal sampled at the input sampling rate into an output digital signal sampled at the output sampling rate.
- an output digital signal is obtained by taking out (down-sampling) a sample that matches the output sampling rate R2 from a sequence of N times the sample value of the input digital signal.
- FIG. 10 is a diagram for explaining a conventional sampling rate conversion method.
- a circle in the figure indicates a digital signal having a sampling rate R3.
- a circle with hatched lines indicates an input digital signal at the input sampling rate R1
- a bold circle indicates an output digital signal at the output sampling rate R2
- a thin white circle indicates other than the input / output digital signal.
- sampling rate R3 These digital signals of sampling rate R3 are calculated from the input digital signal (upsampling). At that time, an interpolation value calculation is performed using an FIR-LPF (Finite Impulse Response Low Pass Filter) having a characteristic of blocking a frequency component that is 1/2 or more of the output sampling rate R2. Then, an output digital signal having an output sampling rate R2 is extracted from the digital signal having a sampling rate R3 (down sampling).
- FIR-LPF Finite Impulse Response Low Pass Filter
- the case where the sampling rate is reduced is called down-sampling.
- FIR-LPF is used to block the high frequency component of the input and suppress aliasing noise due to a decrease in sampling rate.
- the case where the sampling rate is increased is called up-sampling.
- up-sampling it is not necessary to block the high frequency component of the input, but FIR-LPF is used to calculate an interpolation value at a position different from the input digital signal.
- FIG. 11 is a diagram showing an impulse response of the FIR-LPF.
- the impulse response of the filter is expressed by a time function obtained by inverse Fourier transform of a predetermined filter characteristic.
- the impulse response waveform exists before and after time 0.
- an output digital signal at time 0 is calculated using an input digital signal in the existence range of the impulse response waveform.
- the impulse response waveform continues for a long time, but in order to make it practical, the impulse response waveform is cut to a certain finite length to perform signal processing.
- the impulse response start time (negative time) is set to 0 or a positive number. Specifically, the impulse response start time -T is converted to 0, and the original time 0 is set to T to perform sampling rate conversion. In digital signal processing, such a time shift process can be performed by using a memory (shift register).
- a sample sampled at a high sampling rate R3 in which both samples of the sampling rates R1 and R2 are present is generated, and a sample string at the sampling rate R2 is extracted therefrom.
- An apparatus using such a very high sampling rate R3 has been difficult to realize with inexpensive semiconductor technology.
- the design of a digital circuit having three operation clock frequencies corresponding to the three sampling rates R1, R2, and R3 is complicated and difficult.
- a general-purpose sampling rate conversion apparatus that can cope with an arbitrary input / output sampling rate (that is, M and N are arbitrary) is desired.
- the sampling rate is substantially proportional to the number of pixels. For example, a plurality of transformations of 1 / ⁇ 2 in horizontal and vertical (actually 7/10 for rational ratio), 1/2, 1 / 2 ⁇ 2, 1/4,... are prepared. .
- the sampling rate can be set to 1 in the original image, and can be prepared in a wide range such as 1/2, 1/4, 1/8, and so on. For this reason, even if a network quality variation (a variation in a usable sampling rate) occurs, the service can be continued without stopping.
- the present invention has been made in order to solve the above-described problems, and its purpose is to enable parallel conversion to a plurality of sampling rates, a small circuit scale, and a general-purpose sampling rate conversion apparatus. Is what you get.
- sampling rate conversion devices for conversion into 1, 2,..., A), respectively, and the position coordinates of the input digital signals close to the position coordinates Tki of the plurality of output digital signals Yki and the position coordinates Tki, respectively.
- FIR-LPF Finite Impulse Response Low Pass Filter
- a sampling rate conversion apparatus according to an embodiment of the present invention will be described with reference to the drawings.
- the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.
- FIG. 1 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 1 of the present invention.
- a plurality of (a) output digital signals Yki (i 1, 2,...) Obtained by sampling input digital signals sampled at an input sampling rate at different output sampling rates. , A), respectively.
- Divider 1 divides the processing clock by 1/2 to generate an input clock.
- the frequency of the input clock is 1 ⁇ 2 of the frequency of the processing clock.
- the shift register 2 sequentially inputs input digital signals in synchronization with the input clock, stores a predetermined number (p) of input digital signals, and outputs them in parallel.
- the plurality of registers 3 a to 3 c primarily stores the input digital signal group input in parallel from the shift register 2.
- the parallel FIR calculator 4 converts the input digital signal groups IN1, IN2, and IN3 supplied from one of the registers 3a to 3c into output digital signals.
- an input digital signal close to the position coordinate Tki means (1) an input digital signal whose position coordinate difference from the position coordinate Tki is 0 or the closest positive number, and (2) a position coordinate with the position coordinate Tki.
- the target input digital signal may be shifted by one input sample period.
- FIG. 2 is a block diagram showing the position coordinate difference calculation unit according to Embodiment 1 of the present invention.
- the position coordinate difference calculation unit 5 a includes an input integrator 6, an output integrator 7, an integrated value comparator 8 that controls them, and an ID generation unit 9.
- the configuration of the position coordinate difference calculation units 5b and 5c is the same.
- C1 is a constant
- M1 and N1 are relatively prime integers
- the sampling period of the input digital signal is C1 ⁇ M1
- the sampling period of the output digital signal is C1 ⁇ N1.
- the input integrator 6 integrates M1 and outputs an integrated value Sm1.
- the output integrator 7 integrates N1 and outputs an integrated value Sn1.
- the integrated value comparator 8 causes the input integrator 6 to integrate M1 when Sm1 ⁇ Sn1.
- Sn1 ⁇ Sm1 N1 is accumulated in the output integrator 7, and Sn1-Sm1 when N1 is accumulated in the output integrator 7 is output as the position coordinate difference Dk1.
- the ID generation unit 9 outputs ID1.
- the calculation instruction signal 1 is output, and the calculation instruction signal 1 is maintained and stored in the register 10 and sent to the control unit 11 and the register 3a.
- the register 3a stores the input digital signal group when the calculation instruction signal 1 is received. Thereafter, after receiving the calculation instruction signal 1, the control unit 11 returns a clear signal to the register 10 to clear the calculation instruction signal 1. Since the calculation instruction signal maintains the same state for several clocks of the processing clock, calculation corresponding to the calculation instruction signals from the respective position coordinate difference calculation units 5a to 5c can be performed during that period.
- the initial value detection reset unit 12 resets Sm1 and Sn1 to the initial values when the difference between Sm1 and Sn1 matches the initial value. Note that Sm1 and Sn1 are also reset to initial values when a reset signal is input from the outside.
- the RAM Random Access Memory
- ROM Read Only Memory
- the FIR coefficient memories 13a to 13c store the position coordinates of the output digital signal Yki.
- FIR coefficient F (Tki-Zki (q)) corresponding to Zki (q)) is output.
- the FIR coefficient memories 13a to 13c store a set of FIR coefficients for each type of position coordinate difference Dki, and select and output a set of FIR coefficients according to the input position coordinate difference Dki. Since there are Mi output cycles Ni during the period of the least common multiple Mi ⁇ Ni of the input cycle Mi and the output cycle Ni, there are Mi kinds of position coordinate differences Dki, and Mi sets of FIR coefficients are required. Note that the FIR coefficient memories 13a to 13c are not individual elements, but generally use a single RAM that is distinguished by an address.
- Yki F (Tki ⁇ Zki (1)) * Xki (1) + F (Tki ⁇ Zki (2)) * Xki (2) +... + F (Tki ⁇ Zki (p)) * Xki (p) is calculated to obtain the output digital signal Yki (FIR-LPF interpolation calculation).
- the parallel FIR computing unit 4 is an 8-Tap parallel FIR computing unit that performs a parallel product-sum operation using eight input digital signals to obtain one output digital signal.
- the input digital signal group, the FIR coefficient group, and the identification code ID necessary for calculating the output digital signal are temporarily stored in the register.
- the FIR coefficients output from the FIR coefficient memories 13a to 13c and the identification codes ID1 to ID3 are temporarily stored in the FIR coefficient output registers 14a to 14c, respectively, and the registers 3a to 3c receive the calculation instruction signals. Save the group.
- the control unit 11 sequentially reads them and supplies them to the parallel FIR computing unit 4.
- the control unit 11 is a parallel-serial converter (Priority-Encoder), and when the position coordinate differences corresponding to two or more different output digital signals are calculated simultaneously, the FIR coefficient corresponding to each position coordinate difference is calculated.
- the group and the group of input digital signals are supplied to the parallel FIR computing unit 4 according to a predetermined order.
- the position coordinate difference is calculated simultaneously by the three position coordinate difference calculation units 5a to 5c, the signal of the position coordinate difference calculation unit 5a is first, the position coordinate difference calculation unit 5b is second, and the position coordinate difference is The calculation unit 5c is processed third.
- the output digital signal obtained by the parallel FIR computing unit 4 is temporarily stored in the output memories 16a to 16c corresponding to the ID by the selector 15 and output in synchronization with the output clock.
- FIG. 3 is a diagram for briefly explaining the principle of FIR-LPF interpolation calculation.
- circles with diagonal lines indicate input digital signals, and bold circles indicate output digital signals.
- the input period M is 4 and the output period N is 5.
- An output digital signal Yk present at a position Tk that does not exist in the input digital signal is interpolated and calculated from the surrounding input digital signal Xk (q).
- the impulse response waveform of the filter continues for a long time, but in order to make it practical, signal processing is performed by cutting the impulse response waveform to a certain finite length.
- about 30 input digital signals around the output digital signal Yk (15 before and after) are used.
- 7-Tap FIR-LPF is used which calculates an output digital signal from seven input digital signals. Since the proximity input digital signal of Yk is Xk (4), Yk is calculated using seven input digital signals Xk (1) to Xk (7) in the vicinity of Yk. Further, since the proximity input digital signal of Yk + 1 is Xk (5) (positions coincide), Yk + 1 is calculated using the input digital signals Xk (2) to Xk (8) in the vicinity of Yk + 1. Xk (2) to Xk (8) can also be expressed as Xk + 1 (1) to Xk + 1 (7).
- FIG. 4 is a diagram showing the positions of input / output digital signals.
- a circle indicates the position of the input / output digital signal, and the initial position is 0 for both input and output.
- the position of the output digital signal Yk3 20.
- Table 1 shows the transition of the integrated value in the present embodiment.
- Mod7 phase difference in the table means Modulo (Sni ⁇ Smi, 7), and is a remainder (0 to 6) obtained by dividing Sni ⁇ Smi by 7.
- the integration of the input cycles M1 to M3 is not once every processing clock, but once every two clocks.
- the sampling rate of the input digital signal is 74 MHz (interlace HD video frequency)
- the integration of the input period M is set to once every two times.
- Table 2 shows the operation state of the control unit.
- the priority order of the input digital signal group to be processed is IN1> IN2> IN3.
- a clear signal is output for the processed calculation instruction signal. For example, in state 3 (calculation instruction signals 1 and 2 are 1), IN1 is selected and output, and clear signal 1 is also output. When IN1 is processed and calculation instruction signal 1 is cleared by clear signal 1, the state shifts to state 2 (only calculation instruction signal 2 is 1).
- the position coordinates of the input digital signal close to the position coordinates of the output digital signal are specified. Based on the position coordinates and the input sampling rate, the position coordinates of a certain number of input digital signals to be used in the FIR-LPF can be obtained. An output digital signal can be calculated by reading out FIR coefficients to be applied to those input digital signals from the memory and performing FIR-LPF interpolation calculation.
- the present embodiment can operate at an arbitrary clock frequency that is not related to the input / output sampling rate in principle. Therefore, it is general purpose because it can cope with an arbitrary input / output sampling rate (that is, M and N are arbitrary). Conventionally, the sampling rate of the least common multiple of the input sampling rate and the output sampling rate has been used, but in the present embodiment, the use of such a high sampling rate can be avoided.
- the conventional apparatus operates at three clock frequencies, but the apparatus of the present embodiment can operate at one clock frequency. For this reason, the sampling rate conversion apparatus according to the present embodiment can be realized by an inexpensive semiconductor technology.
- the control unit 11 when the position coordinate differences corresponding to two or more different output digital signals are simultaneously calculated, the control unit 11 inputs the group of FIR coefficients corresponding to the respective position coordinate differences and the input. A group of digital signals is supplied to the parallel FIR computing unit 4 according to a predetermined order. Thereby, parallel conversion to a plurality of sampling rates is possible. And the control part 11 carries out the time division operation
- the magnitude relationship between Smi and Sni is determined, Mi is added to Smi and Ni is added to Sni so as to maintain a state where Smi and Sni substantially match, and the input / output digital signal is added. Calculate the positional relationship. Thereby, the position coordinate of the input digital signal close to the position coordinate of the output digital signal can be easily specified.
- the values of the input cycle indexes M1 to Ma can be taken so as to be relatively prime to the values of the output cycle indexes N1 to Na.
- the operation of the input / output integrator is repeated for each least common multiple of each input / output cycle pair. Therefore, the position coordinate difference calculation units 5a to 5c reset Smi and Sni to initial values every time Smi and Sni become the least common multiple of Mi and Ni. Thereby, the number of constituent bits of the input / output integrator can be reduced.
- the position coordinate difference calculation units 5a to 5c share the input digital signal and the shift register, but can be reset individually.
- resetting is performed each time the integrated value reaches the least common multiple.
- This reset means that the positional relationship of the input / output digital signals is the same as that at the time of the first reset (the input / output positional coordinates match).
- the reset may be performed when the difference value between Smi and Sni becomes an initial value.
- the shift register samples the input digital signal in synchronization with the input clock, and the position coordinate difference calculation units 5a to 5c perform calculation in synchronization with the input clock.
- FIG. FIG. 5 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 2 of the present invention.
- FIG. 6 is a block diagram showing a position coordinate difference calculation unit according to Embodiment 2 of the present invention.
- the difference from Embodiment 1 is that one input integrator is shared in the calculation of a plurality of output digital signals.
- the position coordinate difference calculation unit 5 includes one input integrator 6, three output integrators 7a to 7c, three integrated value comparators 8a to 8c for controlling them, and three ID generators 9a to 9c.
- the input integrator 6 integrates M in synchronization with the input clock and outputs an integrated value Sm.
- the output integrators 7a to 7c integrate Ni and output integrated values Sni.
- the integrated value comparators 8a to 8c cause the input integrator 6 to integrate M when Sm ⁇ Sni.
- Sni ⁇ Sm Ni is integrated in the output integrator 7 and Sni ⁇ Sm when the output integrator 7 is integrated with Ni is output as the position coordinate difference Dki.
- the ID generation unit 9 outputs IDi.
- calculation instruction signals 1 to 3 are output, and the calculation instruction signals 1 to 3 are maintained and stored in the registers 10a to 10c, respectively, and sent to the control unit 11 and the registers 3a to 3c.
- Other configurations are the same as those of the first embodiment.
- the integrated value changes as in the first embodiment. Therefore, the circuit scale can be further reduced while obtaining the same effect as that of the first embodiment.
- FIG. FIG. 7 is a block diagram showing a sampling rate conversion apparatus according to Embodiment 3 of the present invention.
- the input digital signal group is not directly stored in the register as in the first and second embodiments, but the count value of the counter 17 is stored in the registers 18a to 18c.
- the counter 17 counts in synchronization with the shift register 2. This count value indicates the operating state of the shift register 2.
- the FIR coefficient is not directly stored in the register, but the ID (2 bits) and the phase difference Dki respectively corresponding to the three output digital signals are stored in the registers 19a to 19c.
- the parallel / serial converter 20 of the control unit 11 calculates each position coordinate difference and each position coordinate difference when the position coordinate differences respectively corresponding to two or more different output digital signals are calculated simultaneously.
- the first count value which is the value of the counter 17 at the time, is stored in the FIR calculation parameter FIFO 21 according to a predetermined order.
- the data selector 22 corresponds to the first count value from the shift register 2 based on the difference value between the second count value that is the current value of the counter 17 and the first count value stored in the registers 18a to 18c.
- the ID code among FIR calculation parameters indicates the type of FIR (output digital signal to be calculated) and is expressed by a position coordinate difference (Modulo (M)). It can be seen which position difference (phase) coefficient group of the FIR coefficients should be used from the respective values (Sn1-Sm, Sn2-Sm, Sn3-Sm).
- Table 4 shows the transition of the integrated value in the case of the present embodiment.
- the sampling rate of the input digital signal is 74 MHz.
- the sampling rate of the three output digital signals is converted in approximately 1 / ⁇ 2 steps (actually 7/10).
- Sampling rates F1, F2, and F3 of the three output digital signals are 52 MHz, 37 MHz, and 26 MHz, respectively.
- the sampling rate of the input / output digital signal is the same, but the frequency of the processing clock has decreased from 148 MHz to 123 MHz, so that there are fewer cycles in which the output digital signal is not calculated. I understand.
- the capacity of the registers 3a to 3c and the FIR coefficient memories 13a to 13c is considerably increased.
- the shift register 2 is expanded by 3 samples.
- the FIR operation may be delayed by a clock, so the capacity of the shift register 2 is set to be p + a input digital signals. If 3 sets are parallel, 3 samples should be expanded.
- the capacity of the shift register 2 is 300 bits for 30 pixels in the first embodiment, but increases to 330 bits for 33 pixels in the present embodiment.
- FIG. FIG. 8 is a block diagram showing a position coordinate difference calculation unit according to Embodiment 4 of the present invention.
- the position coordinate difference calculation unit 5 further includes a comparison subtracter 23 in addition to the configuration of the second embodiment (not shown).
- E is a positive integer greater than or equal to M1 or greater than N1 to N3
- the comparison subtractor 23 supplies the load clock to the input integrator 6 and the output integrator 7 simultaneously when Sm and all Sn1 to Sn3 are equal to or greater than E, E is subtracted simultaneously from Sm and Sn1 to Sn3.
- Table 5 shows the transition of the integrated value Sm and Sn1 to Sn3 in the present embodiment.
- the frequency of the processing clock is 123.3 MHz, and the sampling rate of the output digital signal is 52 MHz, 37 MHz, and 26 MHz.
- the input / output operation is the same as in Table 3, but an E subtraction signal column is added.
- E 25
- E 32
- the comparison between each integrated value and E can be made by determining whether the sixth bit is 1 or 0, and subtraction of E can be performed by simply setting 1 in the sixth bit to 0. Therefore, it is preferable to set E to a power of 2.
- the least common multiple of a + 1 positive integers is a relatively large value, this embodiment is more practical.
- FIG. 9 is a diagram illustrating a state in which an input clock of 74 MHz is generated from a processing clock of 123.3 MHz.
- the input clock is not a uniform clock, but the processing clock is divided every 5 cycles, and 3 out of 5 cycles are used. This state is also shown in “M integration” in Table 3.
- the processing clock is divided to generate an input clock having a frequency A1 / A2 (A1 and A2 are positive integers) times the frequency of the processing clock.
- the input digital signal is transferred to the shift register for A2 cycles of the A1 cycle of the processing clock.
- the frequency of the input clock can be controlled, a circuit that operates synchronously according to mounting conditions can be realized.
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Abstract
Description
図1は本発明の実施の形態1に係る標本化レート変換装置を示すブロック図である。この装置は、入力標本化レートで標本化された入力デジタル信号を、互いに異なる出力標本化レートで標本化された複数(a個)の出力デジタル信号Yki、(i=1,2,・・・,a)にそれぞれ変換する。本実施の形態では3つの出力デジタル信号Yk1~Yk3への変換を行う(即ちa=3)。
図5は、本発明の実施の形態2に係る標本化レート変換装置を示すブロック図である。図6は、本発明の実施の形態2に係る位置座標差算出部を示すブロック図である。複数の出力デジタル信号の演算において1つの入力積算器を共有する点が実施の形態1とは異なる。
図7は、本発明の実施の形態3に係る標本化レート変換装置を示すブロック図である。本実施の形態では、実施の形態1,2のように入力デジタル信号群を直接レジスタに記憶させるのではなく、カウンタ17のカウント値をレジスタ18a~18cに記憶させる。カウンタ17はシフトレジスタ2に同期してカウントする。このカウント値はシフトレジスタ2の動作状態を示す。
図8は、本発明の実施の形態4に係る位置座標差算出部を示すブロック図である。位置座標差算出部5は実施の形態2の構成(不図示)に加えて比較減算器23を更に有する。EをM以上又はN1~N3以上の正整数として、比較減算器23はSmと全てのSn1~Sn3がE以上である場合に入力積算器6及び出力積算器7に同時にLoadクロックを供給し、SmとSn1~Sn3から同時にEを減算する。
Claims (7)
- 入力標本化レートで標本化された入力デジタル信号を、互いに異なる出力標本化レートで標本化された複数(a個)の出力デジタル信号Yki、(i=1,2,・・・,a)にそれぞれ変換する標本化レート変換装置であって、
前記複数の出力デジタル信号Ykiの位置座標Tkiにそれぞれ近接する入力デジタル信号の位置座標と位置座標Tkiとの位置座標差Dkiをそれぞれ算出する位置座標差算出部と、
前記出力標本化レートの1/2以上の周波数成分を遮断する特性を有するFIR-LPF(Finite Impulse Response Low Pass Filter)に入力されるインパルス入力の位置座標をz=0とした場合における前記FIR-LPFのFIR係数F(z)を保存し、前記位置座標差Dkiが入力されると、前記出力デジタル信号Ykiの位置座標Tkiの周辺近傍に存在する一定個数(p個)の入力デジタル信号Xki(q)の位置座標をZki(q)、(q=1,2,・・・,p)として位置座標差(Tki-Zki(q))に対応するFIR係数F(Tki-Zki(q))を出力するFIR係数メモリと、
Yki=F(Tki-Zki(1))*Xki(1)+F(Tki-Zki(2))*Xki(2)+…+F(Tki-Zki(p))*Xki(p)を演算して前記複数の出力デジタル信号Ykiを求めるFIR演算器と、
異なる2つ以上の前記出力デジタル信号にそれぞれ対応する前記位置座標差が同時に算出された場合に、それぞれの位置座標差に対応する前記FIR係数の群と前記入力デジタル信号の群を予め定めた順番に従って前記FIR演算器に供給する制御部とを備えることを特徴とする標本化レート変換装置。 - Ci、(i=1,2,・・・,a)を定数、MiとNiを互いに素な正整数として、前記入力デジタル信号の標本化周期をCi・Miとし、前記複数の出力デジタル信号の標本化周期をCi・Niとし、
前記位置座標差算出部は、
Miを積算して積算値Smiをそれぞれ出力する複数(a個)の入力積算器と、
Niを積算して積算値Sniをそれぞれ出力する複数(a個)の出力積算器と、
Smi-Sniが所定値以下の場合に前記入力積算器にMiを積算させ、Sni-Smiが所定値以下の場合に前記出力積算器にNiを積算させ、前記出力積算器にNiを積算させた際のSni-Smiを前記位置座標差Dkiとしてそれぞれ出力する複数(a個)の積算値比較器とを有することを特徴とする請求項1に記載の標本化レート変換装置。 - 前記位置座標差算出部は、SmiとSniがMiとNiの最小公倍数となるごとにSmiとSniを初期値にリセットすることを特徴とする請求項2に記載の標本化レート変換装置。
- Ciを定数、MとNi、(i=1,2,・・・,a)を互いに素な正整数として、前記入力デジタル信号の標本化周期をCi・Mとし、前記複数の出力デジタル信号の標本化周期をCi・Niとし、
前記位置座標差算出部は、
Mを積算して積算値Smを出力する入力積算器と、
Niを積算して積算値Sniをそれぞれ出力する複数(a個)の出力積算器と、
Sni-Smが所定値以下の場合に前記出力積算器にNiを積算させ、前記出力積算器にNiを積算させた際のSni-Smを前記位置座標差Dkiとしてそれぞれ出力する複数(a個)の積算値比較器とを有することを特徴とする請求項1に記載の標本化レート変換装置。 - 前記入力デジタル信号を順に記憶するシフトレジスタと、
前記シフトレジスタに同期したカウンタとを更に備え、
前記制御部は、
異なる2つ以上の前記出力デジタル信号にそれぞれ対応する前記位置座標差が同時に算出された場合に、それぞれの位置座標差と、それぞれの位置座標差が算出された際の前記カウンタの値である第1のカウント値とを予め定めた順番に従って保存するメモリと、
現在の前記カウンタの値である第2のカウント値と前記第1のカウント値との差分値に基づいて前記シフトレジスタから前記第1のカウント値に対応する前記入力デジタル信号の群を読み出して、前記FIR演算器に供給するデータセレクタとを有することを特徴とする請求項1~4の何れか1項に記載の標本化レート変換装置。 - 前記位置座標差算出部は、EをM以上又はNi以上の正整数として、Smと全てのSniがE以上である場合にSmとSniから同時にEを減算する比較減算器を更に有することを特徴とする請求項4に記載の標本化レート変換装置。
- 処理クロックF0を分周して入力クロックを生成する分周器を更に備え、
前記位置座標差算出部は前記入力クロックに同期して算出を行い、
前記複数の出力デジタル信号の出力標本化レートをそれぞれF1、F2、・・・Faとして、F0≧F1+F2+・・・Faとなることを特徴とする請求項1~6の何れか1項に記載の標本化レート変換装置。
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ATE14358T1 (de) | 1980-11-26 | 1985-08-15 | Studer Willi Ag | Verfahren und schaltungsanordnung zur umsetzung der abtastfrequenz einer abtastfolge unter umgehung der konversion in ein kontinuierliches signal. |
JP2600236B2 (ja) * | 1987-12-29 | 1997-04-16 | ソニー株式会社 | サンプリング周波数変換回路 |
US5719571A (en) | 1995-09-22 | 1998-02-17 | Sony Corporation | Sampling rate converting method and apparatus |
FR2826816B1 (fr) | 2001-06-29 | 2003-09-26 | St Microelectronics Sa | Dispositif de conversion d'une sequence d'echantillons numeriques |
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JPH04235407A (ja) * | 1991-01-10 | 1992-08-24 | Matsushita Electric Ind Co Ltd | アナログ/ディジタル変換方式 |
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BR112015011570B1 (pt) | 2021-11-23 |
BR112015011570A2 (pt) | 2017-07-11 |
US20150304660A1 (en) | 2015-10-22 |
JP5573926B2 (ja) | 2014-08-20 |
JP2014103639A (ja) | 2014-06-05 |
US10397579B2 (en) | 2019-08-27 |
EP2924879A4 (en) | 2016-08-24 |
EP2924879B1 (en) | 2017-08-30 |
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