WO2014063380A1 - Mosfet的制造方法 - Google Patents

Mosfet的制造方法 Download PDF

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Publication number
WO2014063380A1
WO2014063380A1 PCT/CN2012/083749 CN2012083749W WO2014063380A1 WO 2014063380 A1 WO2014063380 A1 WO 2014063380A1 CN 2012083749 W CN2012083749 W CN 2012083749W WO 2014063380 A1 WO2014063380 A1 WO 2014063380A1
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Prior art keywords
shallow trench
layer
semiconductor substrate
region
sidewall
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French (fr)
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尹海洲
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/430,690 priority Critical patent/US9324835B2/en
Publication of WO2014063380A1 publication Critical patent/WO2014063380A1/zh
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H10D62/115—Dielectric isolations, e.g. air gaps
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
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Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a stress-enhanced MOSFET. Background technique
  • MOSFETs metal oxide semiconductor field effect transistors
  • the performance of the semiconductor material e.g., mobility
  • the device performance of the MOSFET itself e.g., threshold voltage
  • the carrier mobility can be increased, thereby reducing the on-resistance and increasing the switching speed of the device.
  • a tensile stress should be applied to the channel region along the longitudinal direction of the channel region, and a compressive stress is applied to the channel region along the lateral direction of the channel region to enhance the carrier as a carrier.
  • the mobility of electrons Conversely, when the transistor is a P-type MOSFET, the channel region should be stressed along the longitudinal direction of the channel region, and a tensile stress is applied to the channel region along the lateral direction of the channel region to enhance the carrier as a carrier.
  • the mobility of holes is
  • the formation of the source and drain regions using a semiconductor material different from the material of the semiconductor substrate can produce the desired stress.
  • the Si:C source and drain regions formed on the Si substrate can serve as a stressor, and a tensile stress is applied to the channel region along the longitudinal direction of the channel region.
  • the SiGe source and drain regions formed on the Si substrate can serve as a stressor, and compressive stress is applied to the channel region along the longitudinal direction of the channel region.
  • FIGS. 1-4 show schematic diagrams of semiconductor structures for fabricating various stages of a stress-enhanced MSOFET in accordance with methods of the prior art, wherein the semiconductor structures are shown in the longitudinal direction of the channel region in Figures la, 2a, 3a, 4a
  • a cross-sectional view of the semiconductor structure along the lateral direction of the channel region is shown in Figures 3b, 4b
  • a top view of the semiconductor structure is shown in Figures lb, 2b, 3c, 4c.
  • a line AA indicates a clipping position along a longitudinal direction of the channel region
  • a line BB indicates a clipping position along a lateral direction of the channel region.
  • the method begins with the semiconductor structure shown in FIGS.
  • the stacked, gate stack includes a gate dielectric 103 and a gate conductor 104.
  • the semiconductor substrate 101 is etched to a desired depth, thereby forming an opening at a position corresponding to the source and drain regions of the semiconductor substrate 101, as shown in FIG. 2a and 2b are shown.
  • the semiconductor layer 106 is epitaxially grown to form a source region and a drain region. A portion of the semiconductor substrate 101 below the gate dielectric 103 and between the source and drain regions will serve as a channel region.
  • the semiconductor layer 106 grows from the surface of the semiconductor substrate 101 and is selective. That is, the growth rate of the semiconductor layer 106 on the crystal l ine surface of the semiconductor substrate 101 is different.
  • the semiconductor substrate 101 is composed of Si and the semiconductor layer 106 is composed of SiGe having an atomic percentage of Ge of about 10-15%
  • the semiconductor layer 106 grows most on the ⁇ 1 1 1 ⁇ crystal plane of the semiconductor substrate 101. slow.
  • the formed semiconductor layer 106 includes not only the (100) main surface parallel to the surface of the semiconductor substrate 101, but also the ⁇ 1 1 1 ⁇ facet at a position adjacent to the shallow trench isolation 102 and the side wall 105. (facet), this is called the edge effect of the growth of the semiconductor layer 106, as shown in Figures 3a, 3b and 3c.
  • the facet of the semiconductor layer 106 is undesirable because it results in an increase in its free surface, causing stress in the semiconductor layer 106 to be released, thereby reducing the stress applied to the channel region.
  • silicidation is performed on the surface of the semiconductor layer 106 to form a metal silicide layer 107 as shown in Figs. 4a, 4b and 4c. This silicidation consumes a portion of the semiconductor material of the semiconductor layer 106. Due to the presence of the small facets of the semiconductor layer 106, silicidation can proceed along the small facets, possibly eventually reaching the semiconductor substrate 101.
  • silicidation in the semiconductor substrate 101 is undesirable because it may form a metal silicide in the junction region, resulting in an increase in junction leakage.
  • a method of fabricating a MOSFET comprising: forming a shallow trench in a semiconductor substrate, The shallow trench surrounds the active region; performing a first ion implantation on one sidewall of the active region via the shallow trench to form a first heavily doped region in the one sidewall; a second ion implantation is performed on the opposite sidewall of the source region to form a second heavily doped region in the one sidewall; the shallow trench is filled with an insulating material to form an active region for defining the MOSFET Shallow trench isolation; forming a gate stack and an insulating layer on the semiconductor substrate, the insulating layer as a sidewall surrounding the gate stack and a cap covering the gate stack; isolated by shallow trench, first heavily doped region a second heavily doped region and an insulating layer are used as a hard mask to form an opening in the semiconductor substrate; a bottom surface and a sidewall of the opening are used as a growth seed layer to epitaxially grow the semiconductor layer; and the semiconductor
  • the method utilizes a source region and a drain region formed of a semiconductor layer to apply stress to a channel region in a semiconductor substrate. Since the bottom surface and the side walls of the opening are grown seed layers during epitaxial growth, the semiconductor layer can completely fill the openings in the semiconductor substrate. The U 1 1 ⁇ facet of the semiconductor layer is only in its continued growth portion, thereby suppressing the influence of the edge effect.
  • FIGS 1-4 show schematic diagrams of semiconductor structures for fabricating various stages of a stress-enhanced MSOFET in accordance with methods of the prior art, wherein the semiconductor structures are shown in the longitudinal direction of the channel region in Figures la, 2a, 3a, 4a
  • a cross-sectional view of the semiconductor structure along the lateral direction of the channel region is shown in Figures 3b, 4b
  • a top view of the semiconductor structure is shown in Figures lb, 2b, 3c, 4c.
  • FIG. 5-12 illustrate schematic diagrams of semiconductor structures for fabricating various stages of a stress-enhanced MSOFET in accordance with an embodiment of the method of the present invention, wherein semiconductor structures are shown along the channel region in Figures 5-6, 7a, 8a, 9-12 A cross-sectional view in the longitudinal direction, and a top view of the semiconductor structure is shown in Figures 7b, 8b. detailed description
  • semiconductor structure refers to the general term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed;
  • longitudinal direction of the channel region refers to the source region to The drain region and the direction, or the opposite direction;
  • transverse direction of the channel region is a direction perpendicular to the longitudinal direction of the channel region in a plane parallel to the main surface of the semiconductor substrate.
  • the longitudinal direction of the channel region is generally along the ⁇ 110> direction of the silicon wafer, and the lateral direction of the channel region is generally along the ⁇ 011> direction of the silicon wafer.
  • the semiconductor material includes, for example, a group III-V semiconductor such as GaAs, InP, GaN, SiC, and a Group IV semiconductor such as Si, Ge.
  • the gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaTbN.
  • the gate dielectric may be composed of 510 2 or a material having a dielectric constant greater than SiO 2 , and includes, for example, an oxide, a nitride, an oxynitride, a silicate, an aluminate, a titanate, wherein the oxide includes, for example, Si0 2 .
  • nitrides include Si, silicates such as including Hf Si0x, e.g. aluminates including LaA10 3, titanates include, for example SrTi0 3, oxynitrides
  • SiON is included.
  • the gate dielectric may be formed not only by materials well known to those skilled in the art, but also materials developed for the gate dielectric in the future.
  • the following steps shown in Figures 5 through 12 are performed to fabricate a stress-enhanced MS0FET, in which cross-sectional views of semiconductor structures at different stages are shown. If necessary, a top view is also shown in the drawing, in which the line AA is used to indicate the intercepting position in the longitudinal direction of the channel region.
  • the method begins with the semiconductor structure shown in FIG. 5, in which a pad oxide layer 202 and a pad nitride layer 203 are sequentially formed on the semiconductor substrate 201.
  • the semiconductor substrate 201 is composed of, for example, Si.
  • the pad oxide layer 202 is composed, for example, of silicon oxide and has a thickness of about 2 to 5 nm.
  • the pad nitride layer 203 is composed, for example, of silicon nitride and has a thickness of about 10 to 50 nm.
  • the pad oxide layer 202 can alleviate stress between the semiconductor substrate 201 and the pad nitride layer 203.
  • the substrate nitride layer 205 is used as a hard mask in the subsequent etching step. Processes for forming the various layers described above are known.
  • the pad oxide layer 202 is formed by thermal oxidation.
  • the pad nitride layer 203 is formed by chemical vapor deposition.
  • a photoresist layer (not shown) is formed on the pad nitride layer 203 by spin coating, and the photoresist layer is formed into a shallow trench isolation by a photolithography process including exposure and development therein. pattern.
  • a photoresist layer as a mask, by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution therein, sequentially removing from top to bottom Pad nitride layer 203 and exposed portions of pad oxide layer 202.
  • the photoresist layer is removed by dissolving or ashing in a solvent.
  • the semiconductor substrate 201 is etched to a desired depth by a known dry etching or wet etching using the pad nitride layer 203 and the pad oxide layer 202 as a hard mask, thereby being in the semiconductor substrate 201.
  • a shallow groove is formed as shown in FIG. As will be appreciated by those skilled in the art, the shallow trench surrounds the active region of the MOSFET.
  • a photoresist layer PR1 is formed on the pad nitride layer 203 by spin coating, and the photoresist layer PR1 is patterned by a photolithography process so as to be in the longitudinal direction of the channel region to be formed.
  • One sidewall of the active region is exposed through the shallow trench.
  • a first sidewall of the exposed region of the active region is ion implanted via a shallow trench to form a heavily doped region 204-1, as shown in Figures 7a and 7b. .
  • the first ion implantation is inclined by a predetermined angle with respect to the vertical direction.
  • the dopant for the first ion implantation is, for example, BF2 or B
  • the implantation energy is less than lkeV
  • the implantation dose is greater than 5 ⁇ 10 14 cm ⁇ 2 , so that the peak doping level of the heavily doped region 204-1 is greater than 7 X 10 19 cm- 3 .
  • the photoresist layer PR1 is removed by dissolving or ashing in a solvent.
  • a photoresist layer PR2 is formed on the pad nitride layer 203 by spin coating, and the photoresist layer PR2 is patterned by a photolithography process so as to be in the longitudinal direction of the channel region to be formed.
  • the other sidewall of the active region is exposed through the shallow trench.
  • a second ion implantation is performed on the exposed other sidewall of the active region via the shallow trench to form a heavily doped region 204-2, as shown in FIGS. 8a and 8b. Show.
  • the second ion implantation is inclined by a predetermined angle with respect to the vertical direction.
  • the process conditions for the second ion implantation are the same as for the first ion implantation.
  • the photoresist layer PR2 is removed by dissolving or ashing in a solvent.
  • a layer of insulating material (not shown) is formed on the surface of the semiconductor structure by a known deposition process.
  • the layer of insulating material fills the shallow trench.
  • the portion of the insulating material layer outside the shallow trench is removed by chemical mechanical polishing (CMP), and the pad nitride layer 203 and the pad oxide layer 202 are further removed.
  • CMP chemical mechanical polishing
  • the portion of the insulating material layer remaining in the shallow trench forms a shallow trench isolation 205, as shown in FIG.
  • shallow trench isolation 205 defines the active region of the MOSFET.
  • a dielectric layer and a polysilicon layer are sequentially formed on the surface of the semiconductor structure by a known deposition process, which is patterned to form a gate stack including the gate dielectric 206 and the gate conductor 207.
  • a nitride layer 208 of, for example, 10-50 nm is deposited on the entire surface of the semiconductor structure by the above-described known process, and then the sidewalls and caps surrounding the gate stack are formed by anisotropic etching, as shown in FIG. Show.
  • the shallow trench isolation 205, the heavily doped regions 204-1 and 204-2, and the nitride layer 208 are used as hard masks to etch the semiconductor substrate 201 to a desired concentration, thereby corresponding to the source region on the semiconductor substrate 201.
  • An opening is formed at the position of the drain region as shown in FIG.
  • the etch is anisotropic or isotropic, however, due to the etch selectivity, the heavily doped regions 204-1 and 204-2 are substantially unetched.
  • the etchant used in the etching may be a solution of Tetramethylammonium hydroxide (abbreviated as TMAH) or potassium hydroxide (KOH).
  • the semiconductor layer 209 is epitaxially grown. It should be noted that this opening is not necessarily shown in FIG. 11.
  • the sidewall of the opening on the gate stack and the side walls and the cap 208 may be a " ⁇ " type sidewall formed by wet etching. , the sidewall facet index is U 1 1 ⁇ .
  • the semiconductor layer 209 grows from the bottom surface and the side walls of the opening of the semiconductor substrate 201, and is selective. That is, the growth rates of the semiconductor layers 209 on different crystal faces of the semiconductor substrate 201 are different.
  • the semiconductor layer 209 grows the slowest on the ⁇ 1 1 1 ⁇ crystal plane of the semiconductor substrate 201.
  • the bottom surface and the side walls of the opening in the semiconductor substrate 201 are each composed of a semiconductor material.
  • the heavily doped regions 204-1 and 204-2 serve as a part of the sidewall of the opening, and although exhibiting selectivity with respect to the semiconductor substrate 201 in the etching step, crystallographic properties and the semiconductor substrate are grown when the semiconductor layer 209 is epitaxially grown.
  • 201 is similar and thus also acts as a growing seed layer. As a result, the semiconductor layer 209 can completely fill the opening of the semiconductor substrate 201.
  • the semiconductor layer 209 After completely filling the opening, the semiconductor layer 209 loses the growth seed layer of the open sidewall and continues to freely grow.
  • the continuation growth portion of the semiconductor layer 209 includes not only the (100) main surface parallel to the surface of the semiconductor substrate 201 but also the ⁇ 1 1 1 ⁇ facet at a position adjacent to the nitride layer 208 and the side wall 208. , as shown in Figure 12.
  • the ⁇ 1 1 1 ⁇ facet of the semiconductor layer 209 is only located in its continued growth portion.
  • the semiconductor layer 209 is located The portion within the opening of the semiconductor substrate 201 has a constrained bottom surface and sidewalls. Therefore, the facets of the semiconductor layer 209 do not adversely affect the stress applied to the channel region.
  • the semiconductor layer 209 is ion-implanted according to a conventional process, and then, for example, a spike anneal is performed at a temperature of about 1000 to 1080 ° C to activate.
  • a spike anneal is performed at a temperature of about 1000 to 1080 ° C to activate.
  • the dopants implanted by the previous implantation step and the damage caused by the implantation are eliminated, thereby forming source and drain regions.
  • a portion of the semiconductor substrate below the gate dielectric 206 and between the source and drain regions serves as a channel region.
  • silicidation is performed on the surface of the semiconductor layer 209 to form a metal silicide layer to reduce the contact resistance of the source and drain regions.
  • Ni has a thickness of about 5 to 12 nm, and then heat-treated at a temperature of 300 to 500 ° C for 1 to 10 seconds to form a surface portion of the semiconductor layer 209 to form NiSi, and finally, unreacted by wet etching.
  • Ni is first deposited, and then heat-treated at a temperature of 300 to 500 ° C for 1 to 10 seconds to form a surface portion of the semiconductor layer 209 to form NiSi, and finally, unreacted by wet etching.
  • This silicidation consumes a portion of the semiconductor material of the semiconductor layer 209. Due to the presence of the small facets of the semiconductor layer 209 , silicidation can be performed along the small facets. Since the semiconductor layer 209 completely fills the opening of the semiconductor substrate 201, silicidation does not reach the semiconductor substrate 201.
  • an interlayer insulating layer, a via hole in the interlayer insulating layer, a wiring or an electrode on the upper surface of the interlayer insulating layer are formed on the resultant semiconductor structure, thereby completing other portions of the MOSFET. .
  • the present invention is equally applicable to stress-enhanced n-type MOSFETs.
  • the semiconductor substrate 201 is composed of, for example, Si
  • the semiconductor layer 209 is composed of, for example, Si: C for forming a source region and a drain region, and applying a pull to the channel region as a longitudinal direction along the channel region. Stress source of stress.
  • a stress-enhanced n-type MOSFET can be fabricated in a manner similar to that described above.

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Abstract

公开了一种制造MOSFET的方法，包括：在半导体衬底（201）中形成浅沟槽，该浅沟槽围绕有源区；经由浅沟槽对有源区的一个侧壁进行第一次离子注入，以在所述一个侧壁中形成第一重掺杂区；经由浅沟槽对有源区的相对的另一个侧壁进行第二次离子注入，以在所述另一个侧壁中形成第二重掺杂区；采用绝缘材料填充浅沟槽，以形成用于限定MOSFET的有源区的浅沟槽隔离（205）；在半导体衬底（201）上形成栅叠层（206、207）和绝缘层（208），该绝缘层（208）作为围绕栅叠层（206、207）的侧墙和覆盖栅叠层（206、207）的帽盖；以浅沟槽隔离（205）、第一重掺杂区（204-1）、第二重掺杂区（204-2）和绝缘层（208）作为硬掩膜在半导体衬底（201）中形成开口；以开口的底面和侧壁为生长籽层，外延生长半导体层；以及对半导体层进行离子注入以形成源区（209）和漏区（209）。

Description

MOSFET的制造方法 本申请要求了 2012年 10月 23日提交的、 申请号为 201210407135. 0、 发明名称 为 "MOSFET的制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。 技术领域
本发明涉及半导体器件的制造方法， 更具体地， 涉及应力增强的 MOSFET的制造 方法。 背景技术
集成电路技术的一个重要发展方向是金属氧化物半导体场效应晶体管 （MOSFET) 的尺寸按比例缩小， 以提高集成度和降低制造成本。 然而， 在 MOSFET的尺寸减小时， 半导体材料的性能 （例如迁移率） 以及 MOSFET 自身的器件性能 （例如阈值电压） 均 可能变劣。
通过向 MOSFET的沟道区施加合适的应力， 可以提高载流子的迁移率， 从而减小 导通电阻并提高器件的开关速度。 当形成的器件是 n型 MOSFET时， 应当沿着沟道区 的纵向方向对沟道区施加拉应力， 并且沿着沟道区的横向方向对沟道区施加压应力， 以提高作为载流子的电子的迁移率。 相反， 当晶体管是 P型 MOSFET时， 应当沿着沟 道区的纵向方向对沟道区压应力， 并且沿着沟道区的横向方向对沟道区施加拉应力， 以提高作为载流子的空穴的迁移率。
采用与半导体衬底的材料不同的半导体材料形成源区和漏区，可以产生期望的应 力。对于 n型 M0SFET, 在 Si衬底上形成的 Si： C源区和漏区可以作为应力源， 沿着沟 道区的纵向方向对沟道区施加拉应力。 对于 P型 M0SFET, 在 Si衬底上形成的 SiGe 源区和漏区可以作为应力源， 沿着沟道区的纵向方向对沟道区施加压应力。
图 1-4示出根据现有技术的方法制造应力增强的 MS0FET的各个阶段的半导体结 构的示意图， 其中在图 la、 2a、 3a、 4a中示出了半导体结构沿沟道区的纵向方向的 截面图， 在图 3b、 4b中示出了半导体结构沿沟道区的横向方向的截面图， 在图 lb、 2b、 3c、 4c中示出了半导体结构的俯视图。 在图中， 线 AA表示沿沟道区的纵向方向 的截取位置， 线 BB表示沿沟道区的横向方向的截取位置。 该方法开始于图 la和 lb所示的半导体结构， 其中， 在半导体衬底 101中形成浅 沟槽隔离 102以限定 M0SFET的有源区， 在半导体衬底 101上形成由侧墙 105包围的 栅叠层， 栅叠层包括栅极电介质 103和栅极导体 104。
以浅沟槽隔离 102、栅极导体 104和侧墙 105作为硬掩模， 蚀刻半导体衬底 101， 达到期望的深度，从而在半导体衬底 101对应于源区和漏区的位置形成开口，如图 2a 和 2b所示。
在半导体衬底 101的位于开口内的暴露表面上， 外延生长半导体层 106， 以形成 源区和漏区。半导体衬底 101的位于栅极电介质 103下方以及源区和漏区之间的一部 分将作为沟道区。
半导体层 106从半导体衬底 101的表面开始生长， 并且是选择性的。 也即， 半导 体层 106在半导体衬底 101的不同晶面 （crystal l ine surface ) 上的生长速率不同。 在半导体衬底 101由 Si组成、 以及半导体层 106由 Ge的原子百分比约为 10-15%的 SiGe组成的示例中， 半导体层 106在半导体衬底 101的 {1 1 1}晶面上生长最慢。 结 果， 所形成的半导体层 106不仅包括与半导体衬底 101的表面平行的 （100 )主表面， 而且在与浅沟槽隔离 102和侧墙 105相邻的位置还包括 {1 1 1}刻面 （facet ), 这称 为半导体层 106生长的边缘效应 （edge effect ), 如图 3a、 3b和 3c所示。
然而， 半导体层 106的小刻面是不期望的， 因为这导致其自由表面的增加， 使得 半导体层 106中的应力得以释放， 从而减小对沟道区施加的应力。
进一步地， 在半导体层 106的表面进行硅化以形成金属硅化物层 107， 如图 4a、 4b和 4c所示。 该硅化消耗半导体层 106的一部分半导体材料。 由于半导体层 106的 小刻面的存在， 硅化可以沿着小刻面进行， 最终可能到达半导体衬底 101。
然而，半导体衬底 101中的硅化是不期望的，因为这可能在结区形成金属硅化物， 导致结泄漏的增加。
因此， 期望在应力增强的 M0SFET抑制用于形成源区和漏区的半导体层的边缘效 应。 发明内容
本发明的目的是提供一种提高沟道区应力和 /或减小结泄漏的 M0SFET 的制造方 法。
根据本发明， 提供一种制造 M0SFET的方法， 包括： 在半导体衬底中形成浅沟槽， 该浅沟槽围绕有源区； 经由浅沟槽对有源区的一个侧壁进行第一次离子注入， 以在所 述一个侧壁中形成第一重掺杂区；经由浅沟槽对有源区的相对的另一个侧壁进行第二 次离子注入， 以在所述一个侧壁中形成第二重掺杂区； 采用绝缘材料填充浅沟槽， 以 形成用于限定 M0SFET的有源区的浅沟槽隔离；在半导体衬底上形成栅叠层和绝缘层， 该绝缘层作为围绕栅叠层的侧墙和覆盖栅叠层的帽盖；以浅沟槽隔离、第一重掺杂区、 第二重掺杂区和绝缘层作为硬掩模在半导体衬底中形成开口； 以开口的底面和侧壁为 生长籽层， 外延生长半导体层； 以及对半导体层进行离子注入以形成源区和漏区。
该方法利用由半导体层形成的源区和漏区对半导体衬底中的沟道区施加应力。由 于在外延生长时以开口的底面和侧壁为生长籽层， 因此半导体层可以完全填充半导体 衬底中的开口。 半导体层的 U 1 1}刻面仅仅位于其继续生长部分中， 从而抑制了边 缘效应的影响。 附图说明
图 1-4示出根据现有技术的方法制造应力增强的 MS0FET的各个阶段的半导体结 构的示意图， 其中在图 la、 2a、 3a、 4a中示出了半导体结构沿沟道区的纵向方向的 截面图， 在图 3b、 4b中示出了半导体结构沿沟道区的横向方向的截面图， 在图 lb、 2b、 3c、 4c中示出了半导体结构的俯视图。
图 5-12示出根据本发明的方法的实施例制造应力增强的 MS0FET的各个阶段的半 导体结构的示意图， 其中在图 5-6、 7a、 8a、 9_12中示出了半导体结构沿沟道区的纵 向方向的截面图， 在图 7b、 8b中示出了半导体结构的俯视图。 具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中， 相同的元件采用类似的附 图标记来表示。 为了清楚起见， 附图中的各个部分没有按比例绘制。
为了简明起见， 可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解， 在描述器件的结构时， 当将一层、 一个区域称为位于另一层、 另一个 区域 "上面"或 "上方" 时， 可以指直接位于另一层、 另一个区域上面， 或者在其与 另一层、 另一个区域之间还包含其它的层或区域。 并且， 如果将器件翻转， 该一层、 一个区域将位于另一层、 另一个区域 "下面"或 "下方" 。
如果为了描述直接位于另一层、 另一个区域上面的情形， 本文将采用 "直接 在……上面"或 "在……上面并与之邻接" 的表述方式。
在本申请中，术语 "半导体结构"指在制造半导体器件的各个步骤中形成的整个 半导体结构的统称， 包括已经形成的所有层或区域； 术语 "沟道区的纵向方向"指从 源区到漏区和方向， 或相反的方向； 术语 "沟道区的横向方向"在与半导体衬底的主 表面平行的平面内与沟道区的纵向方向垂直的方向。 例如， 对于在 U 0 0}硅晶片上 形成的 M0SFET, 沟道区的纵向方向通常沿着硅晶片的〈110〉方向， 沟道区的横向方向 通常沿着硅晶片的〈011〉方向。
在下文中描述了本发明的许多特定的细节， 例如器件的结构、 材料、 尺寸、 处理 工艺和技术， 以便更清楚地理解本发明。 但正如本领域的技术人员能够理解的那样， 可以不按照这些特定的细节来实现本发明。
除非在下文中特别指出， M0SFET的各个部分可以由本领域的技术人员公知的材料 构成。 半导体材料例如包括 III-V族半导体， 如 GaAs、 InP、 GaN、 SiC， 以及 IV族半 导体， 如 Si、 Ge。 栅极导体可以由能够导电的各种材料形成， 例如金属层、 掺杂多晶 硅层、 或包括金属层和掺杂多晶硅层的叠层栅极导体或者是其他导电材料， 例如为 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax, MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx 和所述各 种导电材料的组合。栅极电介质可以由 5102或介电常数大于 Si02的材料构成，例如包 括氧化物、氮化物、氧氮化物、硅酸盐、铝酸盐、钛酸盐，其中，氧化物例如包括 Si02、 Hf02 Zr02、 A1203、 Ti02、 L¾03, 氮化物例如包括 Si ， 硅酸盐例如包括 Hf Si0x， 铝酸 盐例如包括 LaA103， 钛酸盐例如包括 SrTi03， 氧氮化物例如包括 SiON。 并且， 栅极电 介质不仅可以由本领域的技术人员公知的材料形成，也可以采用将来开发的用于栅极 电介质的材料。
按照本发明的实施例， 执行图 5 至 12 中所示的以下步骤以制造应力增强的 MS0FET, 在图中示出了不同阶段的半导体结构的截面图。 如果必要， 在图中还示出了 俯视图， 在俯视图中采用线 AA表示沿沟道区的纵向方向的截取位置。
该方法开始于图 5所示的半导体结构，在半导体衬底 201上依次形成衬垫氧化物 层 202和衬垫氮化物层 203。半导体衬底 201例如由 Si组成。衬垫氧化物层 202例如 由氧化硅组成， 厚度约为 2-5nm。 衬垫氮化物层 203 例如由氮化硅组成， 厚度约为 10-50nm。 正如已知的那样， 衬垫氧化物层 202可以减轻半导体衬底 201和衬垫氮化 物层 203之间的应力。 衬底氮化物层 205在随后的蚀刻步骤中用作硬掩模。 用于形成上述各层的工艺是已知的。 例如， 通过热氧化形成衬垫氧化物层 202。 例如， 通过化学气相沉积形成衬垫氮化物层 203。
然后， 通过旋涂在衬垫氮化物层 203上形成光致抗蚀剂层 （未示出）， 并通过其 中包括曝光和显影的光刻工艺将光致抗蚀剂层形成浅沟槽隔离的图案。利用光致抗蚀 剂层作为掩模， 通过干法蚀刻， 如离子铣蚀刻、 等离子蚀刻、 反应离子蚀刻、 激光烧 蚀， 或者通过其中使用蚀刻剂溶液的湿法蚀刻， 从上至下依次去除衬垫氮化物层 203 和衬垫氧化物层 202的暴露部分。 该蚀刻在半导体衬底 201的表面停止， 并且在衬垫 氮化物层 203和衬垫氧化物层 202形成浅沟槽隔离的图案。通过在溶剂中溶解或灰化 去除光致抗蚀剂层。
利用衬垫氮化物层 203和衬垫氧化物层 202—起作为硬掩模，通过已知的干法蚀 刻或湿法蚀刻， 蚀刻半导体衬底 201达期望的深度， 从而在半导体衬底 201中形成浅 沟槽， 如图 6所示。 正如本领域的技术人员可以理解的那样， 该浅沟槽围绕 M0SFET 的有源区。
然后， 通过旋涂在衬垫氮化物层 203上形成光致抗蚀剂层 PR1， 并通过光刻工艺 将光致抗蚀剂层 PR1形成图案，从而在将要形成的沟道区的纵向方向上经由浅沟槽暴 露有源区的一个侧壁。 以光致抗蚀剂层 PR1作为掩模， 经由浅沟槽对有源区的暴露的 一个侧壁进行第一次离子注入， 以形成重掺杂区 204-1， 如图 7a和 7b所示。 为了在 有源区的暴露的一个侧壁 （图中的左侧的侧壁） 上形成重掺杂区 204-1， 第一次离子 注入相对于垂直方向倾斜预定的角度。在一个示例中， 第一次离子注入的掺杂剂例如 是 BF2或 B， 注入能量小于 lkeV， 注入剂量大于 5 X 1014 cm— 2， 使得重掺杂区 204-1 的峰值掺杂水平大于 7 X 1019 cm— 3。然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层 PR1。
然后， 通过旋涂在衬垫氮化物层 203上形成光致抗蚀剂层 PR2， 并通过光刻工艺 将光致抗蚀剂层 PR2形成图案，从而在将要形成的沟道区的纵向方向上经由浅沟槽暴 露有源区的另一个侧壁。 以光致抗蚀剂层 PR2作为掩模， 经由浅沟槽对有源区的暴露 的另一个侧壁进行第二次离子注入， 以形成重掺杂区 204-2， 如图 8a和 8b所示。 为 了在有源区的暴露的另一个侧壁 （图中的右侧的侧壁） 上形成重掺杂区 204-2， 第二 次离子注入相对于垂直方向倾斜预定的角度。第二次离子注入的工艺条件与第一次离 子注入相同。 然后， 通过在溶剂中溶解或灰化去除光致抗蚀剂层 PR2。
然后， 通过已知的沉积工艺， 在半导体结构的表面上形成绝缘材料层 （未示出）。 该绝缘材料层填充浅沟槽。 通过化学机械抛光 （CMP) 去除绝缘材料层位于浅沟槽外 部的部分， 并且进一步去除衬垫氮化物层 203和衬垫氧化物层 202。 绝缘材料层留在 浅沟槽内的部分形成浅沟槽隔离 205， 如图 9所示。 正如本领域的技术人员可以理解 的那样， 浅沟槽隔离 205限定 M0SFET的有源区。
然后， 通过已知的沉积工艺， 在半导体结构的表面上依次形成电介质层以及多晶 硅层， 对其进行图案化， 从而形成包括栅极电介质 206和栅极导体 207的栅极叠层。 接着， 通过上述已知的工艺， 在半导体结构的整个表面上沉积例如 10-50纳米的氮化 物层 208， 然后通过各向异性蚀刻形成包围栅叠层的侧墙和帽盖， 如图 10所示。
然后， 以浅沟槽隔离 205、 重掺杂区 204-1和 204-2、 氮化物层 208作为硬掩模， 蚀刻半导体衬底 201， 达到期望的浓度， 从而在半导体衬底 201对应于源区和漏区的 位置形成开口， 如图 11所示。 该蚀刻是各向异性或各向性的， 然而， 由于蚀刻的选 择性， 重掺杂区 204-1和 204-2基本上未受到蚀刻。 例如， 在该蚀刻中采用的蚀刻剂 可以是四甲基氢氧化铵 （Tetramethylammonium hydroxide, 缩写为 TMAH) 或氢氧化 钾 （K0H) 等溶液。
然后， 在半导体衬底 201的开口内， 外延生长半导体层 209。 需要注意的是， 这 个开口并不一定如图 11所示， 例如该开口位于栅极叠层以及侧墙和帽盖 208的两侧 的侧壁可能是湿法腐蚀形成的 "∑"型侧壁， 侧壁晶面指数为 U 1 1}。 半导体层 209 从半导体衬底 201的开口的底面和侧壁开始生长， 并且是选择性的。 也即， 半导体层 209在半导体衬底 201的不同晶面上的生长速率不同。 在半导体衬底 201由 Si组成、 以及半导体层 209由 SiGe组成的 p型 M0SFET的示例中，半导体层 209在半导体衬底 201的 {1 1 1}晶面上生长最慢。 然而， 与现有技术不同， 半导体衬底 201中的开口的 底面和侧壁均由半导体材料组成。重掺杂区 204-1和 204-2作为开口的侧壁的一部分， 虽然在蚀刻步骤中相对于半导体衬底 201表现出选择性， 但在外延生长半导体层 209 时晶体学特性与半导体衬底 201相似， 因而也作为生长籽层。 结果， 半导体层 209可 以完全填充半导体衬底 201的开口。
在完全填充该开口之后， 半导体层 209失去开口侧壁的生长籽层， 并继续自由外 延生长。 结果， 半导体层 209的继续生长部分不仅包括与半导体衬底 201的表面平行 的 （100 )主表面， 而且在与氮化物层 208和侧墙 208相邻的位置还包括 {1 1 1}刻面， 如图 12所示。
半导体层 209的 {1 1 1}刻面仅仅位于其继续生长部分中。 半导体层 209的位于 半导体衬底 201的开口内的部分具有受约束的底面和侧壁。 因此， 半导体层 209的刻 面并未不利地影响对沟道区施加的应力。
尽管未示出， 在图 5-12所示的步骤之后， 按照常规的工艺对半导体层 209进行 离子注入， 然后例如在约 1000-1080°C的温度下执行尖峰退火（spike anneal ), 以激 活通过先前的注入步骤而注入的掺杂剂并消除注入导致的损伤， 从而形成源区和漏 区。半导体衬底的位于栅极电介质 206下方以及源区和漏区之间的一部分作为沟道区。
优选地， 在半导体层 209的表面进行硅化以形成金属硅化物层， 以减小源区和漏 区的接触电阻。
该硅化的工艺是已知的。 例如， 首先沉积厚度约为 5-12nm 的 Ni 层， 然后在 300-500°C的温度下热处理 1-10秒钟，使得半导体层 209的表面部分形成 NiSi，最后 利用湿法蚀刻去除未反应的 Ni。
该硅化消耗半导体层 209的一部分半导体材料。由于半导体层 209的小刻面的存 在， 硅化可以沿着小刻面进行。 由于半导体层 209完全填充半导体衬底 201的开口， 硅化并未到达半导体衬底 201。
在图 12所示的步骤之后， 在所得到的半导体结构上形成层间绝缘层、 位于层间 绝缘层中的通孔、 位于层间绝缘层上表面的布线或电极， 从而完成 M0SFET的其他部 分。
尽管在上述实施例中描述了应力增强的 P型 M0SFET及其中使用的应力源的材料， 但本发明同样适应于应力增强的 n型 M0SFET。 在 n型 M0SFET中， 半导体衬底 201例 如由 Si组成， 半导体层 209例如由 Si : C组成， 用于形成源区和漏区， 并且作为沿着 沟道区的纵向方向对沟道区施加拉应力的应力源。 除了应力源的材料不同之外， 可以 采用与上述方法类似的方法制造应力增强的 n型 M0SFET。
以上描述只是为了示例说明和描述本发明， 而非意图穷举和限制本发明。 因此， 本发明不局限于所描述的实施例。对于本领域的技术人员明显可知的变型或更改， 均 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种制造 M0SFET的方法， 包括：
在半导体衬底中形成浅沟槽， 该浅沟槽围绕有源区；
经由浅沟槽对有源区的一个侧壁进行第一次离子注入， 以在所述一个侧壁中形成 第一重掺杂区；
经由浅沟槽对有源区的相对的另一个侧壁进行第二次离子注入， 以在所述一个侧 壁中形成第二重掺杂区；
采用绝缘材料填充浅沟槽， 以形成用于限定 M0SFET的有源区的浅沟槽隔离； 在半导体衬底上形成栅叠层和绝缘层，该绝缘层作为围绕栅叠层的侧墙和覆盖栅 叠层的帽盖；
以浅沟槽隔离、第一重掺杂区、第二重掺杂区和绝缘层作为硬掩模在半导体衬底 中形成开口；
以开口的底面和侧壁为生长籽层， 外延生长半导体层； 以及
对半导体层进行离子注入以形成源区和漏区。
2、 根据权利要求 1所述的方法， 其中形成浅沟槽的步骤包括：
在半导体衬底上形成包括浅沟槽隔离的图案的第一硬掩模； 以及
蚀刻半导体衬底以形成浅沟槽。
3、 根据权利要求 2所述的方法， 其中所述第一硬掩模包括位于半导体衬底上的 衬垫氧化物层和位于衬垫氧化物层上的衬垫氮化物层。
4、 根据权利要求 1所述的方法， 其中第一次离子注入包括：
形成第一光致抗蚀剂掩模， 该第一光致抗蚀剂掩模遮挡有源区的所述另一个侧 壁， 并暴露有源区的所述一个侧壁；
经由浅沟槽隔离对有源区的暴露的所述一个侧壁进行第一次离子注入； 以及 去除第一光致抗蚀剂掩模。
5、 根据权利要求 1所述的方法， 其中第二次离子注入包括：
形成第二光致抗蚀剂掩模， 该第二光致抗蚀剂掩模遮挡有源区的所述一个侧壁， 并暴露有源区的所述另一个侧壁；
经由浅沟槽隔离对有源区的暴露的所述另一个侧壁进行第二次离子注入； 以及 去除第二光致抗蚀剂掩模。
6、 根据权利要求 1所述的方法， 其中第一次离子注入和第二次离子注入的掺杂 剂是选自 BF2和 B中的至少一种。
7、 根据权利要求 1所述的方法， 其中第一次离子注入和第二次离子注入相对于 垂直方向倾斜预定的角度。
8、 根据权利要求 1所述的方法， 其中所述 M0SFET为 p型 M0SFET。
9、 根据权利要求 8所述的方法， 其中所述半导体衬底由 Si组成， 所述半导体层 由 SiGe组成。
10、 根据权利要求 1所述的方法， 其中所述 M0SFET为 n型 M0SFET。
11、 根据权利要求 10所述的方法， 其中所述半导体衬底由 Si组成， 所述半导体 层由 Si : C组成。
12、 根据权利要求 1所述的方法， 其中在形成源区和漏区之后中， 还包括： 执行硅化以在源区和漏区的表面形成金属硅化物。
PCT/CN2012/083749 2012-10-23 2012-10-30 Mosfet的制造方法 Ceased WO2014063380A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035061A1 (en) * 2013-07-31 2015-02-05 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3012258A1 (fr) * 2013-10-23 2015-04-24 St Microelectronics Crolles 2 Procede de realisation de transistors nmos et pmos sur un substrat du type soi, en particulier fdsoi, et circuit integre correspondant
CN104752513B (zh) * 2015-03-12 2017-11-21 西安电子科技大学 一种制备基于65nm工艺的冗余掺杂抗辐照MOS场效应管的方法
CN106409919A (zh) * 2015-07-30 2017-02-15 株式会社半导体能源研究所 半导体装置以及包括该半导体装置的显示装置
US10790391B2 (en) 2018-06-27 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain epitaxial layer profile
CN114068317A (zh) * 2020-08-06 2022-02-18 上海华力集成电路制造有限公司 栅氧的形成方法
US12027368B2 (en) * 2021-04-23 2024-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating semiconductor device
CN118658872B (zh) * 2024-08-19 2024-11-29 合肥晶合集成电路股份有限公司 半导体器件及其版图结构

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150037A1 (en) * 2006-12-24 2008-06-26 Chartered Semiconductor Manufacturing, Ltd Selective STI Stress Relaxation Through Ion Implantation
US20090267149A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Source/drain junction for high performance mosfet formed by selective epi process
CN102623487A (zh) * 2011-01-26 2012-08-01 中国科学院微电子研究所 半导体器件及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6649461B1 (en) * 2002-04-25 2003-11-18 Chartered Semiconductor Manufacturing Ltd. Method of angle implant to improve transistor reverse narrow width effect
KR100568858B1 (ko) * 2003-07-24 2006-04-10 삼성전자주식회사 수직 이중 채널을 갖는 ｓｏｉ 트랜지스터의 제조 방법 및그에 따른 구조
KR100525960B1 (ko) * 2004-02-05 2005-11-02 삼성전자주식회사 반도체 소자 형성방법
US7569434B2 (en) * 2006-01-19 2009-08-04 International Business Machines Corporation PFETs and methods of manufacturing the same
US20090174002A1 (en) * 2008-01-09 2009-07-09 International Business Machines Corporation Mosfet having a high stress in the channel region
KR20090096885A (ko) * 2008-03-10 2009-09-15 삼성전자주식회사 국부적 매립 절연막을 구비하는 반도체 장치 및 그 제조방법
US20100075477A1 (en) * 2008-09-22 2010-03-25 Hynix Semiconductor Inc. Method of Manufacturing Semiconductor Device
JP2010171144A (ja) * 2009-01-21 2010-08-05 Toshiba Corp 半導体装置
DE102009006884B4 (de) * 2009-01-30 2011-06-30 Advanced Micro Devices, Inc., Calif. Verfahren zur Herstellung eines Transistorbauelementes mit In-Situ erzeugten Drain- und Source-Gebieten mit einer verformungsinduzierenden Legierung und einem graduell variierenden Dotierstoffprofil und entsprechendes Transistorbauelement
JP5341994B2 (ja) * 2009-06-26 2013-11-13 株式会社東芝 半導体装置の製造方法
CN102034865B (zh) * 2009-09-30 2012-07-04 中国科学院微电子研究所 半导体器件及其制造方法
US8236659B2 (en) * 2010-06-16 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Source and drain feature profile for improving device performance and method of manufacturing same
US8933512B2 (en) * 2010-12-03 2015-01-13 Institute of Microelectronics, Chinese Academy of Science MOSFET and method for manufacturing the same
DE102011003439B4 (de) * 2011-02-01 2014-03-06 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Durchlassstromerhöhung in Feldeffekttransistoren durch asymmetrische Konzentrationsprofile von Legierungssubstanzen einer Kanalhalbleiterlegierung und Halbleiterbauelement
US9633854B2 (en) * 2011-06-23 2017-04-25 Institute of Microelectronics, Chinese Academy of Sciences MOSFET and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080150037A1 (en) * 2006-12-24 2008-06-26 Chartered Semiconductor Manufacturing, Ltd Selective STI Stress Relaxation Through Ion Implantation
US20090267149A1 (en) * 2008-04-24 2009-10-29 International Business Machines Corporation Source/drain junction for high performance mosfet formed by selective epi process
CN102623487A (zh) * 2011-01-26 2012-08-01 中国科学院微电子研究所 半导体器件及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035061A1 (en) * 2013-07-31 2015-02-05 Samsung Electronics Co., Ltd. Semiconductor Device and Method for Fabricating the Same

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