CN114068317A - 栅氧的形成方法 - Google Patents

栅氧的形成方法 Download PDF

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CN114068317A
CN114068317A CN202010780587.8A CN202010780587A CN114068317A CN 114068317 A CN114068317 A CN 114068317A CN 202010780587 A CN202010780587 A CN 202010780587A CN 114068317 A CN114068317 A CN 114068317A
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gate oxide
hard mask
shallow trench
mask layer
forming
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成鑫华
尹俊
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Abstract

本发明公开了一种栅氧的形成方法，包括步骤：步骤一、在半导体衬底表面形成硬质掩膜层，依次对浅沟槽形成区域的硬质掩膜层和半导体衬底进行刻蚀形成浅沟槽；步骤二、进行带倾角离子注入在浅沟槽侧面顶部注入离子形成顶角区；步骤三、在浅沟槽中填充场氧并去除硬质掩膜层；步骤四、进行热氧化在有源区的表面形成栅氧；在栅氧的热氧化过程中，顶角区中注入的离子使顶角区的热氧化速率增加，使栅氧在所述顶角区的表面的厚度增加并从而使栅氧在顶角区的具有圆化形貌。本发明能改善栅氧的形貌，从而能提高器件的击穿电压和可靠性。

Description

栅氧的形成方法
技术领域
本发明涉及一种半导体集成电路制造方法，特别是涉及一种栅氧的形成方法。
背景技术
在半导体集成电路中，半导体器件如CMOS，VDMOS，IGBT等都会采用栅氧，栅氧的顶部会形成栅导电材料层如多晶硅栅，被多晶硅栅所覆盖的阱区作为沟道区，通过在将栅极电压加到所述多晶硅栅之后，所述多晶硅栅会使沟道区的表面反型并形成导电沟道，载流子在导电沟道中流动形成沟道电流。栅氧则作为多晶硅栅和沟道区之间的隔离层，防止沟道区和多晶硅栅之间产生漏电流，所以，栅氧的质量较好时能降低漏电流，提高器件的可靠性。
但是，在通过栅氧控制电压的器件在工艺过程中，经常会出现电荷或热载流子等相关因素导致栅氧的电学参数在测试过程中失效，漏电流增大从而降低可靠性的情况。其中，影响栅氧的电学性能的电荷包括栅氧中的界面态俘获的电荷；热载流子则是在器件导通中经过电场加速的沟道区表面的载流子，通常在漏区电压较大时会对沟道区产生耗尽从而形成较大的电场，电场会使载流子加速形成热载流子，热载流子能量较大时会进入到栅氧或穿过栅氧从而使栅氧的电学性能变差。
为了改进这种状况，也即为了防止栅氧在电荷或热载流子的作用下而导致的电学参数变差这种状况，一种方面，需要提高栅氧本身的品质，降低界面态，减少俘获电荷，提升本征击穿电压。另一方面，改善栅氧的形貌也逐渐的提到日程上来。如何形成符合要求的形貌成为技术关键点。
发明内容
本发明所要解决的技术问题是提供一种栅氧的形成方法，能改善栅氧的形貌，从而能提高器件的击穿电压和可靠性。
为解决上述技术问题，本发明提供的栅氧的形成方法包括如下步骤：
步骤一、在半导体衬底表面形成硬质掩膜层，依次对浅沟槽形成区域的所述硬质掩膜层和所述半导体衬底进行刻蚀形成浅沟槽，有源区由位于所述浅沟槽之间的所述半导体衬底组成，所述有源区表面的所述硬质掩膜层保留。
步骤二、进行带倾角离子注入在所述浅沟槽侧面顶部注入离子形成顶角区，所述顶角区位于所述有源区的外侧边缘。
步骤三、在所述浅沟槽中填充场氧并去除所述硬质掩膜层。
步骤四、进行热氧化在所述有源区的表面形成栅氧；在所述栅氧的热氧化过程中，所述顶角区中注入的离子使所述顶角区的热氧化速率增加，使所述栅氧在所述顶角区的表面的厚度增加并从而使所述栅氧在所述顶角区的具有圆化形貌。
进一步的改进是，所述半导体衬底为硅衬底。
进一步的改进是，所述硬质掩膜层由氮化层组成或者由氧化层和氮化层叠加而成。
进一步的改进是，步骤二中，所述带倾角离子注入的注入能量的最大值要求保证注入的离子不会穿过所述硬质掩膜层到达所述硬质掩膜层底部的所述有源区的表面。
进一步的改进是，所述带倾角离子注入的注入能量为500kev～5kev。
进一步的改进是，步骤二中，所述顶角区的纵向深度由所述硬质掩膜层的厚度、所述浅沟槽的顶部开口宽度以及所述带倾角离子注入的注入角度；所述硬质掩膜层的厚度和所述浅沟槽的顶部开口宽度为固定值，所述带倾角离子注入的注入角度为可设定值，通过设定所述带倾角离子注入的注入角度设定所述顶角区的纵向深度。
进一步的改进是，步骤二中，所述带倾角离子注入的注入总剂量分多次完成。
进一步的改进是，步骤二中，所述带倾角离子注入的注入过程中，所述半导体衬底的法线沿着所述带倾角离子注入的注入方向自转。
进一步的改进是，步骤二中，所述带倾角离子注入的注入离子包括氩离子或氟离子。
进一步的改进是，步骤四中，所述栅氧的热氧化的温度为800℃～1100℃。
进一步的改进是，步骤三中，所述场氧的淀积工艺采用HDPCVD工艺。
进一步的改进是，所述场氧的淀积工艺完成后还包括对所述场氧进行回刻或化学机械研磨，使所述场氧仅填充于所述浅沟槽中。
进一步的改进是，步骤四完成后还包括如下步骤：
形成栅极导电材料层。
对所述栅极导电材料层进行图形化，图形化后的所述栅极导电材料层仅位于栅极结构的形成区域，由所述栅氧和顶部的所述栅极导电材料层叠加而成。
进一步的改进是，所述栅极导电材料层的材料包括多晶硅。
进一步的改进是，采用所述栅氧的半导体器件包括CMOS，VDMOS和IGBT。
针对本发明所要解决的技术问题，本发明在栅氧形成之前预先对半导体衬底进行处理，具体为在浅沟槽形成之后以及在浅沟槽中填充场氧之前，增加了带倾角离子注入，带倾角离子注入能将离子注入到浅沟槽侧面的顶部并形成顶角区而且能调节顶角区的纵向深度，由于有源区是由浅沟槽定义的，有源区的边缘正好位于顶角区，故顶角区中注入的离子能增加栅氧的热氧化工艺中的热氧化速率，从而能增加顶角区表面的栅氧厚度并使栅氧在顶角区的具有圆化形貌。
而现有工艺中，在本发明对应的顶角区中没有注入离子，在栅氧的热氧化工艺中，顶角区表面的热氧化速率会慢于有源区的内部区域表面的热氧化速率且二者相差较大，有源区的内部区域表面为位于顶角区内侧的有源区表面，这样会使顶角区表面的栅氧的厚度和有源区的内部区域表面的栅氧的差异较大，使得顶角区表面的栅氧成为整个有源区表面的栅氧的薄弱环节，从而容易在顶角区表面的栅氧处发生击穿，并降低器件的可靠性。
而本发明通过增加顶角区表面的栅氧厚度后，能使顶角区表面的栅氧厚度和有源区的内部区域表面的栅氧厚度的差异变小且能使顶角区的栅氧更加圆化，能提升在顶角区表面的栅氧处耐压能力，最后能提高整个有源区表面的栅氧的耐压能力，从而能提高器件的击穿电压和可靠性。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是本发明实施例栅氧的形成方法的流程图；
图2A-图2F是本发明实施例方法各步骤中的器件结构图；
图3是本发明实施例方法的步骤二中顶角区的纵向深度和带倾角离子注入的注入角度的关系示意图；
图4A是现有技术中未进行本发明实施例方法的带倾角离子注入时形成的栅氧的照片；
图4B是本发明实施例方法形成的栅氧的照片。
具体实施方式
如图1所示，是本发明实施例栅氧7的形成方法的流程图；如图2A至图2F所示，是本发明实施例方法各步骤中的器件结构图；本发明实施例栅氧7的形成方法包括如下步骤：
步骤一、如图2A所示，在半导体衬底1表面形成硬质掩膜层。
本发明实施例方法中，所述半导体衬底1为硅衬底。
所述硬质掩膜层由氧化层2和氮化层3叠加而成。在其他实施例方法中，也能为：所述硬质掩膜层由氮化层组成。
依次对浅沟槽4形成区域的所述硬质掩膜层和所述半导体衬底1进行刻蚀形成浅沟槽4，有源区由位于所述浅沟槽4之间的所述半导体衬底1组成，所述有源区表面的所述硬质掩膜层保留。
本发明实施例方法中，浅沟槽4的形成区域通过光刻工艺形成的光刻胶图形定义；在刻蚀所述硬质掩膜层之后，去除所述光刻胶图形，之后再以所述硬质掩膜层为掩膜对底部的所述半导体衬底1进行刻蚀形成所述浅沟槽。
步骤二、进行带倾角离子注入在所述浅沟槽4侧面顶部注入离子形成顶角区5，所述顶角区5位于所述有源区的外侧边缘。
本发明实施例中，所述带倾角离子注入的注入能量的最大值要求保证注入的离子不会穿过所述硬质掩膜层到达所述硬质掩膜层底部的所述有源区的表面。较佳为，所述带倾角离子注入的注入能量为500kev～5kev。
所述带倾角离子注入的注入离子包括氩离子或氟离子。
所述带倾角离子注入的注入总剂量分多次完成。所述带倾角离子注入的注入过程中，所述半导体衬底1的法线沿着所述带倾角离子注入的注入方向自转。
如图2B所示，是所述半导体衬底1在一个方向时进行所述带倾角离子注入时的示意图，箭头线201表示所述带倾角离子注入，注入角度为所述带倾角离子注入的注入方向和所述半导体衬底1的法线方向的夹角。在图2B中，所述带倾角离子注入仅能对所述浅沟槽4的一个侧面的顶部进行注入，注入形成的所述顶角区单独用标记5a表示。
如图2C所示，是所述半导体衬底1转动到另一个方向时进行所述带倾角离子注入时的示意图，可以看出，所述带倾角离子注入会对所述浅沟槽4的另一个侧面的顶部进行注入，该次注入形成的所述顶角区单独用标记5b表示。
随着所述半导体衬底1的法线沿着所述带倾角离子注入的注入方向自转并进行分批次的注入，能确保最后形成的各所述浅沟槽4顶部的所述顶角区5的注入剂量均匀，如图2D所示，是完成所述带倾角离子注入时的示意图。
所述顶角区5的纵向深度由所述硬质掩膜层的厚度、所述浅沟槽4的顶部开口宽度以及所述带倾角离子注入的注入角度；所述硬质掩膜层的厚度和所述浅沟槽4的顶部开口宽度为固定值，所述带倾角离子注入的注入角度为可设定值，通过设定所述带倾角离子注入的注入角度设定所述顶角区5的纵向深度。图2D中，d1表示所述硬质掩膜层的厚度。d2表示所述顶角区5的底部处的所述浅沟槽4的宽度，如果所述浅沟槽4的侧面垂直的话，d2等于所述浅沟槽4的顶部开口宽度；如果所述浅沟槽4的侧面倾斜的话，d2也能从所述浅沟槽4的顶部开口宽度得到，通常d2约等于所述浅沟槽4的顶部开口宽度。dx表示表示所述顶角区5的宽度。α表示所述带倾角离子注入的注入角度。
如图3所示，是本发明实施例方法的步骤二中顶角区的纵向深度和带倾角离子注入的注入角度的关系示意图；图2D中对应的d1、d2和dx以及α也在图3中标出，图3中的三角形的斜边对应于所述带倾角离子注入的注入方向，从图3可以得到：tg(α)＝d2/(d1+dx)；
进行变化可以得到：dx＝(d2-d1*tg(α))/tg(α)。
由于上述公式可以看出，d1和d2为固定值，例如d1能取
Figure BDA0002620040200000051
d2能取
Figure BDA0002620040200000052
d1和d2的具体值能根据实际工艺变化，但是一旦设定之后就不再改变，也即在步骤二中不会再改变。但是在步骤二中能调节α，且是通过调节α调节dx。
步骤三、如图2E所示，在所述浅沟槽4中填充场氧6并去除所述硬质掩膜层。
本发明实施例方法中，所述场氧6的淀积工艺采用HDPCVD工艺。
所述场氧6的淀积工艺完成后还包括对所述场氧6进行回刻或化学机械研磨，使所述场氧6仅填充于所述浅沟槽4中。
步骤四、如图2F所示，进行热氧化在所述有源区的表面形成栅氧7；在所述栅氧7的热氧化过程中，所述顶角区5中注入的离子使所述顶角区5的热氧化速率增加，使所述栅氧7在所述顶角区5的表面的厚度增加并从而使所述栅氧7在所述顶角区5的具有圆化形貌。图2F中，和未进行所述带倾角离子注入相比，本发明实施例方法能使虚线圈102处的所述场氧7的厚度增加且形貌更加圆化。
本发明实施例方法中，所述栅氧7的热氧化的温度为800℃～1100℃。
为了进一步详细说明本发明实施例方法形成的所述栅氧7在所述顶角区5的表面的厚度会增加，现结合所述栅氧7对应的照片进行说明：
如图4A所示，是现有技术中未进行本发明实施例方法的带倾角离子注入时形成的栅氧的照片；图4A中，所述半导体衬底单独用标记1a标出，所述场氧单独用标记6a标出，所述栅氧单独用标记7a标出。所述顶角区的表面的所述栅氧7a位于虚线圈102a，所述顶角区的表面的所述栅氧7a的厚度用d4a表示，所述顶角区内侧的所述有源区表面的所述栅氧7b的厚度用d3a表示；d3a的大小为
Figure BDA0002620040200000061
d4a的大小为
Figure BDA0002620040200000062
d4a和d3a的比值为76.88％。d4a和d3a的比值表示现有方法形成的所述栅氧7a的台阶覆盖能力。
如图4B所示，是本发明实施例方法形成的栅氧的照片；图4B中，所述半导体衬底单独用标记1b标出，所述场氧单独用标记6b标出，所述栅氧单独用标记7b标出。所述顶角区的表面的所述栅氧7b位于线框102b中，所述顶角区的表面的所述栅氧7b的厚度用d4b表示，所述顶角区内侧的所述有源区表面的所述栅氧7b的厚度用线宽103中的d3b表示；d3b的大小为
Figure BDA0002620040200000063
d4b的大小为
Figure BDA0002620040200000064
d4b和d3b的比值为88.89％。d4b和d3b的比值表示本发明实施例方法形成的所述栅氧7b的台阶覆盖能力,可以看出本发明实施例方法形成的所述栅氧7b的台阶覆盖能力得到显著的增加即从76.88％增加到了88.89％。
步骤四完成后还包括如下步骤：
形成栅极导电材料层。通常，所述栅极导电材料层的材料包括多晶硅。
对所述栅极导电材料层进行图形化，图形化后的所述栅极导电材料层仅位于栅极结构的形成区域，由所述栅氧7和顶部的所述栅极导电材料层叠加而成。
采用所述栅氧7的半导体器件包括CMOS，VDMOS和IGBT。
针对本发明所要解决的技术问题，本发明实施例在栅氧7形成之前预先对半导体衬底1进行处理，具体为在浅沟槽4形成之后以及在浅沟槽4中填充场氧6之前，增加了带倾角离子注入，带倾角离子注入能将离子注入到浅沟槽4侧面的顶部并形成顶角区5而且能调节顶角区5的纵向深度，由于有源区是由浅沟槽4定义的，有源区的边缘正好位于顶角区5，故顶角区5中注入的离子能增加栅氧7的热氧化工艺中的热氧化速率，从而能增加顶角区5表面的栅氧7厚度并使栅氧7在顶角区5的具有圆化形貌。
而现有工艺中，在本发明实施例对应的顶角区5中没有注入离子，在栅氧7的热氧化工艺中，顶角区5表面的热氧化速率会慢于有源区的内部区域表面的热氧化速率且二者相差较大，有源区的内部区域表面为位于顶角区5内侧的有源区表面，这样会使顶角区5表面的栅氧7的厚度和有源区的内部区域表面的栅氧7的差异较大，使得顶角区5表面的栅氧7成为整个有源区表面的栅氧7的薄弱环节，从而容易在顶角区5表面的栅氧7处发生击穿，并降低器件的可靠性。
而本发明实施例通过增加顶角区5表面的栅氧7厚度后，能使顶角区5表面的栅氧7厚度和有源区的内部区域表面的栅氧7厚度的差异变小且能使顶角区5的栅氧7更加圆化，能提升在顶角区5表面的栅氧7处耐压能力，最后能提高整个有源区表面的栅氧7的耐压能力，从而能提高器件的击穿电压和可靠性。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限值。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (15)

1.一种栅氧的形成方法，其特征在于，包括如下步骤：
步骤一、在半导体衬底表面形成硬质掩膜层，依次对浅沟槽形成区域的所述硬质掩膜层和所述半导体衬底进行刻蚀形成浅沟槽，有源区由位于所述浅沟槽之间的所述半导体衬底组成，所述有源区表面的所述硬质掩膜层保留；
步骤二、进行带倾角离子注入在所述浅沟槽侧面顶部注入离子形成顶角区，所述顶角区位于所述有源区的外侧边缘；
步骤三、在所述浅沟槽中填充场氧并去除所述硬质掩膜层；
步骤四、进行热氧化在所述有源区的表面形成栅氧；在所述栅氧的热氧化过程中，所述顶角区中注入的离子使所述顶角区的热氧化速率增加，使所述栅氧在所述顶角区的表面的厚度增加并从而使所述栅氧在所述顶角区的具有圆化形貌。
2.如权利要求1所述的栅氧的形成方法，其特征在于：所述半导体衬底为硅衬底。
3.如权利要求1或2所述的栅氧的形成方法，其特征在于：所述硬质掩膜层由氮化层组成或者由氧化层和氮化层叠加而成。
4.如权利要求1所述的栅氧的形成方法，其特征在于：步骤二中，所述带倾角离子注入的注入能量的最大值要求保证注入的离子不会穿过所述硬质掩膜层到达所述硬质掩膜层底部的所述有源区的表面。
5.如权利要求4所述的栅氧的形成方法，其特征在于：所述带倾角离子注入的注入能量为500kev～5kev。
6.如权利要求1或4或5所述的栅氧的形成方法，其特征在于：步骤二中，所述顶角区的纵向深度由所述硬质掩膜层的厚度、所述浅沟槽的顶部开口宽度以及所述带倾角离子注入的注入角度；所述硬质掩膜层的厚度和所述浅沟槽的顶部开口宽度为固定值，所述带倾角离子注入的注入角度为可设定值，通过设定所述带倾角离子注入的注入角度设定所述顶角区的纵向深度。
7.如权利要求6所述的栅氧的形成方法，其特征在于：步骤二中，所述带倾角离子注入的注入总剂量分多次完成。
8.如权利要求7所述的栅氧的形成方法，其特征在于：步骤二中，所述带倾角离子注入的注入过程中，所述半导体衬底的法线沿着所述带倾角离子注入的注入方向自转。
9.如权利要求1或4或5所述的栅氧的形成方法，其特征在于：步骤二中，所述带倾角离子注入的注入离子包括氩离子或氟离子。
10.如权利要求1所述的栅氧的形成方法，其特征在于：步骤四中，所述栅氧的热氧化的温度为800℃～1100℃。
11.如权利要求1所述的栅氧的形成方法，其特征在于：步骤三中，所述场氧的淀积工艺采用HDPCVD工艺。
12.如权利要求11所述的栅氧的形成方法，其特征在于：所述场氧的淀积工艺完成后还包括对所述场氧进行回刻或化学机械研磨，使所述场氧仅填充于所述浅沟槽中。
13.如权利要求1所述的栅氧的形成方法，其特征在于：步骤四完成后还包括如下步骤：
形成栅极导电材料层；
对所述栅极导电材料层进行图形化，图形化后的所述栅极导电材料层仅位于栅极结构的形成区域，由所述栅氧和顶部的所述栅极导电材料层叠加而成。
14.如权利要求13所述的栅氧的形成方法，其特征在于：所述栅极导电材料层的材料包括多晶硅。
15.如权利要求1或13所述的栅氧的形成方法，其特征在于：采用所述栅氧的半导体器件包括CMOS，VDMOS和IGBT。
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