WO2014059565A1 - Cmos制造方法 - Google Patents

Cmos制造方法 Download PDF

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Publication number
WO2014059565A1
WO2014059565A1 PCT/CN2012/001542 CN2012001542W WO2014059565A1 WO 2014059565 A1 WO2014059565 A1 WO 2014059565A1 CN 2012001542 W CN2012001542 W CN 2012001542W WO 2014059565 A1 WO2014059565 A1 WO 2014059565A1
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source
drain
region
substrate
pmos
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PCT/CN2012/001542
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English (en)
French (fr)
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殷华湘
闫江
陈大鹏
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中国科学院微电子研究所
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Publication of WO2014059565A1 publication Critical patent/WO2014059565A1/zh

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to an integrated method of source-drain selective epitaxy of a CMOS device. Background technique
  • the Strain Channel Engineering has become more and more important to improve the channel carrier mobility.
  • a variety of uniaxial process induced stresses are integrated into the device process, that is, introducing compressive or tensile stresses in the channel direction to enhance carrier mobility and improve device performance.
  • an embedded SiGe (e-SiGe) source-drain or 100-crystal substrate is combined with a tensile stress etch barrier (tCESL) to provide compressive stress in a pMOS device; in the 65nm process, Based on the 90nm process, the first-generation source-drain stress memory technology (SMT' 1 ) is further used, and a double-etch barrier layer is used.
  • e-SiGe embedded SiGe
  • tCESL tensile stress etch barrier
  • the second-generation source-drain stress memory technology is used on the basis of SMT ' 2 ), using e-SiGe technology combined with single tCESL or dual CESL, and using Stress Proximity Technique (SPT), in addition to using 110 surface substrate for pMOS and 100 surface substrate for nMOS; After 32nm, the third-generation source-drain stress memory technology (SMT x 3 ) was used. The embedded SiC source and drain were also used to enhance the tensile stress in the nMOS device.
  • SPT Stress Proximity Technique
  • the source-drain contact resistance accounts for a larger proportion of the resistance of the entire device, which seriously restricts the performance of the device.
  • a method generally is to epitaxially grow on the source/drain regions to form a raised source/drain region, or to form a metal silicide in the contact region.
  • the specific application is based on the above stress channel engineering, and it is necessary to selectively epitaxial SiGe for source and drain of the PMOS region, and selective epitaxial Si or Si:C for source and drain of the NMOS region.
  • the manufacturer of such NMOS and PMOS epitaxial lifts generally uses a mask or a cap layer to etch a source/drain trench in one of the MOSFET regions and selectively epitaxially form a material source lift source drain, and then deposit a second mask or cap layer, and then A MOSFET region is etched to form a source-drain trench and selectively epitaxially forms a raised source drain of another material.
  • the manufacturing method utilizes two masks for etching and epitaxy respectively, and the required processes are complicated, costly, time consuming, and easy to bring reliability problems. Summary of the invention
  • CMOS manufacturing method capable of low-cost, high-efficiency source-drain selective epitaxy.
  • the present invention provides a CMOS fabrication method comprising: forming a gate stack structure on an NMOS region and a PMOS region on a substrate; forming a gate spacer around the gate stack structure; selectively etching a PMOS region substrate Forming source and drain trenches on both sides of the gate spacer; forming a first source/drain lift region in the source drain trench; forming a cap layer on the NMOS region and the PMOS region on the substrate.
  • the gate stack structure is a dummy gate stack structure including a pad oxide layer and a dummy gate material layer, and the dummy gate material layer includes polysilicon, amorphous silicon, microcrystalline silicon, amorphous germanium, and combinations thereof.
  • selective epitaxial growth is performed to form a first source/drain lift region and/or a cap layer.
  • the step of selectively etching the PMOS region substrate further includes: forming a protective layer on the entire device; selectively etching the protective layer to expose the substrate in the PMOS region; etching the exposed substrate in the PMOS region to form a source/drain trench groove.
  • the cross-sectional shape of the source and drain trenches includes a rectangle, a trapezoid, an inverted trapezoid, a dome, a D, a C, and a combination thereof.
  • the cap layer also serves as the second source-drain lift region of the NMOS region.
  • the cap layer comprises Si, Si: C.
  • the first source-drain lift region comprises SiGe, SiGe: (:.
  • the protective layer comprises silicon nitride, silicon oxide and a combination thereof.
  • the protective layer is further removed.
  • the PMOS lift source and drain are selectively etched and epitaxially grown, and then the NMOS lift source and drain are globally epitaxially grown, the process steps are reduced, the cost is reduced, and the reliability of the device is improved.
  • FIG. 1 to 5 are schematic cross-sectional views showing respective steps of a CMOS manufacturing method according to the present invention.
  • FIG. 6 is a schematic flow chart of a CMOS fabrication method in accordance with the present invention. detailed description
  • a (false) gate stack structure is formed on the substrate.
  • a substrate 1 is provided.
  • the substrate 1 is suitably selected according to the needs of the device, and may include single crystal silicon (Si), silicon on insulator (SOI), single crystal germanium (Ge), germanium on insulator (GeOI), strained silicon (strained Si), germanium silicon (SiGe). ) or compound semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), and carbon-based semiconductors such as graphene, SiC, carbon nanotubes and many more.
  • the substrate 1 is a bulk Si or SOI for compatibility with a CMOS process for making large scale integrated circuits.
  • a shallow trench isolation (STI) 2 is formed in the substrate 1, for example, photolithography/etching of the substrate 1 to form shallow trenches, and then an insulating isolation material is deposited by conventional techniques such as LPCVD, PECVD, and CMP planarization until the substrate 1 is exposed.
  • Forming STI 2 wherein the filling material of the STI 2 may be a conventional insulating material such as an oxide, a nitride, an oxynitride, or the like, and may also be Bi 0 . 95 La 0 .
  • the area surrounded by the STI 2 constitutes an active area, wherein the left side area in FIG. 1 corresponds to the NMOS area, and the right side area corresponds to the PMOS area.
  • the NMOS region and the PMOS region are only one and adjacent, in fact, according to the layout design requirements, two kinds of MOSFETs Zones may or may not be adjacent.
  • a gate insulating layer 3 and a gate material layer 4 are sequentially deposited over the entire surface of the wafer, i.e., the surface of the substrate 1 and the surface of the STI 2, and etched to form a gate stack structure (3/4) in the active region.
  • a back gate process is employed, so the gate stack structure is a dummy gate stack structure that will be removed in subsequent processes. Therefore, the gate insulating layer 3 is preferably a pad layer of silicon oxide; the gate material layer 4 is a dummy gate material layer, preferably polysilicon, amorphous silicon, microcrystalline silicon, amorphous germanium, and combinations thereof.
  • the gate insulating layer 3 is preferably silicon oxide, nitrogen-doped silicon oxide, silicon nitride, or other high-k material, and the high-k material includes, but is not limited to, selected from the group consisting of Hf0 2 , HfSiO x , HfSiON , HfA10 x , HfTaO x , a base material of HfLaO x , HfAlSiO x , HfLaSiO x (wherein each material is appropriately adjusted according to a distribution ratio of a plurality of metal groups and a chemical price, and the oxygen atom content X can be appropriately adjusted, for example, 1 to 6 and not limited to an integer), or
  • the invention comprises a rare earth-based high-k dielectric material selected from the group consisting of Zr ⁇ 2 , La 2
  • a barrier layer (not shown) of nitride is preferably formed between the gate material layer 4 and the gate insulating layer 3 by a conventional method such as PVD, CVD, ALD, etc., and the barrier layer is made of M x N y , M x Si y N z , M x Al y N z , M a Al x Si y N z , wherein M is Ta, Ti, Hf, Zr, Mo, W or other elements. More preferably, the gate material layer 4 and the barrier layer not only adopt a composite layer structure stacked on top of each other, but also a mixed implant doped layer structure, that is, a material constituting the gate material layer 4 and the barrier layer is simultaneously deposited on the gate. On the pole insulating layer 3, the gate conductive layer thus comprises the material of the above barrier layer.
  • a hard mask layer or a capping layer (not shown) of a material such as silicon nitride may be further formed over the gate material layer 4 to protect the gate stack structure during subsequent etching.
  • ion implantation may be performed as a mask after the gate stack structure is formed, such that the corresponding regions of the substrate are lightly doped to form a source/drain extension region or a halo source/drain doping region (not shown).
  • a gate spacer 5 is formed on the substrate 1 around the (false) gate stack structure 3/4, and a protective layer 6 is formed over the entire device.
  • PECVD, HDPCVD, etc. a deposition method, depositing an insulating layer of silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC) on the substrate 1, the gate stack structure 3/4, and then photolithography/etching to form a gate spacer 5.
  • the gate spacer 5 is used to define the position of the source and drain regions later.
  • a protective layer 6 made of silicon nitride or the like is deposited on the entire device by a method such as PEC VD or HDPCVD, covering the substrate 1 and the gate stack structure in the NM 0 S region and the PMOS region.
  • selective etching forms source and drain trenches in the PMOS region.
  • a portion of the protective layer 6 of the PMOS region is etched away to expose the substrate of the PMOS region, leaving only a portion of the protective layer 6 in the NMOS region.
  • TMAH wet etching or fluorine-based, chlorine-based gas plasma dry etching is used to form source-drain trenches 1 T in the PMOS region.
  • the cross-sectional shape of the source/drain trench IT may be rectangular, trapezoidal, inverted trapezoidal, or ⁇ -shaped (multi-section broken lines are connected, recessed toward the channel region, that is, the width of the middle portion of the trench is larger than the width of the top and/or bottom), D Shape (1/2 curve, curve including circle, ellipse, hyperbola), C shape (greater than 1/2 curve, curve including circle, ellipse, hyperbola).
  • the depth of the source drain trench 1T is preferably smaller than the thickness/depth of the STI 2.
  • a first lift source drain region 1 P is formed.
  • the material is, for example, SiGe or SiGe:C suitable for PMOS.
  • ion implantation may be performed after in-situ doping, or epitaxial growth, to form heavily doped source and drain regions (not shown), and for PMOS doped boron B, aluminum Al, gallium Ga, indium In and so on.
  • the rising source/drain region 1 P can effectively reduce the source-drain contact resistance of the PMOS region, and can also apply stress to the PMOS channel region to increase the carrier mobility.
  • the protective layer 6 is removed, and a cap layer is simultaneously formed in the NMOS region and the PMOS region.
  • the remaining protective layer 6 of the NMOS region is removed by wet etching and/or dry etching.
  • global selective epitaxy is simultaneously performed on the active regions of the NMOS and the PMOS, selective epitaxial growth by PECVD, HDPCVD, MBE, ALD, thermal decomposition, etc., the substrate 1 on both sides of the gate stack structure and the first
  • a cap layer 7 is formed on the source/drain region 1 P, and the material thereof is, for example, Si or Si:C suitable for NMOS.
  • the cap layer 7 can also serve as the second lift source drain region 1 N in the NMOS region.
  • ion implantation may be performed after in-situ doping, or epitaxial growth, to form a heavily doped source and drain region (not shown), and may be doped with phosphorus for the NMOS? , arsenic As, ⁇ Sb, etc.
  • the cap layer 7/uplift source/drain region 1 N can effectively reduce the source-drain contact resistance of the NMO S region, and can also apply stress to the NMO S channel region to increase carrier mobility.
  • a subsequent process may be performed, such as depositing an interlayer dielectric layer (ILD, not shown) of a low-k material, etching the ILD to form a source-drain contact hole until the exposed source/drain region 1N/1P is exposed, and forming a source/drain contact hole
  • ILD interlayer dielectric layer
  • the metal silicide, the deposited metal is filled to form a source-drain contact plug, and finally the device fabrication is completed.
  • the dummy gate stack can be removed to form a gate trench, and the gate insulating layer of the high-k material and the gate conductive layer of the metal material are deposited in the gate trench.
  • the gate stack structure is then followed by the subsequent process.
  • CMOS schematic of a planar channel is shown in the drawings of the present invention, those skilled in the art will appreciate that the present invention is also applicable to other device structures, such as stereo multi-gate, vertical channel, nanowire devices, and the like. .
  • the PMOS lifts the source and drain by selective etching and epitaxial growth
  • the NMOS boosts the source and drain by the global selective epitaxial growth, which reduces the process steps, reduces the cost, and improves the reliability of the device.

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Abstract

一种CMOS制造方法，包括：在衬底（1）上NMOS区域和PMOS区域形成栅极堆叠结构（3）、（4）；在栅极堆叠结构周围形成栅极侧墙（5）；选择性刻蚀PMOS区域衬底，在栅极侧墙两侧形成源漏沟槽（1T）；在源漏沟槽中形成第一源漏抬升区（1P）；在衬底上NMOS区域和PMOS区域形成盖层（7）。这种CMOS制造方法，先选择性刻蚀、外延生长PMOS抬升源漏，后全局选择性外延生长NMOS抬升源漏，减少了工艺步骤，降低了成本，提高了器件的可靠性。

Description

CMOS制造方法 优先权要求
本申请要求了 2012年 10月 17日提交的、 申请号为 201210395581.4、 发明名称为 "CMOS制造方法" 的中国专利申请的优先权， 其全部内容 通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法，特别是涉及一种 CMOS器件 源漏选择性外延的集成方法。 背景技术
从 90nm CMOS集成电路工艺起， 随着器件特征尺寸的不断缩小， 以提高沟道载流子迁移率为 目 的应力沟道工程 （ Strain Channel Engineering ) 起到了越来越重要的作用。 多种单轴工艺诱致应力被集 成到器件工艺中去， 也即在沟道方向引入压应力或拉应力从而增强载 流子迁移率， 提高器件性能。 例如， 在 90nm工艺中， 采用嵌入式 SiGe ( e-SiGe ) 源漏或 100晶向衬底并结合拉应力蚀刻阻障层 （ tCESL ) 来 提供 pMOS器件中的压应力； 在 65nm工艺中， 在 90nm工艺基础上进 一步采用第一代源漏极应力记忆技术 （ SMT' 1 ), 并采用了双蚀刻阻障 层； 45nm 工艺中， 在之前基础上采用了第二代源漏极应力记忆技术 ( SMT ' 2 ), 采用 e-SiGe技术结合单 tCESL或双 CESL, 并采用了应力 近临技术 （ Stress Proximity Technique, SPT ), 此外还针对 pMOS采用 110面衬底而针对 nMOS采用 100面衬底； 32nm之后， 采用了第三代 源漏极应力记忆技术 （SMTx 3 )， 在之前基础之上还选用了嵌入式 SiC 源漏来增强 nMOS器件中的拉应力。
另一方面， 32nm以下工艺中， 源漏接触电阻在整个器件的电阻中 所占比例越来越大， 严重制约了器件性能提高。 为了减小源漏接触电 阻， 通常采取的方法是在源漏区上外延生长形成抬升的源漏区， 或者 在接触区域形成金属硅化物。 具体应用在前述应力沟道工程的基础上， 不仅要对于 PMOS区的源漏选择性外延 SiGe,还要对于 NMOS区的源 漏选择性外延 Si或者 Si:C。 这种 NMOS、 PMOS均外延抬升的制造方 法通常是利用掩模或盖帽层， 先在其中一种 MOSFET区域刻蚀形成源 漏沟槽并选择性外延形成一种材料的抬升源漏， 随后沉积第二掩模或 盖帽层， 再在另一种 MOSFET区域刻蚀形成源漏沟槽并选择性外延形 成另一种材料的抬升源漏。 此种制作方法利用两次掩模分别刻蚀、 外 延， 需要的工序复杂， 成本较高、 耗时较多， 且容易带来可靠性问题。 发明内容
由上所述， 本发明的目的在于提供一种能低成本、 高效的源漏选 择性外延的 CMOS制造方法。
为此， 本发明提供了一种 CMOS制造方法， 包括： 在衬底上 NMOS 区域和 PMOS区域形成栅极堆叠结构； 在栅极堆叠结构周围形成栅极侧 墙； 选择性刻蚀 PMOS区域衬底， 在栅极侧墙两侧形成源漏沟槽； 在源 漏沟槽中形成第一源漏抬升区； 在衬底上 NMOS区域和 PMOS区域形成 盖层。
其中， 栅极堆叠结构是假栅极堆叠结构， 包括垫氧化层和假栅极 材料层， 假栅极材料层包括多晶硅、 非晶硅、 微晶硅、 非晶锗及其组 合。
其中， 选择性外延生长以形成第一源漏抬升区和 /或盖层。
其中， 选择性刻蚀 PMOS区域衬底的步骤进一步包括： 在整个器件 上形成保护层；选择性刻蚀保护层，暴露 PMOS区域的衬底；刻蚀 PMOS 区域暴露的衬底， 形成源漏沟槽。
其中， 源漏沟槽的剖面形态包括矩形、 梯形、 倒梯形、 ∑形、 D形、 C形及其组合。
其中， 盖层也作为 NMOS区域的第二源漏抬升区。
其中， 盖层包括 Si、 Si:C。
其中， 第一源漏抬升区包括 SiGe、 SiGe: (：。
其中， 保护层包括氮化硅、 氧化硅及其组合。
其中， 形成第一源漏抬升区之后还包括去除保护层。
依照本发明的 CMOS制造方法， 先选择性刻蚀、 外延生长 PMOS抬 升源漏， 后全局选择性外延生长 NMOS抬升源漏， 减少了工艺步骤， 降 低了成本， 提高了器件的可靠性。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 5为依照本发明的 CMOS制造方法各步骤的剖面示意图；以 及
图 6为依照本发明的 CMOS制造方法的示意性流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了能低成本、 高效的源漏选择性外延的 CMOS制造方法。 需要指出的是， 类似的附图标记表示类似的结构， 本 申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 等等可用于 修饰各种器件结构或制造工序。 这些修饰除非特别说明并非暗示所修 饰器件结构或制造工序的空间、 次序或层级关系。
以下将结合图 6的流程图并且参照图 1至图 5的剖面示意图来详细 说明依照本发明的半导体器件制造方法各步骤。
如图 1 所示， 在衬底上形成（假）栅极堆叠结构。 提供衬底 1。 衬 底 1依照器件用途需要而合理选择， 可包括单晶体硅（Si ) 、 绝缘体上 硅（ SOI ) 、 单晶体锗（ Ge ) 、 绝缘体上锗（ GeOI ) 、 应变硅（ Strained Si ) 、 锗硅 （SiGe ) , 或是化合物半导体材料， 例如氮化镓 （GaN ) 、 砷化镓 （GaAs ) 、 磷化铟（InP)、 锑化铟 （ InSb ) ， 以及碳基半导体例 如石墨烯、 SiC、 碳纳管等等。 优选地， 衬底 1 为体 Si或 SOI以便与 CMOS工艺兼容而用于制作大规模集成电路。
在衬底 1 中形成浅沟槽隔离 （STI ) 2， 例如先光刻 /刻蚀衬底 1 形 成浅沟槽然后采用 LPCVD、 PECVD 等常规技术沉积绝缘隔离材料并 CMP平坦化直至露出衬底 1 , 形成 STI 2 , 其中 STI 2的填充材料可以 是氧化物、 氮化物、 氮氧化物等常规绝缘材料， 还可以是 Bi0.95La0.05NiO3、 BiNi03、 ZrW208、 Ag3[Co(CN)6]等具有超大 （正 /负） 热膨胀系数的材料 （ 100K 的温度下线性体积膨胀系数的绝对值大于 10_4/K ) 以便通过应力 STI 2向沟道区施加应力从而进一步提高载流子 迁移率。 STI 2包围的区域构成有源区域， 其中图 1 中左侧区域对应于 NMOS区域， 右侧区域对应于 PMOS区域。 图 1 中虽然 NMOS区域与 PMOS区域仅为一个且相邻，实际上依照版图设计需要，两种 MOSFET 区或可以为多个， 也可以不相邻。
在整个晶片表面也即衬底 1和 STI 2表面依次沉积栅极绝缘层 3和栅 极材料层 4， 并刻蚀形成位于有源区域内的栅极堆叠结构 （3/4 ) 。 在本 发明一个实施例中， 采用后栅工艺， 因此栅极堆叠结构是假栅极堆叠 结构， 将在后续工艺中去除。 因此栅极绝缘层 3优选为氧化硅的垫层； 栅极材料层 4是假栅极材料层， 优选为多晶硅、 非晶硅、 微晶硅、 非晶 锗及其组合。
值得注意的是， 除此之外， 在本发明其他实施例中， 可以采用前 栅工艺， 栅极堆叠结构将在后续工艺中保留。 因此栅极绝缘层 3优选为 氧化硅、 掺氮氧化硅、 氮化硅、 或其它高 K材料， 高 k材料包括但不限 于包括选自 Hf02、 HfSiOx、 HfSiON、 HfA10x、 HfTaOx、 HfLaOx、 HfAlSiOx、 HfLaSiOx的铪基材料 （其中， 各材料依照多元金属组分配 比以及化学价不同， 氧原子含量 X可合理调整， 例如可为 1 ~ 6且不限于 整数） ， 或是包括选自 Zr〇2、 La203、 LaA103、 Ti02、 Y2O3的稀土基高 K介质材料， 或是包括 Α1203 , 以其上述材料的复合层； 栅极材料层 4则 可为多晶硅、 多晶锗硅、 或金属， 其中金属可包括 Co、 Ni、 Cu、 Al、 Pd、 Pt、 Ru、 Re、 Mo、 Ta、 Ti、 Hf、 Zr、 W、 Ir、 Eu、 Nd、 Er、 La 等金属单质、 或这些金属的合金以及这些金属的氮化物， 栅极材料层 4 中还可掺杂有 C、 F、 N、 0、 B、 P、 As等元素以调节功函数。 栅极材 料层 4与栅极绝缘层 3之间还优选通过 PVD、 CVD、 ALD等常规方法形 成氮化物的阻挡层（未示出）， 阻挡层材质为 MxNy、 MxSiyNz、 MxAlyNz、 MaAlxSiyNz, 其中 M为 Ta、 Ti、 Hf、 Zr、 Mo、 W或其它元素。 更优选地， 栅极材料层 4与阻挡层不仅采用上下叠置的复合层结构， 还可以采用混 杂的注入掺杂层结构， 也即构成栅极材料层 4与阻挡层的材料同时沉积 在栅极绝缘层 3上， 因此栅极导电层包括上述阻挡层的材料。
优选地， 在栅极材料层 4之上还可以进一步形成例如氮化硅等材质 的硬掩模层或者盖帽层 （未示出） ， 以在后续刻蚀过程中保护栅极堆 叠结构。 优选地， 可以在形成栅极堆叠结构之后， 以此为掩模进行离 子注入， 使得衬底相应区域具有轻掺杂而构成源漏扩展区或者暈状源 漏掺杂区 （未示出） 。
如图 2所示， 在 （假） 栅极堆叠结构 3/4周围的衬底 1上形成栅极侧 墙 5 , 并且在整个器件上形成保护层 6。 采用 PECVD、 HDPCVD等常规 沉积方法， 在衬底 1、 栅极堆叠结构 3/4上沉积氮化硅、 氮氧化硅、 类金 刚石无定形碳（ DLC )等材质的绝缘层 , 随后光刻 /刻蚀形成栅极側墙 5。 栅极侧墙 5用于限定稍后源漏区的位置。通过 PEC VD、 HDPCVD等方法， 在整个器件上沉积氮化硅等材质的保护层 6 , 覆盖了 NM 0 S区域和 PMOS区域中的衬底 1、 栅极堆叠结构。
如图 3所示， 选择性刻蚀， 在 PMOS区域形成源漏沟槽。 刻蚀去除 PMOS区域的部分保护层 6以暴露 PMOS区域的衬底，仅在 NMOS区域留 下部分保护层 6。 随后采用 TMAH湿法腐蚀或者氟基、 氯基气体等离子 干法刻蚀， 在 PMOS区域形成源漏沟槽 1 T。 源漏沟槽 I T的剖面形态可以 是矩形、 梯形、 倒梯形、 ∑形 （多段折线相连， 朝向沟道区凹进， 也即 沟槽中部的宽度要大于顶部和 /或底部的宽度） 、 D形 （ 1/2曲线， 曲线 包括圆、 橢圆、 双曲线） 、 C形 （大于 1/2曲线， 曲线包括圆、 椭圆、 双曲线） 。 源漏沟槽 1T的深度优选地小于 STI 2的厚度 /深度。
如图 4所示， 形成第一抬升源漏区 1 P。 通过 CVD、 UHVCVD , HDPCVD MBE、 ALD、 热分解等方法选择性外延生长， 在 PMOS区 域的源漏沟槽中形成第一抬升源漏区 1 P , 其顶部优选地高于衬底 1顶 部， 其材质例如是适用于 PMOS的 SiGe、 SiGe:C。 优选地， 可以在外延 生长同时原位掺杂、 或者外延生长之后执行离子注入， 形成重掺杂源 漏区 （未示出） ， 对于 PMOS而言掺杂硼 B、 铝 Al、 镓 Ga、 铟 In等。 该 抬升源漏区 1 P可以有效降低 PMOS区域的源漏接触电阻，此外还可以向 PMOS沟道区施加应力， 增大载流子迁移率。
如图 5所示， 去除保护层 6 , 在 NMOS区域和 PMOS区域同时形成盖 层。 通过湿法腐蚀和 /或干法刻蚀， 去除 NMOS区域剩余的保护层 6。 随 后， 在 NMOS和 PMOS的有源区上同时执行全局选择性外延， 通过 PECVD、 HDPCVD、 MBE、 ALD、 热分解等方法选择性外延生长， 在 栅极堆叠结构两侧的衬底 1以及第一抬升源漏区 1 P上形成盖层 7， 其材 质例如是适用于 NMOS的 Si或者 Si:C。该盖层 7在 NMOS区域也可以作为 第二抬升源漏区 1 N。 优选地， 可以在外延生长同时原位掺杂、 或者外 延生长之后执行离子注入， 形成重掺杂源漏区 （未示出 ) , 对于 NMOS 而言可以掺杂磷？、 砷 As、 锑 Sb等。 在 NMOS区域， 该盖层 7/抬升源漏 区 1 N可以有效降低 NMO S区域的源漏接触电阻， 此外还可以向 NMO S 沟道区施加应力， 增大载流子迁移率。 此后， 可以执行后续工艺， 例如沉积低 k材料的层间介质层（ ILD, 未示出） ， 刻蚀 ILD形成源漏接触孔直至暴露抬升源漏区 1N/1P, 在源 漏接触孔中形成金属硅化物， 沉积金属填充形成源漏接触塞， 最终完 成器件制造。 对于后栅工艺而言， 可以在形成 ILD之后， 去除假栅极堆 叠形成栅极沟槽， 在栅极沟槽中沉积高 k材料的栅极绝缘层和金属材料 的栅极导电层构成的最终栅极堆叠结构， 然后再执行后续的工艺。
此外， 虽然本发明附图中仅显示了平面沟道的 CMOS示意图， 但是 本领域技术人员应当知晓的是本发明也可应用于其他器件结构， 例如 立体多栅、 垂直沟道、 納米线器件等。
依照本发明的 CMOS制造方法， 先选择性刻蚀、 外延生长 PMOS抬 升源漏， 后全局选择性外延生长 NMOS抬升源漏， 减少了工艺步骤， 降 低了成本， 提高了器件的可靠性。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种 CMOS制造方法， 包括：
在衬底上 NM0S区域和 PM0S区域形成栅极堆叠结构；
在栅极堆叠结构周围形成栅极侧墙；
选择性刻蚀 PMOS区域衬底 , 在栅极侧墙两侧形成源漏沟槽； 在源漏沟槽中形成第一源漏抬升区；
在衬底上 NMOS区域和 PMOS区域形成盖层。
2. 如权利要求 1的方法， 其中， 栅极堆叠结构是假栅极堆叠结构， 包括垫氧化层和假栅极材料层， 假栅极材料层包括多晶硅、 非晶硅、 微晶硅、 非晶锗及其组合。
3. 如权利要求 1的方法， 其中， 选择性外延生长以形成第一源漏抬 升区和 /或盖层。
4. 如权利要求 1的方法， 其中， 选择性刻蚀 PMOS区域衬底的步骤 进一步包括：
在整个器件上形成保护层；
选择性刻蚀保护层， 暴露 PMOS区域的衬底；
刻蚀 PMOS区域暴露的衬底， 形成源漏沟槽。
5. 如权利要求 1的方法， 其中， 源漏沟槽的剖面形态包括矩形、 梯 形、 倒梯形、 ∑形、 D形、 C形及其组合。
6. 如权利要求 1的方法， 其中， 盖层也作为 NMOS区域的第二源漏 抬升区。
7. 如权利要求 1的方法， 其中， 盖层包括 Si、 Si:C。
8. 如权利要求 1的方法， 其中， 第一源漏抬升区包括 SiGe、 SiGe:C„
9. 如权利要求 4的方法， 其中， 保护层包括氮化硅、 氧化硅及其组 合。
10. 如权利要求 4的方法， 其中， 形成第一源漏抬升区之后还包括 去除保护层。
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