WO2014056268A1 - 太阳能电池及其制作方法 - Google Patents

太阳能电池及其制作方法 Download PDF

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Publication number
WO2014056268A1
WO2014056268A1 PCT/CN2012/083615 CN2012083615W WO2014056268A1 WO 2014056268 A1 WO2014056268 A1 WO 2014056268A1 CN 2012083615 W CN2012083615 W CN 2012083615W WO 2014056268 A1 WO2014056268 A1 WO 2014056268A1
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doped
layer
insulating layer
region
opening
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PCT/CN2012/083615
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English (en)
French (fr)
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陈芃
梁硕玮
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友达光电股份有限公司
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Priority to JP2015535954A priority Critical patent/JP2015531550A/ja
Priority to EP12886416.2A priority patent/EP2908340A4/en
Publication of WO2014056268A1 publication Critical patent/WO2014056268A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a solar cell and a method of fabricating the same, and more particularly to a solar cell battery having high photoelectric conversion efficiency and a method of fabricating the same. Background technique
  • One of the objects of the present invention is to provide a solar cell and a method of fabricating the same that can improve the photoelectric conversion efficiency of a solar cell by designing the relative positions of the doping elements and the insulating layer in the solar cell.
  • the invention discloses a solar cell comprising a semiconductor substrate, a doped layer, a doped polysilicon layer, a doped region, an insulating layer, at least one first electrode and at least one second electrode.
  • the semiconductor substrate has a first surface and a second surface, wherein the second surface has a first region and a second region, and the semiconductor substrate has a first doping type.
  • the doped layer is located on the first surface of the semiconductor substrate and has the first doping type.
  • the doped polysilicon layer is disposed in the first region on the second surface of the semiconductor substrate and exposes the second region of the second surface of the semiconductor substrate.
  • the doped region is disposed in the second region of the second surface of the semiconductor substrate, wherein one of the doped polysilicon layer and the doped region has a second doping type, and the doped polysilicon layer and the doped region are The other has the first doping type and the second doping type is opposite to the first doping type.
  • the insulating layer covers the surface of the doped polysilicon layer and the doped region, and has at least one first opening exposing a partially doped polysilicon layer and at least one second opening exposing a partially doped region.
  • the first electrode is disposed on the surface of the insulating layer, and is connected to the doped polysilicon layer via the first opening, and the second electrode is also disposed on the surface of the insulating layer, and is connected to the doped region via the second opening.
  • the present invention also discloses a method of fabricating a solar cell comprising the following steps. First, a semiconductor substrate having a first surface and a second surface, wherein the second surface has a first region and a second region, and the semiconductor substrate has a first doping type. A doped polysilicon layer is formed over the first region of the second surface of the semiconductor substrate that exposes the second region of the second surface of the semiconductor substrate.
  • An insulating layer is then formed covering the doped polysilicon layer and the doped region surface. The insulating layer has at least one first opening exposing a partially doped polysilicon layer and at least one second opening exposing a partially doped region.
  • Forming a metal layer on the surface of the insulating layer comprising at least a first electrode and a second electrode, wherein the first electrode is in contact with the doped polysilicon layer via the first opening of the insulating layer, and the second electrode is via the insulating layer The second opening is in contact with the doped region.
  • the doped polysilicon layer of the solar cell of the present invention acts as an emitter or back surface electric field, the junction formed by the polysilicon and the semiconductor substrate can reduce the carrier recombination problem, thereby improving the photoelectric conversion efficiency.
  • 1 to 7 are schematic flow charts of a first embodiment of a method for fabricating a solar cell of the present invention.
  • Figure 8 is a cross-sectional view showing the structure of a second embodiment of the solar cell of the present invention.
  • 9 to 13 are schematic views showing the process of a third embodiment of a method for fabricating a solar cell of the present invention.
  • Figure 14 is a cross-sectional view showing the structure of a fourth embodiment of the solar cell of the present invention.
  • FIG. 1 is a cross-sectional view showing a first embodiment of a solar cell of the present invention.
  • the solar cell 10 of the invention is an interdigitated back contact (IBC) solar cell comprising a semiconductor substrate 12, a doped layer 14, a doped polysilicon layer 16, a doped region 32, and an insulating layer 20. At least one first electrode 22 and at least one second electrode 24.
  • the semiconductor substrate 12 has a first surface 12a and a second surface 12b.
  • the first surface 12a is a light-receiving side, which can be regarded as a front side of the solar cell 10, and the second surface 12b is opposite.
  • the other side of the semiconductor substrate 12 is provided on the first surface 12a and can be regarded as the rear side of the solar cell 10. That is, the above two sides are located on different sides of the semiconductor substrate 12 and on the opposite side.
  • the second surface 12b defines a first region 26 and a second region 28. As shown in FIG. 1, the patterns of the first region 26 and the second region 28 are substantially staggered from left to right as an example, but are not limited thereto. In other embodiments, the first region 26 and the second region 28 may also occupy the left and right halves of the second surface 12b of the semiconductor substrate or have other suitable arrangements.
  • the doped layer 14 is located on the first surface 12a of the semiconductor substrate 12, and the doped layer 14 and the semiconductor substrate 12 have a first doping type of the same polarity, and the doping concentration of the doping layer 14 is preferably higher than that of the semiconductor substrate 12.
  • the impurity concentration for example, the semiconductor substrate 12 is lightly doped, and the doped layer 14 is heavily doped, but is not limited thereto.
  • the doped polysilicon layer 16 is disposed in the first region 26 on the second surface 12b of the semiconductor substrate 12, exposing the second region 28 of the second surface 12b of the semiconductor substrate 12, and the doped region 32 is disposed on the semiconductor substrate 12. Among the second regions 28 of the second surface 12b. As shown in FIG.
  • the doped polysilicon layer 16 is located on the second surface 12b, and the doped region 32 is substantially below the second surface 12b of the semiconductor substrate 12.
  • the doped region 32 is disposed below the second surface 12b.
  • the doped polysilicon layer 16 and the doped region 32 are alternately spaced from left to right as an example.
  • One of the doped polysilicon layer 16 and the doped region 32 has a first doping type
  • the other of the doped polysilicon layer 16 and the doped region 32 has a second doping type
  • the second doping The type is opposite to the first doping type
  • both the doped polysilicon layer 16 and the doped region 32 preferably have a heavily doped concentration.
  • the insulating layer 20 is disposed on the second surface 12b of the semiconductor substrate 12, and has at least one first opening 34 (three first openings 34 are shown as an illustration) and at least one second opening 36 (two seconds are shown)
  • the opening 36 as an illustration) exposes the partially doped polysilicon layer 16 and the partially doped region 32, respectively.
  • the first electrode 22 is disposed on the surface of the insulating layer 20, is in contact with the doped polysilicon layer 16 through the first opening 34, and the second electrode 24 is also disposed on the surface of the insulating layer 20 through the second opening 36 and the doped region. 32 contacts.
  • first electrode 22 and the second electrode 24 are not connected to each other, one of them is used as the positive electrode of the solar cell 10, and the other is used as the negative electrode of the solar cell 10. Therefore, the positive and negative electrodes of the solar cell 10 are all located on the back side of the battery, that is, on the second surface 12b opposite to the light receiving side first surface 12a.
  • the insulating layer 20 is a composite insulating layer, including at least a first insulating layer 38 and a second insulating layer 40, wherein the first insulating layer 38 covers the surface of the doped polysilicon layer 16 and has at least one The first opening 42 and the at least one second opening 44 expose the partially doped polysilicon layer 16 for the first opening 42 and the doped region 32 for the second opening 44.
  • the second insulating layer 40 covers the first insulating layer 38 and the partially doped region 32 and has at least a third opening 46 and at least a fourth opening 48. Wherein, the third opening 46 corresponds to the first opening 42 and the fourth opening 48 corresponds to the second opening 48.
  • the third opening 46 exposes the partially doped polysilicon layer 16, and the fourth opening 48 A portion of the doped region 32 is exposed.
  • the first opening 42 of the first insulating layer 38 and the third opening 46 of the second insulating layer 40 constitute the first opening 34 of the insulating layer 20, and the second opening of the first insulating layer 38.
  • the secondary opening 44 and the fourth opening 48 of the second insulating layer 40 form a second opening 36 of the insulating layer 20.
  • the first insulating layer 38 and the second insulating layer 40 comprise different materials.
  • the first insulating layer 38 comprises a fixed oxidized charge (or a fixed oxide layer charge or an oxide layer fixed charge).
  • the polarity of the fixed oxide charge is opposite to the polarity of the fixed oxidation charge contained in the second insulating layer 40.
  • the polarity of the fixed oxidation charge of the first insulating layer 38 and the doping polarity of the doped polysilicon layer 16 is opposite to the doping polarity of the doping region 32, whereby the first insulating layer 38 and the second insulating layer 40 can respectively dope the doped polysilicon layer 16 and
  • the minority carriers in the doped region 32 provide a field effect passivation function, avoiding the recombination of a few carriers, but are not limited thereto.
  • the polarity of the fixed oxidation charge of the first insulating layer 38 and the second insulating layer 40 can be determined by selecting the materials of the first insulating layer 38 and the second insulating layer 40.
  • silicon oxide (SiO x ) or nitrogen silicide may be used ( SiN x ) , silicon oxynitride (SiON), yttrium oxide (Y0 X ), other suitable materials, or a combination of at least two of the above, on the other hand, alumina ( ⁇ 10 ⁇ ), aluminum nitride can be used.
  • the polarity of the doping type of the semiconductor substrate 12, the doping layer 14, the doped polysilicon layer 16, the doping region 32 of the present embodiment, and the polarities of the fixed oxidation charges of the first insulating layer 38 and the second insulating layer 40 are exemplified. described as follows.
  • semiconductor substrate 12 is N-doped
  • doped layer 14 is N + doped
  • doped polysilicon layer 16 is P + doped
  • doped region 32 is N. + type doping
  • the first insulating layer 38 cooperates with the doping type of the doped polysilicon layer 16 to include a negative fixed oxide charge
  • the second insulating layer 40 includes a positive fixed oxidation charge in conjunction with the doping type of doped region 32.
  • solar cell 10 can also optionally include an oxide layer 18 disposed in first region 26 of second surface 12b of semiconductor substrate 12, in second region 28 of semiconductor substrate 12, doped polysilicon layer Between 16 and the semiconductor substrate 12, it is used as a tunnel oxide layer.
  • the oxide layer 18 has a thin enough thickness to increase the probability of electrons directly tunneling through the oxide layer 18, thereby increasing the photoelectric conversion efficiency.
  • the thickness of the oxide layer 18 may be about 5 to 20 angstroms (Angstroms, A). In certain embodiments, the oxide layer 18 has a thickness of about 10 angstroms. Preferably, the oxide layer 18 has a thickness of about 15 angstroms. Since the P + -type doped polysilicon layer 16 , the tunneling oxide layer 18 and the N-type doped semiconductor substrate 12 provide a heterodim junction-like structure, the saturation current can be greatly reduced, thereby being effective. Improve the photoelectric conversion efficiency.
  • the doping layer 14 functions as a front side field (FSF) element, and the doping region 32 serves as a back surface.
  • FSF front side field
  • BSF back side field
  • a doped polysilicon layer 16 having a P + type doping is used as an emitter of the solar cell 10.
  • the semiconductor substrate 12 is P-doped, and the doped layer 14 is P + doped.
  • the doped polysilicon layer 16 is N + -type doped, and the doped region 32 is P + -type doped, and the first insulating layer 38 includes a positive fixed oxide charge, and the second insulating layer 40 includes a negative fixed oxide charge.
  • the doped polysilicon layer 16 serves as an emitter of the solar cell 10, and because the PN junction between the semiconductor substrate 12 and the doped polysilicon layer 16 also enables the solar cell 10 to have good photoelectric conversion efficiency.
  • the semiconductor substrate 12 may be designed to be N-type doped, the doped layer 14 is N + doped, the doped polysilicon layer 16 is N + doped, and the doped region 32 is P + Type doping, the first insulating layer 38 comprises a positive fixed oxide charge, and the second insulating layer 40 comprises a negative fixed oxide charge, the doped polysilicon layer 16 is treated as a back surface electric field (BSF), and the doped region 32 is a shot.
  • BSF back surface electric field
  • the emitter and doped layer 14 are treated as a front surface electric field (FSF); or, in still other embodiments, the semiconductor substrate 12 is P-doped, and the doped layer 14 is P + doped, doped
  • the polysilicon layer 16 is P + -type doped, and the doped region 32 is N + -type doped, the first insulating layer 38 includes a negative-type fixed oxidation charge, and the second insulating layer 40 includes a positive-type fixed oxidation charge, and is doped.
  • the polysilicon layer 16 acts as a back surface electric field (BSF), the doped region 32 is an emitter, and the doped layer 14 acts as a front surface electric field (FSF).
  • BSF back surface electric field
  • FSF front surface electric field
  • the correspondence between the doping type of each doping element and the fixed oxidation charge polarity of the first insulating layer 38 and the second insulating layer 40 in the present invention is not limited to the above embodiment.
  • the solar cell 10 of the present embodiment may optionally include an antireflection coating (ARC) layer 30 disposed on the surface of the doped layer 14, but is not limited thereto.
  • the anti-reflection layer may be a single layer or a multilayer structure, and the material thereof includes silicon nitride, silicon oxide, silicon oxynitride, zinc oxide, titanium oxide, indium tin oxide (ITO), indium oxide, and bismuth oxide. a stannic oxide zirconium oxide, hafiiium oxide, an antimony oxide, a gadolinium oxide, other suitable materials, or a mixture of at least two of the foregoing.
  • the junction of the semiconductor substrate 12 and the doped layer 14 may selectively have a texturing process, for example, the first surface 12a has a roughened structure 12c to further improve the photoelectric conversion efficiency. But not limited to this.
  • FIG. 2 to FIG. 7 are schematic flowcharts of a first embodiment of a method for fabricating a solar cell according to the present invention.
  • a semiconductor substrate 12 is provided first, which may be a crystalline semiconductor substrate or a polycrystalline semiconductor substrate.
  • the thickness of the semiconductor substrate 12 is exemplified by about 50 microns to about 300 microns.
  • the semiconductor substrate 12 is preferably a substrate having a first doping type.
  • the semiconductor substrate 12 is exemplified as an N-doped substrate.
  • the semiconductor substrate 12 can be selectively cleaned and the damaged layer removed.
  • a thin oxide layer 18 can be selectively formed on the second surface 12b of the semiconductor substrate 12 as a tunneling oxide layer having a thickness ranging from about 5 angstroms to 20 angstroms, preferably about 15 angstroms, and the oxide layer 18 is exemplified.
  • the silicon oxide material may be included, formed by an ozone oxidation process or a high temperature oxidation process, but is not limited thereto.
  • a doped polysilicon layer 16 is formed on the surface of the oxide layer 18 to a thickness of about 50 to 500 nm, but is not limited thereto.
  • the doped polysilicon layer 16 may have a first doping type or a second doping type.
  • the doped polysilicon layer 16 has a second doping type having a polarity opposite to the first doping type of the semiconductor substrate 12, such as
  • the doped polysilicon layer 16 has a P + -type doping, and preferably has a doping concentration in the range of about 10 19 to 10 21 atoms/cm 2 , but is not limited thereto.
  • An example of a method for fabricating the doped polysilicon layer 16 is as follows: A chemical vapor deposition (CVD) forms a polysilicon layer on the surface of the oxide layer 18, and then an ion implantation process.
  • CVD chemical vapor deposition
  • the doped polysilicon layer 16 of the present embodiment may include a P type dopant.
  • a P type dopant for example, boron or boron compounds, but not limited to this.
  • Other methods of forming the doped polysilicon layer 16 include, for example, directly forming a doped polysilicon layer 16 having a P + -type doping by low pressure chemical vapor deposition (LPCVD), or forming an amorphous silicon layer first. The amorphous silicon layer is recrystallized by laser annealing or the like to form a polysilicon layer, and then an ion implantation process is performed.
  • the method of forming the doped polysilicon layer 16 is not limited to the above.
  • a first insulating layer 38 is selectively formed on the surface of the doped polysilicon layer 16, in order to make the first insulating layer 38 have a field effect passivation effect on a minority carrier in the doped polysilicon layer 16, and therefore, when doped
  • the first insulating layer 38 of the present embodiment preferably includes a negative-type fixed oxidation charge, and the material of the first insulating layer 38 may be selected from the materials described in the above embodiments.
  • alumina is used, for example, aluminum oxide, but not limited thereto.
  • the first insulating layer 38 of the present embodiment preferably includes a positive-type fixed oxidation charge, and the material of the first insulating layer 38 may be selected from the materials described above.
  • This embodiment uses silicon oxide as an example, such as SiO 2 , but is not limited thereto.
  • the thickness of the first insulating layer 38 may range from about 20 to 400 nanometers, but is not limited thereto. In other embodiments of the invention, the first insulating layer 38 may alternatively be omitted.
  • the steps of patterning the oxide layer 18, doping the polysilicon layer 16, and the first insulating layer 38 are performed.
  • the patterning process may first define a portion of the first insulating layer 38 to be retained on the surface of the first insulating layer 38 by using a screen printing mask 50 or a photoresist mask, that is, the semiconductor substrate 12
  • the first region 26 of the second surface 12b exposes the first insulating layer 38 in the second region 28 of the second surface 12b.
  • the method of forming the photoresist mask may be an exposure development method or an inkjet coating method. Then, as shown in FIG.
  • a portion of the first insulating layer 38, the doped polysilicon layer 16 and the oxide layer 18 exposed by the screen printing mask 50 or the photoresist mask are removed.
  • This removal method is exemplified by a wet etching or dry etching process, preferably a wet etching process, for example, a mixture of hydrofluoric acid (HF) and nitric acid (HN03).
  • the removing step may be completed in one time, or in multiple steps, for example, sequentially removing a portion of the first insulating layer 38, the partially doped polysilicon layer 16 and the partial oxide layer 18 in different etching processes, but not This is limited.
  • the step of patterning the first insulating layer 38, and doping the polysilicon layer 16 and the oxide layer 18 may also be performed by a laser method, but is not limited thereto. Therefore, the remaining first insulating layer 38, the doped polysilicon layer 16 and the oxide layer 18 are located within the first region 26 on the second surface 12b of the semiconductor substrate 12, exposing the second surface 12b of the semiconductor substrate 12.
  • the second zone 28, wherein the second zone 28 of the second surface 12b can have a plurality of dots, strip patterns or other suitable patterns.
  • the remaining oxide layer 18 is disposed between the first region 26 of the second surface 12b of the semiconductor substrate 12 and the doped polysilicon layer 16.
  • portions of the semiconductor substrate 12 on the surface of the second region 28 of the exposed second surface 12b may continue to be removed such that the semiconductor substrate 12 within the second region 28 A groove is formed in the groove, and the depth of the groove ranges from about 0 to 10 ⁇ m, but is not limited thereto.
  • This embodiment is exemplified by a groove depth of about 0 ⁇ m, that is, the patterning process stops the oxide layer 18 in the second region 28, without additionally forming a groove in the semiconductor substrate 12.
  • a doping region 12 is formed in the second region 28 of the exposed second surface 12b of the semiconductor substrate 12, and the doping region 12 of the embodiment has First doping type, for example having The N + type doping has a polarity opposite to that of the doped polysilicon layer 16.
  • the method of forming the doping region 32 is exemplified as follows: Since the first insulating layer 38 has the second opening 44 exposing the second region 28 of the second surface 12b, the first insulating layer 38 can be utilized as an ion implantation mask, first The second surface 12b of the semiconductor substrate 12 is ion-implanted, and the doped region 32 is formed by tempering or thermal diffusion, or the dopant is diffused directly into the semiconductor substrate 12 of the second region 28 by thermal diffusion, or directly The dopant is introduced into the semiconductor substrate 12 of the second region 28 by ion shower doping, but is not limited thereto.
  • the N + -type dopant may be, for example, phosphorus, arsenic, antimony or a compound of the above materials, but is not limited thereto.
  • the depth of the doping region 12 is exemplified by about 0.5 to 1 micrometer, and the doping concentration is, for example, 1019 to 10 21 atom/cm 2 , but not limited thereto.
  • a second insulating layer 40 is formed on the second surface 12b side of the semiconductor substrate 12 to cover the first insulating layer 38 and the doping region 32.
  • the polarity of the fixed oxidation charge selected by the second insulating layer 40 of the present embodiment needs to be doped with the doped polysilicon layer 16. Polarity and doping area 32 polarity to match.
  • the doped polysilicon layer 16 has P + -type doping
  • the doped region 32 has N + doping
  • the first insulating layer 38 is selected from a material containing a negative fixed oxide charge
  • the second insulating layer The material of the second insulating layer 40 is preferably a material such as silicon oxide or nitrogen silicide, but is not limited thereto.
  • the doped polysilicon layer 16 has an N + -type doping
  • the doped region 32 has a P + doping
  • the first insulating layer 38 is selected from a material containing a positive fixed oxide charge
  • the second insulating layer 40 preferably includes a negative
  • the type of the oxidized charge is fixed, and the material of the second insulating layer 40 may be selected from the materials described above, such as alumina, but not limited thereto.
  • the thickness of the second insulating layer 40 may range from about 20 to 400 nm, but is not limited thereto.
  • the second insulating layer 40 and the first insulating layer 38 are patterned to remove a portion of the second insulating layer 40 and a portion of the first insulating layer 38, so that the first insulating layer 38 has the first opening 42 and the second
  • the insulating layer 40 has a third opening 46 and a fourth opening 48 exposing a partially doped polysilicon layer 16 and a partially doped region 32.
  • the patterning process may define the positions of the third opening 46 and the fourth opening 48 prior to the second insulating layer 40 by using a screen printing mask, and then partially or sequentially remove a portion of the second insulating layer by an etching process. 40 and the first insulating layer 38.
  • the patterning process may also be performed by a photolithography and etching process (also referred to as a photoresist mask), but not limited thereto.
  • the third opening 46 corresponds to the first opening 42, which constitutes the first opening 34 of the insulating layer 20, exposing the partially doped polysilicon layer 16, and the fourth opening 48 corresponds to the first opening
  • the secondary openings 44 which form the second opening 36 of the insulating layer 20, expose a portion of the doped region 32.
  • the first opening 38 may be formed in the first insulating layer 38, the second insulating layer 40 may be formed, and then the second insulating layer 40 may be patterned to form a third in the second insulating layer 40. Secondary opening 46 and fourth opening 48.
  • a metal layer 52 is formed on the second surface 12b side of the semiconductor substrate 12, and the material thereof may be various metals with good conductivity, such as aluminum, silver, platinum, gold, copper or an alloy of the above materials. Or other suitable materials, but not limited to this. Then, the metal layer 52 is patterned to remove a portion of the metal layer 52 to form at least a first electrode 22 and at least a second electrode 24, and the first electrode 22 and the second electrode 24 respectively pass through the first layer of the insulating layer 20. The opening 34 and the second opening 36 are connected to the doped polysilicon layer 16 and the doped region 32.
  • the method of forming the first electrode 22 and the second electrode 24 may also be performed by applying a conductive adhesive method, and the conductive material of the conductive adhesive comprises aluminum, silver, nickel, copper or The alloy of the material, or other suitable materials, but not limited to this.
  • a method in which a conductive paste is applied includes a screen printing method, an inkjet method, or other suitable methods. The thickness, area and pattern of the first electrode 22 and the second electrode 24 can be adjusted as needed, and are not limited to those shown in FIG.
  • the first surface 12a of the semiconductor 12 may be selectively roughened, and then a doped layer 14 having a first doping type identical to the semiconductor substrate 12 is formed on the first surface 12a.
  • the polarity of the doping type for example, the doping layer 14 is heavily doped N + -type doping, and the forming method thereof may be, for example, the doping region 32 described above, including diffusing the dopant into the method using external ion diffusion.
  • the dopant used to form the doping layer 14 may be a dopant similar to the doping region 32, and the same portions will not be described again.
  • the doped layer 14 may also be a doped layer formed separately from the first surface 12a of the semiconductor substrate 12, such as a doped amorphous silicon layer, a crystalline layer, or a polysilicon layer, but not limit.
  • an anti-reflective layer 30 can be selectively formed on the doped layer 14 to cover the first surface 12a of the semiconductor substrate 12.
  • the anti-reflective layer 30 can be a single layer or a multi-layer structure, and the material can be selected from the above. The material of the anti-reflective layer 30 in FIG. Thereby, the fabrication of the main structure of the solar cell 10 of the present invention is completed.
  • each doping element in the solar cell of the present invention and the fixed oxidation charge polarity of the first and second insulating layers are not limited to those shown in FIG. 1, and different doping types are selected differently. Miscellaneous materials, fixed oxidation charges of different polarities also use different oxidizing materials to make the insulating layer, as exemplified above, and therefore will not be described again.
  • the components on the back side of the solar cell are fabricated first, the components on the front side are fabricated.
  • the components on the front side of the solar cell may be fabricated first, such as doped layers and The antireflection layer is then fabricated on the back side of the solar cell, such as an oxide layer, a doped polysilicon layer, a doped region, an insulating layer, a first electrode and a second electrode, and the like.
  • the components on the front side or the back side of the solar cell before the components on the other side are formed and the components on the first surface and the second surface of the semiconductor substrate can be interspersed. It is not limited to the order of production.
  • the method of producing a solar cell of the present invention is not limited to the above embodiment.
  • Other embodiments of the solar cell of the present invention and the method of fabricating the same will be further described below, and in order to facilitate the comparison of the differences of the embodiments and simplify the description, the same reference numerals are used hereinafter to designate the same elements, and mainly for each implementation. The differences between the examples are explained, and the repeated parts are not described again.
  • FIG. 8 is a cross-sectional view showing the structure of a solar cell according to a second embodiment of the present invention.
  • the solar cell 10 of the present embodiment has only one insulating layer 20 having a first opening 34 exposing a partially doped polysilicon layer 16 and a second opening 36 exposing a partially doped region 32,
  • the first electrode 22 and the second electrode 24 are made to be in contact with the doped polysilicon layer 16 and the doped region 32 via the first opening 34 and the second opening 36, respectively.
  • different materials may be selected as needed to form the insulating layer 20.
  • the saturation current of the P + -type doped polysilicon layer 16 and the N + -type doping region For example, when the insulating layer 20 has a negative type fixed oxidation charge, if the saturation current of the N + -type doping region 32 is desired to be improved, and the P + -type doped polysilicon layer 16 is exemplified, it may be selected.
  • the insulating layer 20 is made of a material having a positive type of fixed oxidation charge.
  • the doped polysilicon layer 16 has an N + -type doping
  • the doped doping region 32 has a P + -type doping as an example
  • a material having a positive fixed oxide charge can be selected for the insulating layer 20, and if it is desired to improve, the doping region 32 has a P + -type doped saturation current.
  • a material which causes the insulating layer 20 to have a negative fixed oxidation charge can be selected.
  • the positive or negative fixed oxidation charge material selected may be further described in Figure 1, and will not be described again.
  • the manufacturing method of the solar cell 10 of the present embodiment is similar to that of the previous embodiment. However, the fabrication of the first insulating layer is omitted in the process, and the doped polysilicon layer 16 and the oxide layer 18 are patterned after the doped polysilicon layer 16 is formed. a semiconductor substrate 12 in the second region 28 is exposed, and after the doping region 32 is formed, an insulating layer 20 is formed, and the insulating layer 20 is patterned to form a first opening 34 and a second opening 36, wherein the insulating layer
  • the thickness of the layer 20 may be, for example, about 20 to 500 nm, and the detailed fabrication method of each element will not be described here.
  • FIG. 9 to FIG. 13 are schematic diagrams showing a process of a third embodiment of a method for fabricating a solar cell according to the present invention, wherein FIG. 13 is a cross-sectional view showing the structure of a third embodiment of the solar cell of the present invention.
  • the first surface 12a of the semiconductor substrate 12 is first roughened so that the first surface 12a has the roughened structure 12c, and then the fabrication of the elements on the second surface 12b is performed. Similar to the process shown in FIGS.
  • an oxide layer 18, a doped polysilicon layer 16 and a first insulating layer 38 are sequentially formed on the second surface 12b of the semiconductor substrate 12, and then patterned and oxidized.
  • Layer 18, doped polysilicon layer 16 and first insulating layer 38, such as with screen printing mask 50 as an etch mask, exposed oxide layer 18, doped polysilicon layer 16, first insulating layer 38 and semiconductor substrate The second region 28 of the second surface 12 of 12 is etched. As shown, after the oxide layer 18 is removed, the second surface 12b of the semiconductor substrate 12 continues to be etched down to the second surface 12b.
  • a groove 54 is formed in the second zone 28, and the depth of the groove 54 is exemplified by more than 0 micrometers to about 10 micrometers. Then, a heat tempering process is performed.
  • an amorphous silicon layer 56 is selectively formed on the second surface 12b of the semiconductor substrate 12, which is preferably an intrinsic amorphous silicon layer, and then formed on the intrinsic amorphous silicon layer 56.
  • a doped amorphous silicon layer 58, an amorphous silicon layer 56 and a doped amorphous silicon layer 58 cover the second side 12b of the semiconductor substrate 12 and are filled in the recess 54.
  • the method for forming the intrinsic amorphous silicon layer 56 and the doped amorphous silicon layer 58 is to deposit an amorphous silicon layer by, for example, a CVD method, and then doping the doping such as ion implantation, thermal diffusion, ion shower doping, or the like.
  • the crystalline silicon layer 58 is not limited thereto.
  • the polarity of the doping type of the doped amorphous silicon layer 58 must be opposite to the polarity of the doping type of the doped polysilicon layer 16, and doping of one of the doped amorphous silicon layer 58 and the doped polysilicon layer 16
  • the polarity of the type is the same as the polarity of the doping type of the semiconductor substrate 12.
  • the amorphous silicon layer 56 may have a thickness of about 10 nm or less, preferably about 5 nm
  • the doped amorphous silicon layer 58 may have a thickness of about 2 to 20 nm, preferably about 10 nm, for example, doped.
  • the thickness of the hetero-amorphous silicon layer 58 is preferably twice or more than the thickness of the amorphous silicon layer 56, but is not limited thereto.
  • the partially doped amorphous silicon layer 58 is removed, for example, the partially doped amorphous silicon layer 58 outside the recess 54 is removed, and the remaining doped amorphous silicon layer 58 is formed into a doped region. 32.
  • the method of removing the partially doped amorphous silicon layer 58 includes, for example, laser ablation, or a screen printing mask or a photolithography process, and a dry etching process or the like, but is not limited thereto.
  • the doping type of doping region 32 has the same polarity as the doping type of semiconductor substrate 12, while the doping type of doping region 32 is opposite to the polarity of doped polysilicon layer 16.
  • the doped polysilicon layer 16 has a P + -type doping
  • the doping region 32 has a polarity and doping.
  • the polysilicon layer 16 has opposite polarities and is of the same polarity as the semiconductor substrate 12, and the doped region 32 has an N + type doping.
  • the doped polysilicon layer 16 has an N + -type doping
  • the doping region 32 has a polarity opposite to that of the doped polysilicon layer 16 and has the same polarity as the semiconductor substrate 12 Then, the doping region 32 has a P + type doping.
  • the doped region 32 serves as a BSF element of the solar cell 10.
  • the solar cell 10 of the present embodiment further includes an amorphous silicon layer 56 disposed between the first insulating layer 38 and the second insulating layer 40.
  • the side of the doped polysilicon layer 16 is between the second insulating layer 40 and between the doped region 32 and the semiconductor substrate 12.
  • the patterned second insulating layer 40 and the first electrode 22 and the second electrode 24 may be sequentially formed on the second surface 12b of the semiconductor substrate 12, and on the semiconductor substrate.
  • the first surface 12a of 12 forms a doped layer 14 and an anti-reflective layer 30, wherein the doped layer 14 preferably has the same doping type polarity as the semiconductor substrate 12 to serve as an FSF element.
  • FIG. 14 is a cross-sectional view showing the structure of a solar cell according to a fourth embodiment of the present invention.
  • the solar cell 10 of the present embodiment has only one insulating layer 20 having a first opening 34 exposing a partially doped polysilicon layer 16 and a second opening 36 exposing a partially doped region 32, Therefore, the first electrode 22 and the second electrode 24 can be in contact with the doped polysilicon layer 16 and the doping region 32 via the first opening 34 and the second opening 36, respectively.
  • different materials may be selected as needed to form the insulating layer 20.
  • a material for making the insulating layer 20 have a negative fixed oxidizing charge may be selected. If it is desired to improve the saturation current of the N + -type doping region 32, and the P+-type doped polysilicon layer 16 is exemplified, A material which causes the insulating layer 20 to have a positive fixed oxidation charge can be selected.
  • the doped polysilicon layer 16 has an N + -type doping and the doped region 32 has a P + -type doping as an example, it is desirable to improve the saturation current of the doped polysilicon layer 16 having an N + -type doping.
  • a material which has a positive type of fixed oxidation charge for the insulating layer 20 is selected. If it is desired to improve the doping region 32 having a P + -type doped saturation current, the insulating layer 20 may have a material having a negative fixed oxidation charge. The material of the positive or negative fixed oxidation charge selected for use may be further described in FIG. 1 and will not be described again.
  • the manufacturing method of the solar cell 10 of the present embodiment is similar to that of the third embodiment, except that the fabrication of the first insulating layer is omitted in the process, and the doped polysilicon layer 16 and the oxide layer 18 are patterned after the doped polysilicon layer 16 is formed.
  • the semiconductor substrate 12 in the second region 28 is exposed, and the amorphous silicon layer 56 and the doped amorphous silicon layer 58 are sequentially formed, the doped amorphous silicon layer 58 is patterned to form the doped region 32, and then
  • the insulating layer 20 is formed, and then the insulating layer 20 is patterned to form a first opening 34 and a second opening 36.
  • the thickness of the insulating layer 20 may be, for example, about 20 to 500 nanometers, and the detailed fabrication method of each component is not described herein. .
  • each doping element in the solar cells of the third embodiment to the fifth embodiment of the present invention and the fixed oxidation charge correspondence relationship between the first and second insulating layers are not limited to one type, and reference may be made to The description of the first embodiment has a variety of corresponding designs.
  • the semiconductor substrate has the same doping type as the doped layer, and the doped polycrystalline One of the silicon layer and the doped region has the same polarity as the doping type of the semiconductor substrate, and the other of the doped polysilicon layer and the doped region has an opposite doping type polarity, preferably, doping
  • the polarity of the doping type of the polysilicon layer is opposite to the polarity of the doping type of the semiconductor substrate, and the first insulating layer contains a fixed oxidation charge having a polarity opposite to that of the doped polysilicon layer, and the second insulating layer contains a fixed oxidation
  • the polarity of the charge is opposite to that of the doped region, and different materials are used to form the first and second insulating layers, but not limited thereto.
  • the polarity of the fixed oxidation charge carried by the insulating layer may be opposite to the polarity of the doping element to provide the field effect passivation effect, but not limited thereto.
  • the dopants selected for the doping type, the material of the insulating layer, and the order of fabrication of the front and back side elements in the solar cell please refer to the relevant description in the first embodiment.
  • the positive and negative electrodes of the solar cell of the present invention are disposed on the second surface of the semiconductor substrate, i.e., opposite to the back side of the light receiving surface, the amount of incident light can be increased.
  • the front side and the back side of the solar cell are respectively provided with FSF and BSF elements, and the doped polysilicon layer is used as an emitter, which can greatly improve the light conversion efficiency.
  • a plurality of insulating layers are disposed on the surface of the doped polysilicon layer and the doped region, for example, two insulating layers with opposite fixed oxidation charges are provided, which can respectively provide field effect passivation to the doped polysilicon layer and the doped region. The effect is to reduce the occurrence of composite current. Therefore, according to the structure and manufacturing method of the solar cell of the present invention, the overall photoelectric conversion efficiency of the solar cell can be greatly improved.

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Abstract

提供一种太阳能电池及其制作方法。该太阳能电池包括设于半导体基底（12）第一表面（12a）的掺杂层（14）、设于半导体基底（12）的第二表面（12b）的第一区（26）的掺杂多晶硅层（16）、设于半导体基底（12）第二表面（12b）的第二区（28）的掺杂区（32）、以及覆盖掺杂多晶硅层（16）与掺杂区（32）表面的绝缘层（20）。绝缘层暴露了部分掺杂多晶硅层与部分掺杂区，使掺杂多晶硅层（16）与掺杂区（32）经由绝缘层（20）的开口分别连接于第一电极（22）与第二电极（24）。半导体基底（12）与掺杂层（14）具有第一掺杂类型，掺杂多晶硅层（16）与掺杂区（32）之其中一者具有第二掺杂类型，其中另一者则具有第一掺杂类型，且第二掺杂类型相反于第一掺杂类型。太阳能电池的光电转换效率得到提高。

Description

太阳能电池及其制作方法 技术领域
本发明涉及一种太阳能电池及其制作方法，尤其涉及一种具有高光电转换效率的太阳 能电池及其制作方法。 背景技术
现今人类使用的能源主要来自于石油， 但由于地球的石油资源有限， 因此近年来对于 替代能源的需求与日俱增， 而在各式替代能源中， 太阳能已成为目前最具发展潜力的绿色 能源。
然而， 受限于高制作成本、 工艺复杂与光电转换效率不佳等问题， 太阳能电池的发展 仍待进一步的突破。光电转换效率不佳的原因包括： 设在太阳能电池前侧的金属电极会遮 挡部分入射光线， 以及掺杂元件的少数载子容易发生复合 （recombination) 等。 因此， 如 何制作出具有高光电转换效率的太阳能电池，而使太阳能取代现行高污染与高风险的能源 实为当前能源产业最主要的发展方向之一。 发明内容
本发明的目的之一在于提供一种太阳能电池及其制作方法，通过太阳能电池中各掺杂 元件与绝缘层相对位置的设计， 可以提高太阳能电池的光电转换效率。
本发明公开一种太阳能电池， 其包括一半导体基底、 一掺杂层、 一掺杂多晶硅层、一 掺杂区、 一绝缘层、 至少一第一电极以及至少一第二电极。 半导体基底具有第一表面与第 二表面， 其中第二表面具有第一区与第二区， 且半导体基底具有一第一掺杂类型。 掺杂层 位于半导体基底的第一表面， 并具有该第一掺杂类型。掺杂多晶硅层设置于半导体基底的 第二表面上的第一区内， 且暴露出半导体基底的第二表面的第二区。掺杂区设置于半导体 基底的第二表面的第二区中， 其中， 掺杂多晶硅层与掺杂区之其中一者具有一第二掺杂类 型， 而掺杂多晶硅层与掺杂区之其中另一者具有该第一掺杂类型， 且第二掺杂类型相反于 第一掺杂类型。绝缘层覆盖了掺杂多晶硅层与掺杂区的表面， 且具有至少一第一开口暴露 出部分掺杂多晶硅层以及至少一第二开口暴露出部分掺杂区。 第一电极设置于绝缘层表 面， 且经由第一开口连接于掺杂多晶硅层， 而第二电极亦设置于绝缘层表面， 且经由第二 开口连接于掺杂区。
本发明还公开一种制作太阳能电池的方法， 包括下列步骤。 首先提供一半导体基底， 其具有第一表面与第二表面， 其中第二表面具有第一区与第二区， 且半导体基底具有一第 一掺杂类型。于半导体基底的第二表面的第一区上形成一掺杂多晶硅层， 其暴露出半导体 基底的第二表面的第二区。于暴露出的半导体基底的部分第二表面的第二区中形成至少一 掺杂区， 其中掺杂多晶硅层与掺杂区之其中一者具有一第二掺杂类型， 而掺杂多晶硅层与 掺杂区其中之另一者具有该第一掺杂类型， 且第二掺杂类型相反于第一掺杂类型。然后形 成一绝缘层， 覆盖掺杂多晶硅层与掺杂区表面， 绝缘层具有至少一第一开口暴露出部分掺 杂多晶硅层以及至少一第二开口暴露出部分掺杂区。然后于绝缘层表面形成一金属层， 其 包括至少一第一电极与一第二电极，其中第一电极经由绝缘层的第一开口而与掺杂多晶硅 层相接触， 而第二电极经由绝缘层的第二开口而与掺杂区相接触。 于半导体基底的第一表 面形成一掺杂层覆盖第一表面上， 其中掺杂层具有该第一掺杂类型。
由于本发明太阳能电池的掺杂多晶硅层作为射极或背表面电场，通过其多晶硅与半导 体基底所形成的接面可以减少载子复合问题， 进而提高光电转换效率。 附图说明
图 1至图 7为本发明太阳能电池的制作方法的第一实施例的流程示意图。
图 8为本发明太阳能电池的第二实施例的结构剖面示意图。
图 9至图 13为本发明太阳能电池制作方法的第三实施例的工艺示意图。
图 14为本发明太阳能电池的第四实施例的结构剖面示意图。
其中， 附图标记说明如下：
10太阳能电池 12半导体基底
12a第一表面 12b第二表面
12c粗糙化结构 14掺杂层
16掺杂多晶硅层 18氧化层
20绝缘层 22第一电极
24第二电极 26第一区
28第二区 30抗反射层
32掺杂区 34第一开口
36第二开口 38第一绝缘层
40第二绝缘层 42第一次开口
44第二次开口 46第三次开口
48第四次开口 50网版印刷掩模
52金属层 54凹槽
56非晶硅层 58掺杂非晶硅层 具体实施方式
为使本领域普通技术人员能更进一步了解本发明， 下文特列举本发明的优选实施例， 并配合所附附图， 详细说明本发明的构成内容及所欲达成的功效。
请参考图 1， 图 1为本发明太阳能电池的第一实施例的剖面示意图。 本实施例中， 本 发明太阳能电池 10为指叉式背接触 （interdigitated back contact, IBC ) 太阳能电池， 其包 括一半导体基底 12、一掺杂层 14、 一掺杂多晶硅层 16、一掺杂区 32、 一绝缘层 20、 至少 一第一电极 22以及至少一第二电极 24。其中，半导体基底 12具有第一表面 12a与第二表 面 12b，第一表面 12a为受光面（light-receiving side)，可视为太阳能电池 10的前侧（front side)， 而第二表面 12b相对于第一表面 12a而设于半导体基底 12的另一侧， 可视为太阳 能电池 10的侧 （rear side) 。 也就是说， 上述二侧位于半导体基底 12的不同侧且是相反 侧。 第二表面 12b定义有第一区 26与第二区 28， 如图 1所示， 第一区 26与第二区 28的 图案大体上由左而右互相交错设置为范例， 但不限于此。 于其它实施例中， 第一区 26与 第二区 28也可分占半导体基底第二表面 12b的左右二半边或具有其它合适的设置方式。 掺杂层 14位于半导体基底 12的第一表面 12a， 且掺杂层 14与半导体基底 12具有相同极 性的第一掺杂类型， 掺杂层 14的掺杂浓度优选高于半导体基底 12的掺杂浓度， 例如半导 体基底 12为轻掺杂， 而掺杂层 14为重掺杂， 但不以此为限。 掺杂多晶硅层 16设于半导 体基底 12的第二表面 12b上的第一区 26内， 暴露出半导体基底 12的第二表面 12b的第 二区 28，而掺杂区 32设于半导体基底 12的第二表面 12b的第二区 28之中。如图 1所示， 掺杂多晶硅层 16位于第二表面 12b上， 而掺杂区 32大体上位于半导体基底 12的第二表 面 12b以下， 例如， 掺杂区 32设于第二表面 12b以下的半导体基底 12中。 掺杂多晶硅层 16与掺杂区 32由左而右两者交错间隔设置为范例。 掺杂多晶硅层 16与掺杂区 32两者其 中之一具有第一掺杂类型，而掺杂多晶硅层 16与掺杂区 32其中的另一者具有第二掺杂类 型， 且第二掺杂类型相反于第一掺杂类型， 掺杂多晶硅层 16与掺杂区 32优选皆具有重掺 杂浓度。绝缘层 20设于半导体基底 12的第二表面 12b上， 具有至少一第一开口 34 (图中 显示三个第一开口 34作为说明）与至少一第二开口 36 (图中显示二个第二开口 36作为说 明） ， 分别暴露出部分掺杂多晶硅层 16与部分掺杂区 32。 第一电极 22设于绝缘层 20的 表面， 通过第一开口 34而与掺杂多晶硅层 16接触， 而第二电极 24亦设于绝缘层 20的表 面， 通过第二开口 36而与掺杂区 32接触。 此外， 第一电极 22与第二电极 24彼此互不相 连接， 两者其中之一用来作为太阳能电池 10的正极， 而另一者用来作为太阳能电池 10的 负极。 因此， 太阳能电池 10的正负电极皆位于电池的背侧， 亦即相反于受光侧第一表面 12a的第二表面 12b上。
在优选实施例中， 绝缘层 20为复合绝缘层， 包括至少一第一绝缘层 38与一第二绝缘 层 40， 其中， 第一绝缘层 38覆盖于掺杂多晶硅层 16表面， 且具有至少一第一次开口 42 与至少一第二次开口 44， 第一次开口 42暴露出部分掺杂多晶硅层 16， 而第二次开口 44 暴露出掺杂区 32。 第二绝缘层 40覆盖了第一绝缘层 38与部分掺杂区 32， 且具有至少一 第三次开口 46与至少一第四次开口 48。 其中， 第三次开口 46对应于第一次开口 42， 第 四次开口 48对应于第二次开口 48， 因此， 第三次开口 46暴露出部分掺杂多晶硅层 16， 而第四次开口 48暴露出部分掺杂区 32。 由图 1可知， 第一绝缘层 38的第一次开口 42与 第二绝缘层 40的第三次开口 46构成了绝缘层 20的第一开口 34，而第一绝缘层 38的第二 次开口 44与第二绝缘层 40的第四次开口 48构成了绝缘层 20的第二开口 36。 举例而言， 本实施例中第一绝缘层 38与第二绝缘层 40包含不同的材料， 优选地， 第一绝缘层 38所 包含固定氧化电荷 (或称为固定氧化层电荷或氧化层固定电荷， fixed oxide charge)的极性相 反于第二绝缘层 40所包含固定氧化电荷的极性， 优选地， 第一绝缘层 38的固定氧化电荷 的极性与掺杂多晶硅层 16的掺杂极性相反，而第二绝缘层 40的固定氧化电荷的极性与掺 杂区 32的掺杂极性相反， 借此， 第一绝缘层 38与第二绝缘层 40可分别对掺杂多晶硅层 16和掺杂区 32中的少数载子提供场效应钝化 (field effect passivation)功能， 避免少数载子 的复合， 但不限于此。 在本实施例中， 可通过选择第一绝缘层 38与第二绝缘层 40的材料 来决定第一绝缘层 38与第二绝缘层 40的固定氧化电荷的极性。举例而言， 欲使第一绝缘 层 38及第二绝缘层 40之其中一者带有正型固定氧化电荷 (positive fixed oxide charge)时， 可使用硅氧化物 （SiOx) 、 氮硅化物 （SiNx) 、 氮氧化硅 (SiON)、 氧化钇 (Y0X)、 其它合适 的材料、或上述至少二者的组合来制作，另一方面，则可使用氧化铝 (Α10χ)、氮化铝 (Α1ΝΧ)、 氮氧化 ,吕 (aluminum oxynitride, A10N)、 氟化,吕 (aluminum fluoride, A1FX)、 氧化,合 (hafiiium oxide, HfOx)、 氮掺杂的氧化铪 (nitrogen-doped HfOx)、 其它合适的材料、 或上述至少二者 的组合来制作第一绝缘层 38及第二绝缘层 40其中之另一者， 以使其带有负型固定氧化电 荷 (negative fixed oxide charge), 但不以此为限。
本实施例的半导体基底 12、掺杂层 14、掺杂多晶硅层 16、掺杂区 32的掺杂类型的极 性以及第一绝缘层 38与第二绝缘层 40的固定氧化电荷的极性举例说明如下。例如， 在本 发明的优选实施例中， 半导体基底 12为 N型掺杂， 掺杂层 14为 N+型掺杂， 掺杂多晶硅 层 16为 P+型掺杂， 而掺杂区 32为 N+型掺杂（下文介绍本发明太阳能电池 10制作方法的 第一实施例亦以此设计为例来说明， 如图 1所示） 。 为了让第一绝缘层 38与第二绝缘层 40能提供场效应钝化功能，因此第一绝缘层 38配合掺杂多晶硅层 16的掺杂类型而包含负 型固定氧化电荷， 而第二绝缘层 40配合掺杂区 32的掺杂类型而包含正型固定氧化电荷。 在优选实施例中，太阳能电池 10还可选择性包括一氧化层 18，设置于半导体基底 12的第 二表面 12b的第一区 26中， 位于半导体基底 12的第二区 28、 掺杂多晶硅层 16与半导体 基底 12之间， 当作穿隧氧化层 (tunnel oxide layer)使用。 一般而言， 氧化层 18具有够薄的 厚度， 以增加电子直接穿隧过氧化层 18的机率， 进而增加光电转换效率。 氧化层 18的厚 度可能为约 5到 20埃 (Angstroms, A)。 在某些实施例， 氧化层 18的厚度为约 10埃。 优选 地， 氧化层 18厚度为约 15埃。 由于 P+型掺杂的掺杂多晶硅层 16、 穿隧氧化层 18与 N型 掺杂的半导体基底 12， 提供了类似异质接面（heterojimction) 的结构， 能大幅降低饱和电 流， 因此能有效地提高光电转换效率。 此外， 因为掺杂层 14与掺杂区 32的掺杂类型的极 性相同于半导体基底 12， 因此掺杂层 14作为前表面电场 (front side field, FSF)元件， 掺杂 区 32作为背表面电场 (back side field, BSF)元件， 而具有 P+型掺杂的掺杂多晶硅层 16作 为太阳能电池 10的射极 （emitter) 。
在本发明的另一优选实施例中， 半导体基底 12为 P型掺杂， 掺杂层 14为 P+型掺杂， 掺杂多晶硅层 16为 N+型掺杂， 而掺杂区 32为 P+型掺杂， 且第一绝缘层 38包含正型固定 氧化电荷， 而第二绝缘层 40包含负型固定氧化电荷， 此时掺杂多晶硅层 16作为太阳能电 池 10的射极（emitter)， 且因为半导体基底 12与掺杂多晶硅层 16之间具有 PN接面而同 样能使太阳能电池 10有良好的光电转换效率。 此外， 在其他实施例中， 也可以设计半导 体基底 12为 N型掺杂， 掺杂层 14为 N+型掺杂， 掺杂多晶硅层 16为 N+型掺杂， 掺杂区 32为 P+型掺杂， 第一绝缘层 38包含正型固定氧化电荷， 而第二绝缘层 40包含负型固定 氧化电荷， 则掺杂多晶硅层 16当作背表面电场 (BSF)、 掺杂区 32为射极 (emitter)以及掺杂 层 14当作前表面电场 (FSF); 或者， 在又一其他实施例中， 半导体基底 12为 P型掺杂， 掺杂层 14为 P+型掺杂， 掺杂多晶硅层 16为 P+型掺杂， 而掺杂区 32为 N+型掺杂， 第一绝 缘层 38包含负型固定氧化电荷， 而第二绝缘层 40包含正型固定氧化电荷， 则掺杂多晶硅 层 16 当作背表面电场 (BSF)、 掺杂区 32为射极 (emitter)以及掺杂层 14 当作前表面电场 (FSF)。 然而， 本发明中各掺杂元件的掺杂类型和第一绝缘层 38与第二绝缘层 40的固定 氧化电荷极性之间的对应关系并不以上述实施例为限。
此外， 本实施例的太阳能电池 10 可选择性地包括一抗反射 （antireflection coating, ARC )层 30设在掺杂层 14的表面上， 但不以此为限。 此外， 抗反射层可为单层或多层结 构， 其材料包含氮化硅、 氧化硅、 氮氧化硅、 氧化鋅、 氧化钛、 铟锡氧化物 (ιτο)、 氧化 铟、氧化秘 (bismuth oxide) 氧化锡 (stannic oxide) 氧化浩 (zirconium oxide), 氧化,合 (hafiiium oxide) 氧化锑 (antimony oxide)、 氧化礼 (gadolinium oxide)、 其它合适的材料、 或上述至少 二种的混合物。 再者， 为了增加入光量， 半导体基底 12与掺杂层 14的接面可选择性地具 有粗糙化 (textured)处理， 例如使第一表面 12a具有粗糙化结构 12c， 以进一步提高光电转 换效率， 但不以此为限。
下文将介绍本发明太阳能电池的第一实施例的制作方法， 为了简化说明， 在以下实施 例中使用相同的符号来标注相同的元件， 不再对重复部分进行赘述。 请参考图 2至图 7， 图 2至图 7为本发明太阳能电池的制作方法的第一实施例的流程示意图。 请参考图 2， 首 先提供一半导体基底 12，其可为结晶性（crystalline)半导体基底或多晶性（polycrystalline) 半导体基底。 半导体基底 12的厚度举例为约 50微米至约 300微米。 半导体基底 12优选 为具有第一掺杂类型的基底， 本实施例中， 半导体基底 12举例为 N掺杂基底。 可选择性 对半导体基底 12进行清洗并移除切割损伤层。接着， 可选择性地在半导体基底 12的第二 表面 12b形成薄氧化层 18作为穿隧氧化层， 厚度范围为约 5埃 （angstrom) 至 20埃， 优 选地约为 15埃， 氧化层 18举例可包含硅氧化物材料， 通过臭氧氧化工艺或高温氧化工艺 而形成， 但不以此为限。 然后， 在氧化层 18表面形成掺杂多晶硅层 16， 厚度为约 50至 500纳米， 但不限于此。 掺杂多晶硅层 16可具有第一掺杂类型或第二掺杂类型， 优选地， 掺杂多晶硅层 16具有第二掺杂类型， 其极性相反于半导体基底 12的第一掺杂类型， 例如 掺杂多晶硅层 16 具有 P+型掺杂， 优选掺杂浓度的范围为约 1019至 1021原子 /平方厘米 ( atom/cm2) ， 但不限于此。 制作掺杂多晶硅层 16 的方式举例如下： 可先以化学气相沉 积法（chemical vapor deposition, CVD)在氧化层 18表面形成多晶硅层， 然后再进行离子 注入工艺， 因本实施例的掺杂多晶硅层 16具有 P+型掺杂， 因此可包含 P型掺杂物， 例如 硼或硼化合物， 但不以此为限。 掺杂多晶硅层 16的其他形成方法举例如以低压化学气相 沉积 （low pressure chemical vapor deposition, LPCVD) 直接形成具有 P+型掺杂的掺杂多 晶硅层 16，或是先形成非晶硅层，再经由激光退火等方式使非晶硅层再结晶形成多晶硅层， 然后再进行离子注入工艺， 掺杂多晶硅层 16的形成方法不限于前文所述。
接着， 选择性地在掺杂多晶硅层 16的表面形成第一绝缘层 38， 为了使第一绝缘层 38 对掺杂多晶硅层 16 中的少数载子具有场效应钝化效果， 因此， 当掺杂多晶硅层 16具有 P+型掺杂为范例时， 本实施例的第一绝缘层 38优选包含负型固定氧化电荷， 而第一绝缘 层 38的材料可选用上述实施例所述的材料， 本实施例以氧化铝为范例， 例如三氧化二铝， 但不以此为限。 当以掺杂多晶硅层 16具有 N+型掺杂为范例时， 本实施例的第一绝缘层 38 优选包含正型固定氧化电荷， 而第一绝缘层 38的材料可选用上述所述的材料， 本实施例 以硅氧化物为范例， 例如 Si02， 但不以此为限。 第一绝缘层 38的厚度范围可为约 20至 400纳米， 但不限于此。 在本发明的其他实施例中， 也可选择忽略制作第一绝缘层 38。
然后请参考图 3，进行图案化氧化层 18、掺杂多晶硅层 16以及第一绝缘层 38的步骤。 此图案化工艺举例可先利用网版印刷掩模 （screen printing mask) 50或者是光阻掩模在第 一绝缘层 38表面定义出欲保留的第一绝缘层 38的部分， 亦即半导体基底 12的第二表面 12b的第一区 26， 暴露出第二表面 12b的第二区 28内的第一绝缘层 38。 其中， 光阻掩模 的形成方法可为曝光显影方法或喷墨涂布方法。然后再如图 4所示， 移除被网版印刷掩模 50或光阻掩模暴露的部分第一绝缘层 38、掺杂多晶硅层 16与氧化层 18。此移除方法举例 为湿蚀刻或干蚀刻工艺， 优选为湿蚀刻工艺， 例如以氢氟酸 （HF)与硝酸 (HN03)的混合液 进行移除。 此外， 此移除步骤可以一次完成， 或分多次完成， 例如在不同蚀刻工艺中分次 依序移除部分第一绝缘层 38、 部分掺杂多晶硅层 16以及部分氧化层 18， 但不以此为限。 图案化第一绝缘层 38、掺杂多晶硅层 16与氧化层 18的步骤亦可利用激光方式来完成，但 不以此为限。 因此， 剩下的第一绝缘层 38、掺杂多晶硅层 16与氧化层 18位于半导体基底 12的第二表面 12b上的第一区 26之内， 暴露出半导体基底 12的第二表面 12b的第二区 28， 其中第二表面 12b的第二区 28可具有多个点状 （dot) 、 条状 （strip) 图案或其它合 适的图案。 由图 4可知， 在此图案化工艺之后， 剩下的氧化层 18设置于半导体基底 12的 第二表面 12b的第一区 26与掺杂多晶硅层 16之间。值得注意的是， 在移除暴露出的氧化 层 18后，仍可继续移除暴露出的第二表面 12b的第二区 28表面的部分半导体基底 12，使 第二区 28内的半导体基底 12中形成凹槽， 凹槽的深度范围为约 0至 10微米， 但不以此 为限。 本实施例以凹槽深度为约 0微米来举例说明， 亦即图案化工艺在移除第二区 28中 的氧化层 18即停止， 而不额外于半导体基底 12中形成凹槽。
接着， 请参考图 5， 移除网版印刷掩模 50后， 在暴露出的半导体基底 12的第二表面 12b的第二区 28 内形成掺杂区 12， 本实施例的掺杂区 12具有第一掺杂类型， 例如具有 N+型掺杂， 其极性相反于掺杂多晶硅层 16的掺杂极性。 形成掺杂区 32的方法举例如下： 由于第一绝缘层 38具有第二次开口 44暴露第二表面 12b的第二区 28，因此可利用第一绝 缘层 38当作离子注入掩模， 先对半导体基底 12的第二表面 12b进行离子注入， 再用回火 或热扩散方式形成掺杂区 32， 或直接利用热扩散方式使掺杂物扩散进入第二区 28的半导 体基底 12中，或直接利用离子淋浴掺杂 (ion shower doping)方式使掺杂物进入第二区 28的 半导体基底 12中， 但不限于此。 此外， N+型掺杂物可为例如磷、 砷、 锑或上述材料的化 合物， 但不以此为限。 掺杂区 12的深度举例为约 0.5至 1微米， 掺杂浓度举例为 1019至 1021atom/cm2, 但不以此为限。
然后， 请参考图 6， 在半导体基底 12的第二面 12b—侧全面形成第二绝缘层 40， 覆 盖第一绝缘层 38与掺杂区 32。 为了使第二绝缘层 40对掺杂区 32中的少数载子具有场效 应钝化效果， 本实施例的第二绝缘层 40所选用的固定氧化电荷的极性， 需要与掺杂多晶 硅层 16极性及掺杂区 32极性做搭配。 举例而言： 当掺杂多晶硅层 16具有 P+型掺杂， 掺 杂区 32具有 N+掺杂， 且第一绝缘层 38选用包含负型固定氧化电荷的材料为范例时， 第 二绝缘层 40优选包含正型固定氧化电荷， 第二绝缘层 40的材料可选用如上所述的材料， 例如硅氧化物或氮硅化物， 但不以此为限。 当掺杂多晶硅层 16具有 N+型掺杂， 掺杂区 32 具有 P+掺杂， 且第一绝缘层 38选用包含正型固定氧化电荷的材料为范例时， 第二绝缘层 40优选包含负型固定氧化电荷， 第二绝缘层 40的材料可选用如上所述的材料， 例如氧化 铝， 但不以此为限。第二绝缘层 40的厚度范围可为约 20至 400纳米，但不限于此。接着， 对第二绝缘层 40和第一绝缘层 38进行图案化工艺， 移除部分第二绝缘层 40和部分第一 绝缘层 38， 使第一绝缘层 38具有第一次开口 42， 第二绝缘层 40具有第三次开口 46和第 四次开口 48， 暴露出部分掺杂多晶硅层 16与部分掺杂区 32。此图案化工艺可利用网版印 刷掩模先于第二绝缘层 40定义出第三次开口 46和第四次开口 48的位置， 再利用蚀刻工 艺分次或依次地移除部分第二绝缘层 40和第一绝缘层 38， 在其他实施例中， 也可利用光 刻暨蚀刻工艺 (或称为光阻掩模)来进行此图案化工艺， 但不以此为限。 如图 6所示， 第三 次开口 46对应于第一次开口 42， 两者构成了绝缘层 20的第一开口 34， 暴露出部分掺杂 多晶硅层 16， 而第四次开口 48对应于第二次开口 44， 两者构成了绝缘层 20的第二开口 36， 暴露出部分掺杂区 32。 在其他实施例中， 也可先于第一绝缘层 38中形成第一次开口 38，再形成第二绝缘层 40，然后图案化第二绝缘层 40以于第二绝缘层 40中形成第三次开 口 46和第四次开口 48。
请参考图 7， 在半导体基底 12的第二面 12b—侧全面形成金属层 52， 其材料可为各 式导电性佳的金属， 例如铝、 银、 铂、 金、 铜或上述材料的合金， 或是其它合适的材料， 但不以此为限。 接着， 对金属层 52进行图案化工艺， 移除部分金属层 52以形成至少一第 一电极 22与至少一第二电极 24，第一电极 22与第二电极 24分别通过绝缘层 20的第一开 口 34与第二开口 36而连接于掺杂多晶硅层 16与掺杂区 32。再者，第一电极 22与第二电 极 24的形成方法亦可使用涂布导电胶方法， 导电胶的导电材料包含铝、 银、 镍、 铜或上 述材料的合金， 或是其它合适的材料， 但不以此为限。 其中涂布导电胶的方法包含网印方 法、 喷墨方法或其它合适的方法。 第一电极 22与第二电极 24的厚度、 面积与图案可视需 求加以调整， 并不限于图 7所绘示者。
请再参考图 1， 之后， 可选择性地对半导体 12的第一表面 12a进行粗糙化处理， 然后 在第一表面 12a形成掺杂层 14， 其具有第一掺杂类型， 相同于半导体基底 12的掺杂类型 的极性， 例如掺杂层 14为重掺杂的 N+型掺杂， 其形成方法可例如前述的掺杂区 32， 包括 如使用外部离子扩散的方式将掺杂物扩散进半导体基底 12的第一表面 12a中， 但不以此 为限， 此外， 形成掺杂层 14所使用的掺杂物可选用类似掺杂区 32的掺杂物， 相同部分不 再赘述。 在其他实施例中， 掺杂层 14也可为另外于半导体基底 12的第一表面 12a形成的 掺杂层， 例如为掺杂的非晶硅层、 结晶层或多晶硅层， 但不以此为限。 最后， 可选择性地 在掺杂层 14上全面形成一抗反射层 30， 覆盖半导体基底 12的第一表面 12a， 其中抗反射 层 30可为单层或多层结构， 且其材料可选用上述图 1中抗反射层 30的材料。 借此， 完成 本发明太阳能电池 10主要结构的制作。
值得注意的是， 本发明太阳能电池中各掺杂元件的掺杂类型与第一、第二绝缘层的固 定氧化电荷极性并不限于图 1所示者， 不同的掺杂类型选用不同的掺杂物， 不同极性的固 定氧化电荷亦选用不同的氧化材料来制作绝缘层， 如前文所举例， 因此不再赘述。 此外， 虽然在上述本实施例中是先制作完太阳能电池背侧的元件， 才制作前侧的元件， 但在其他 实施例中， 亦可先制作太阳能电池前侧的元件， 例如掺杂层与抗反射层， 之后再制作太阳 能电池背侧的元件， 例如氧化层、 掺杂多晶硅层、 掺杂区、 绝缘层、 第一电极与第二电极 等。 此外， 又在其他实施例中， 并不限定必须先做完太阳能电池前侧或背侧的元件才制作 另一侧的元件， 半导体基底第一表面与第二表面上的各元件可穿插制作， 并不限定先后制 作顺序。
本发明的制作太阳能电池的方法并不以上述实施例为限。下文将继续介绍本发明太阳 能电池及其制作方法的其它实施例， 且为了便于比较各实施例的相异处并简化说明， 下文 中使用相同的附图标记标注相同的元件， 且主要针对各实施例的相异处进行说明， 而不再 对重复部分进行赘述。
请参考图 8， 图 8为本发明太阳能电池的第二实施例的结构剖面示意图。 与第一实施 例不同的是，本实施例的太阳能电池 10只有一层绝缘层 20，其具有第一开口 34暴露出部 分掺杂多晶硅层 16以及第二开口 36暴露出部分掺杂区 32， 使得第一电极 22与第二电极 24可分别经由第一开口 34与第二开口 36而与掺杂多晶硅层 16和掺杂区 32相接触。为了 使绝缘层 20具有钝化层的功能， 可以依需要来选用不同的材料来制作绝缘层 20， 例如， 若希望改善 P+型掺杂多晶硅层 16的饱和电流， 且 N+型掺杂区 32为范例时， 可以选用使 绝缘层 20具有负型固定氧化电荷的材料， 若希望改善 N+型掺杂区 32的饱和电流， 且 P+ 型掺杂多晶硅层 16为范例时， 则可以选用使绝缘层 20具有正型固定氧化电荷的材料。 另 外， 若掺杂多晶硅层 16具有 N+型掺杂， 搭配的掺杂区 32具有 P+型掺杂为范例时， 希望 改善掺杂多晶硅层 16具有 N+型掺杂的饱和电流， 则可以选用使绝缘层 20具有正型固定 氧化电荷的材料， 若希望改善的是掺杂区 32具有 P+型掺杂的饱和电流， 则可以选用使绝 缘层 20具有负型固定氧化电荷的材料。 所选用的正型或负型固定氧化电荷的材料可再查 看图 1中所述， 不再赘述。 本实施例的太阳能电池 10的制作方法与前一实施例相类似， 唯工艺中省略第一绝缘层的制作，在形成掺杂多晶硅层 16后就对掺杂多晶硅层 16和氧化 层 18进行图案化工艺， 暴露出第二区 28中的半导体基底 12， 并在形成掺杂区 32之后， 形成绝缘层 20， 再图案化绝缘层 20以形成第一开口 34与第二开口 36， 其中， 绝缘层 20 的厚度举例可为约 20至 500纳米， 各元件的详细制作方法不在此赘述。
请参考图 9至图 13，图 9至图 13为本发明太阳能电池制作方法的第三实施例的工艺 示意图， 其中图 13显示了本发明太阳能电池的第三实施例的结构剖面示意图。 如图 9所 示， 在本实施例中， 先对半导体基底 12的第一表面 12a进行粗糙化处理， 使第一表面 12a 具有粗糙化结构 12c， 然后再进行第二表面 12b上元件的制作。 类似于第一实施例中图 2 至图 3中所显示的工艺， 依序在半导体基底 12的第二表面 12b形成氧化层 18、 掺杂多晶 硅层 16与第一绝缘层 38， 然后图案化氧化层 18、 掺杂多晶硅层 16与第一绝缘层 38， 例 如以网版印刷掩模 50当作蚀刻掩模， 对暴露的氧化层 18、 掺杂多晶硅层 16、 第一绝缘层 38与半导体基底 12的第二表面 12的第二区 28进行蚀刻， 如图所示， 此蚀刻工艺在移除 氧化层 18后， 继续向下蚀刻半导体基底 12的第二表面 12b， 以在第二表面 12b的第二区 28中形成凹槽 54， 凹槽 54的深度举例为大于 0微米至约 10微米。 然后， 进行一热回火 工艺。
接着， 请参考图 11， 在半导体基底 12的第二面 12b选择性地形成一非晶硅层 56， 其 优选为一本征非晶硅层， 然后再于本征非晶硅层 56上形成一掺杂非晶硅层 58， 非晶硅层 56与掺杂非晶硅层 58覆盖半导体基底 12的第二面 12b， 并填入凹槽 54中。 本征非晶硅 层 56与掺杂非晶硅层 58的形成方法举例如利用 CVD方法先沉积非晶硅层， 然后再以如 离子注入、 热扩散、 离子淋浴掺杂等方式形成掺杂非晶硅层 58， 但不限于此。掺杂非晶硅 层 58的掺杂类型的极性必须和掺杂多晶硅层 16的掺杂类型的极性相反，且掺杂非晶硅层 58与掺杂多晶硅层 16其中一者的掺杂类型的极性与半导体基底 12的掺杂类型的极性相 同。 非晶硅层 56的厚度可为约 10纳米以下， 优选为约 5纳米， 而掺杂非晶硅层 58的厚 度可为约 2至 20纳米， 优选为约 10纳米， 与例而言， 掺杂非晶硅层 58厚度优选为非晶 硅层 56厚度的两倍或大于两倍， 但不限于此。
然后请参考图 12， 移除部分掺杂非晶硅层 58， 例如将凹槽 54外的部分掺杂非晶硅 层 58移除， 使剩下的掺杂非晶硅层 58形成掺杂区 32。 移除部分掺杂非晶硅层 58的方法 例如包括利用激光消熔（ablation)，或是以网版印刷掩模或光刻工艺并配合干蚀刻工艺等， 但不以此为限。在优选实施例中， 掺杂区 32的掺杂类型与半导体基底 12的掺杂类型具有 相同的极性， 而掺杂区 32的掺杂类型与掺杂多晶硅层 16的极性相反。 举例而言， 若半导 体基底 12具有 N型掺杂， 掺杂多晶硅层 16具有 P+型掺杂， 且掺杂区 32的极性要与掺杂 多晶硅层 16的极性相反， 并要与半导体基底 12极性相同， 则掺杂区 32具有 N+型掺杂。 若半导体基底 12具有 P型掺杂， 掺杂多晶硅层 16具有 N+型掺杂， 且掺杂区 32的极性要 与掺杂多晶硅层 16的极性相反， 并与半导体基底 12极性相同， 则掺杂区 32具有 P+型掺 杂。 掺杂区 32作为太阳能电池 10的 BSF元件， 此时， 本征非晶硅层 56的存在能使掺杂 区 32提供较优良的 BSF效果。 因此， 本实施例与第一实施例之其中一个主要不同处， 在 于本实施例的太阳能电池 10还包括了非晶硅层 56， 设置于第一绝缘层 38与第二绝缘层 40之间、 掺杂多晶硅层 16的侧边与第二绝缘层 40之间、 以及掺杂区 32与半导体基底 12 之间。
请参考图 13， 之后如前述的第一实施例， 可依序在半导体基底 12的第二表面 12b形 成图案化的第二绝缘层 40以及第一电极 22与第二电极 24， 并于半导体基底 12的第一表 面 12a形成掺杂层 14与抗反射层 30， 其中掺杂层 14优选与半导体基底 12有相同的掺杂 类型的极性， 以作为 FSF元件。借此， 即完成了本发明太阳能电池 10的主要元件的制作。 本实施例中各主要元件的制作方法、材料与膜层厚度类似于第一实施例， 可参阅第一实施 例的描述， 在此不再赘述。
请参考图 14， 图 14为本发明太阳能电池的第四实施例的结构剖面示意图。 与第三实 施例不同的是，本实施例的太阳能电池 10只有一层绝缘层 20，其具有第一开口 34暴露出 部分掺杂多晶硅层 16以及第二开口 36暴露出部分掺杂区 32， 因此第一电极 22与第二电 极 24可分别经由第一开口 34与第二开口 36而与掺杂多晶硅层 16和掺杂区 32相接触。 类似地， 为了使绝缘层 20具有钝化层的功能， 可以依需要而选用不同的材料以制作绝缘 层 20， 例如，若希望改善 P+型掺杂多晶硅层 16的饱和电流， 且 N+型掺杂区 32为范例时， 可以选用使绝缘层 20具有负型固定氧化电荷的材料， 若希望改善 N+型掺杂区 32的饱和 电流， 且 P+型掺杂多晶硅层 16为范例时， 则可以选用使绝缘层 20具有正型固定氧化电 荷的材料。 另外， 若掺杂多晶硅层 16具有 N+型掺杂， 搭配的掺杂区 32具有 P+型掺杂为 范例时， 希望改善掺杂多晶硅层 16具有 N+型掺杂的饱和电流， 则可以选用使绝缘层 20 具有正型固定氧化电荷的材料， 若希望改善的是掺杂区 32具有 P+型掺杂的饱和电流， 则 可以选用绝缘层 20具有负型固定氧化电荷的材料。 所选用的正型或负型固定氧化电荷的 材料可再查看图 1所述， 不再赘述。 本实施例的太阳能电池 10的制作方法与第三实施例 相类似， 唯工艺中省略第一绝缘层的制作， 在形成掺杂多晶硅层 16后就对掺杂多晶硅层 16和氧化层 18进行图案化工艺， 暴露出第二区 28中的半导体基底 12， 再依序制作非晶 硅层 56与掺杂非晶硅层 58， 图案化掺杂非晶硅层 58以形成掺杂区 32， 然后形成绝缘层 20， 再对绝缘层 20进行图案化， 形成第一开口 34与第二开口 36， 其中， 绝缘层 20的厚 度举例可为约 20至 500纳米， 各元件的详细制作方法不在此赘述。
值得注意的是， 本发明第三实施例至第五实施例太阳能电池中的各掺杂元件的掺杂 类型与第一、第二绝缘层的固定氧化电荷对应关系并不限于一种， 可参考第一实施例的叙 述而具有多种对应设计。 优选地， 半导体基底与掺杂层具有相同的掺杂类型， 而掺杂多晶 硅层和掺杂区之其中一者和半导体基底的掺杂类型的极性相同，且掺杂多晶硅层和掺杂区 之其中另一者具有相反的掺杂类型极性， 优选地， 掺杂多晶硅层的掺杂类型的极性相反于 半导体基底的掺杂类型的极性，且第一绝缘层包含的固定氧化电荷的极性相反于掺杂多晶 硅层， 而第二绝缘层包含的固定氧化电荷的极性相反于掺杂区， 并依此选用不同的材料来 制作第一与第二绝缘层， 但不以此为限。 若只有一层绝缘层， 则可依需要设计绝缘层所带 有的固定氧化电荷的极性相反于欲提供场效应钝化效果的掺杂元件的极性， 但不以此为 限。 关于掺杂类型所选用的掺杂物、 绝缘层的材料以及太阳能电池中前、 背侧元件的制作 顺序请参考第一实施例中的相关叙述。
由于本发明太阳能电池的正、负极皆设置于半导体基底的第二表面， 亦即相反于受光 面的背侧， 所以能提高入射光量。 在优选实施例中， 太阳能电池的前侧与背侧分别设有 FSF与 BSF元件， 且以掺杂多晶硅层当作射极， 可以大幅提高光线转换效率。 再者， 在掺 杂多晶硅层和掺杂区表面设置了多层绝缘层，例如设置两层带有相反固定氧化电荷的绝缘 层，可以分别对掺杂多晶硅层和掺杂区提供场效应钝化效果，减少复合电流的发生。因此， 根据本发明太阳能电池的结构和制作方法， 可以大幅提升太阳能电池的整体光电转换效 率。
以上所述仅为本发明的优选实施例， 凡依本发明权利要求所做的均等变化与修饰， 皆 应属本发明的涵盖范围。

Claims

权利要求
1. 一种太阳能电池， 包括：
一半导体基底，具有一第一表面与一第二表面，其中该半导体基底具有一第一掺杂类 型， 该第二表面具有一第一区与一第二区；
—掺杂层， 位于该半导体基底的该第一表面， 其具有该第一掺杂类型；
一掺杂多晶硅层，设置于该半导体基底的该第二表面的该第一区上，且暴露出该半导 体基底的该第二表面的该第二区；
一掺杂区，设置于该半导体基底的该第二表面的该第二区中，其中该掺杂多晶硅层与 该掺杂区其中一者具有一第二掺杂类型，而该掺杂多晶硅层与该掺杂区其中另一者具有该 第一掺杂类型， 且该第二掺杂类型相反于该第一掺杂类型；
一绝缘层覆盖该掺杂多晶硅层与该掺杂区表面，并具有至少一第一开口暴露出部分该 掺杂多晶硅层与至少一第二开口暴露出部分该掺杂区；
至少一第一电极， 设置于该绝缘层表面， 并经由该第一开口连接于该掺杂多晶硅层; 以及
至少一第二电极， 设置于该绝缘层表面， 并经由该第二开口连接于该掺杂区。
2. 如权利要求 1所述的太阳能电池， 其中该绝缘层包括：
一第一绝缘层， 设置于该掺杂多晶硅层表面上， 并具有一第一次开口， 以暴露出部分 该掺杂多晶硅层与一第二次开口以暴露出部分该掺杂区； 以及
一第二绝缘层，覆盖该第一绝缘层与该掺杂区，并具有一第三次开口对应于该第一次 开口， 以暴露出部分该掺杂多晶硅层与一第四次开口对应于该第二次开口， 以暴露出部分 该掺杂区；
其中该第一绝缘层与该第二绝缘层所包含的材料不相同，该第一次开口与该第二次开 口构成该第一开口， 且该第三次开口与该第四次开口构成该第二开口。
3. 如权利要求 2所述的太阳能电池， 其中该第一绝缘层包含固定氧化电荷的极性相 反于该第二绝缘层包含固定氧化电荷的极性。
4. 如权利要求 3所述的太阳能电池， 其中当该掺杂区具有该第一掺杂类型且该掺杂 多晶硅层具有该第二掺杂类型时，该第一绝缘层所具有的固定氧化电荷的极性相反于该第 二掺杂类型的极性， 而该第二绝缘层所具有的固定氧化电荷的极性相反于该第一掺杂类 型。
5. 如权利要求 3所述的太阳能电池， 其中当该掺杂多晶硅层具有该第一掺杂类型且 该掺杂区具有该第二掺杂类型时，该第一绝缘层所具有的固定氧化电荷的极性相反于该第 一掺杂类型的极性， 而该第二绝缘层所具有的固定氧化电荷的极性相反于该第二掺杂类 型。
6. 如权利要求 2所述的太阳能电池， 其还包括一非晶硅层， 设置于该第一绝缘层与 该第二绝缘层之间、该掺杂多晶硅层的侧边与该第二绝缘层之间以及该掺杂区与该半导体 基底之间。
7. 如权利要求 1所述的太阳能电池， 其中该半导体基底的该第二表面的该第二区中 还包含至少一凹槽， 且该掺杂区设置于该凹槽中。
8. 如权利要求 7所述的太阳能电池， 其还包括一非晶硅层， 设置于该掺杂多晶硅层 与该绝缘层之间以及该掺杂区与该半导体基底之间。
9. 如权利要求 1所述的太阳能电池， 还包括一氧化层层， 设置于该半导体基底的该 第二表面的该第二区与该掺杂多晶硅层之间。
10. 如权利要求 1所述的太阳能电池， 还包括一抗反射层设于该掺杂层的表面上。
11.一种制作太阳能电池的方法， 包括：
提供一半导体基底，其具有一第一表面与一第二表面，其中该第二表面具有一第一区 与一第二区， 且该半导体基底具有一第一掺杂类型；
于该半导体基底的该第二表面的该第一区上形成一掺杂多晶硅层，且暴露出该半导体 基底的该第二表面的该第二区；
于暴露出的该半导体基底的部分该第二表面的该第二区中形成至少一掺杂区，其中该 掺杂多晶硅层与该掺杂区其中一者具有一第二掺杂类型，而该掺杂多晶硅层与该掺杂区其 中另一者具有该第一掺杂类型， 且该第二掺杂类型相反于该第一掺杂类型；
形成一绝缘层，覆盖该掺杂多晶硅层与该掺杂区表面，该绝缘层具有有至少一第一开 口暴露出部分该掺杂多晶硅层与至少一第二开口暴露出部分该掺杂区；
于该图案化的绝缘层表面形成一金属层， 该金属层包括：
至少一第一电极， 经由该第一开口而与该掺杂多晶硅层相接触； 以及
至少一第二电极， 经由该第二开口而与该掺杂区相接触； 以及
于该半导体基底的该第一表面形成一掺杂层覆盖该第一表面上，其中该掺杂层具有该 第一掺杂类型。
12. 如权利要求 11所述的制作太阳能电池的方法， 还包括在形成该掺杂多晶硅层之 前， 先形成一氧化层设置于该半导体基底的该第二表面的该第二区与该掺杂多晶硅层之 间。
13. 如权利要求 11所述的制作太阳能电池的方法， 其中形成该绝缘层覆盖该掺杂多 晶硅层与该掺杂区表面，并具有该第一开口暴露出部分该掺杂多晶硅层与该第二开口暴露 出部分该掺杂区的步骤包括：
形成一第一绝缘层， 设置于该掺杂多晶硅层表面上， 并具有一第一次开口， 以暴露出 部分该掺杂多晶硅层与一第二次开口以暴露出部分该掺杂区； 以及
形成一第二绝缘层，覆盖该第一绝缘层与该掺杂区，并具有一第三次开口对应于该第 一次开口， 以暴露出部分该掺杂多晶硅层与一第四次开口对应于该第二次开口， 以暴露出 部分该掺杂区； 其中该第一绝缘层与该第二绝缘层所包含的材料不相同，该第一次开口与该第二次开 口构成该第一开口， 且该第三次开口与该第四次开口构成该第二开口。
14. 如权利要求 13所述的制作太阳能电池的方法， 其中该第一绝缘层包含固定氧化 电荷的极性相反于该第二绝缘层包含固定氧化电荷的极性。
15. 如权利要求 14所述的制作太阳能电池的方法， 其中当该掺杂区具有该第一掺杂 类型且该掺杂多晶硅层具有该第二掺杂类型时，该第一绝缘层所具有的固定氧化电荷的极 性相反于该第二掺杂类型的极性，而该第二绝缘层所具有的固定氧化电荷的极性相反于该 第一掺杂类型。
16. 如权利要求 14所述的太阳能电池的制造方法， 其中当该掺杂多晶硅层具有该第 一掺杂类型且该掺杂区具有该第二掺杂类型时，该第一绝缘层所具有的固定氧化电荷的极 性相反于该第一掺杂类型的极性，而该第二绝缘层所具有的固定氧化电荷的极性相反于该 第二掺杂类型。
17. 如权利要求 13所述的制作太阳能电池的方法， 其还包括在形成该掺杂区之前， 先形成一非晶硅层，设置于该第一绝缘层与该第二绝缘层之间、该掺杂多晶硅层的侧边与 该第二绝缘层之间以及该掺杂区与该半导体基底之间。
18. 如权利要求 11所述的制作太阳能电池的方法， 还包含形成一凹槽于该半导体基 底的该第二表面的该第二区中， 且该掺杂区形成于该凹槽中。
19. 如权利要求 18所述的制作太阳能电池的方法， 其还包括在形成该掺杂区之前， 先形成一非晶硅层，设置于该掺杂多晶硅层与该绝缘层之间以及该掺杂区与该半导体基底 之间。
20. 如权利要求 11所述的制作太阳能电池的方法，其中该掺杂区为一掺杂非晶硅层。
21. 如权利要求 11所述的制作太阳能电池的方法， 还包括在该半导体基底的该第二 表面形成一抗反射层， 覆盖该掺杂层。
PCT/CN2012/083615 2012-10-10 2012-10-26 太阳能电池及其制作方法 WO2014056268A1 (zh)

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