WO2014029223A1 - 一种兼具反向导通的异质结构场效应晶体管及其制作方法 - Google Patents

一种兼具反向导通的异质结构场效应晶体管及其制作方法 Download PDF

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WO2014029223A1
WO2014029223A1 PCT/CN2013/076328 CN2013076328W WO2014029223A1 WO 2014029223 A1 WO2014029223 A1 WO 2014029223A1 CN 2013076328 W CN2013076328 W CN 2013076328W WO 2014029223 A1 WO2014029223 A1 WO 2014029223A1
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source electrode
gate
substrate
heterojunction
field effect
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刘扬
魏进
姚尧
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Sun Yat Sen University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the invention belongs to the technical field of semiconductor devices, and in particular relates to a heterostructure field effect transistor having both reverse conduction and a manufacturing method thereof.
  • GaN materials have strong polarization effects, and AlGaN/GaN grown in the polarization direction
  • the heterojunction interface forms a high concentration and high electron mobility two-dimensional electron gas ( 2DEG ) due to polarization effects, making AlGaN/GaN heterostructure field effect transistors (HFETs) ) With extremely low on-resistance, it is ideal for making power switching devices.
  • GaN is a wide bandgap semiconductor, it can operate at temperatures above 500 °C. Therefore GaN devices A wide range of application environments. Under the launch and promotion of research projects around the world, GaN The development of monolithic forbidden semiconductor materials and devices has achieved rapid development. Many semiconductor manufacturers in the world have successively introduced high-power, high-frequency, high-temperature wide-bandgap semiconductor products, and their application fields are expanding.
  • GaN-based power switching devices mainly include A1GaN / GaN HFET (HFET), GaN. Structures such as MOSFETs and MIS-HFETs. Among them, AIGaN / GaN HFET has the advantages of simple process, mature technology, excellent forward conduction characteristics and high operating frequency. The most interesting device structure in GaN power switching devices. As shown in FIG. 1 , it is a schematic structural diagram of a prior art AlGaN/GaN HFET device; wherein, 1 - substrate, 2 - Buffer layer, 3 - epitaxial layer, 4 - barrier layer, 5 - ohmic contact source electrode, 6 - gate, 8 - ohm contact drain electrode. In conventional AlGaN/GaN HFETs In the device, the epitaxial layer 3 is a GaN thin film, and the barrier layer 4 is an AlGaN thin film.
  • the epitaxial layer 3 is a GaN thin film
  • the barrier layer 4 is an AlGaN
  • A1GaN / GaN HFET As a switching device used in power electronic circuits, a diode is often anti-parallel across the switching device, and its function generally includes providing a freewheeling circuit (freewheeling diode) for the main circuit current after the switching device is turned off. To prevent possible reverse voltage from causing damage to the switching device.
  • Existing A1GaN / GaN HFET It has a forward conduction characteristic and cannot achieve reverse diode conduction characteristics. Therefore, in practice, a diode must be connected in anti-parallel to increase system cost.
  • the object of the present invention is to increase the reverse diode conduction characteristic on the basis of the forward conduction characteristic of the heterostructure field effect transistor, which can Heterostructure field effect transistor
  • the reverse diodes are no longer connected in parallel, providing a kind of reverse-conduction that saves chip area, reduces test and package costs, improves reverse-conduction performance, improves system reliability, and reduces power consumption. of Heterostructure field effect transistor and its fabrication method.
  • a heterostructure field effect transistor having a reverse conducting relationship comprising a substrate, a buffer layer, an epitaxial layer and a barrier layer in order from bottom to top; An epitaxial layer and a barrier layer form a heterojunction; an ohmic contact source electrode, a gate electrode and an ohmic contact drain electrode are disposed on the barrier layer of the heterojunction; and a source is further disposed on the barrier layer of the heterojunction electrode.
  • the substrate is a GaN substrate, a SiC substrate, a Si substrate, a GaAs substrate, GeSi Substrate or sapphire substrate.
  • the heterojunction is an AlGaN/GaN heterojunction, an AlGaAs/GaAs heterojunction, InAlGaAs/GaAS Heterojunction, InP/InGaAs Heterojunction, InP/GaAs Heterojunction, InAlAs/InGaAs Heterojunction, AlGaN/GaN Heterojunction, InAlN/GaN heterojunction or InAlGaN/GaN heterojunction.
  • barrier layer / epitaxial layer heterojunction that is, for example, an AlGaN/GaN heterojunction is represented as a barrier layer AlGaN, the epitaxial layer is GaN; the AlGaAs/GaAs heterojunction is represented by the barrier layer being AlGaAs and the epitaxial layer being GaAs, and the others are understood in the same manner.
  • the metal material of the ohmic contact source electrode is a combination of one or more of the following: Titanium, aluminum, nickel, gold, platinum, rhodium, molybdenum, niobium, tantalum, cobalt, zirconium or tungsten;
  • the source electrode is a Schottky contact source
  • the metal material is a combination of one or more of the following: Titanium, aluminum, magnesium, silver, lead, indium, palladium, iridium, zirconium or cobalt.
  • the source electrode is a P-type material forming a PN junction, or a PN junction is combined with a Schottky contact to form a JBS Composite contact.
  • the source electrode is connected to the ohmic contact source electrode through a metal lead; or the source electrode is connected to the ohmic contact source electrode across the gate.
  • the ohmic contact source electrode, the source electrode and the gate are isolated by a dielectric material.
  • the gate is a normally-on gate or a normally-off gate, a structure-based gate of the gate, a normally-on gate, a normally-off gate, a F ion-implanted normally-off gate, a concave gate, and The gate of the p-type cap layer or the MIS type gate.
  • the gate and the source electrode are defined by the Schottky contact on the barrier layer; the ohmic contact source electrode is connected to the source electrode.
  • the gate is defined by a Schottky contact on the barrier layer, and the second source may be performed together or separately, wherein the metal selected by the second source is the same as or different from the gate metal, or a metal having a different work function is formed.
  • Composite electrode
  • the substrate is a GaN substrate, a SiC substrate, a Si substrate, a GaAs substrate, GeSi substrate or sapphire substrate.
  • the epitaxial growth method is a metal organic chemical vapor deposition method or a molecular beam epitaxy method.
  • the working principle of the heterostructure field effect transistor of the present invention assuming that the source voltage is 0V
  • a positive voltage is applied to the drain electrode, and the device can first achieve a forward conduction between the ohmic contact drain electrode and the ohmic contact source like a conventional heterostructure field effect transistor.
  • Open When the voltage applied to the gate is less than the threshold voltage when the device is turned off, the two-dimensional electron gas under the gate region of the device is depleted, and a negative voltage is applied to the drain, and the device is between the source electrode and the ohmic contact drain electrode. Turn-on enables conduction diode characteristics. This allows the device to have conduction characteristics in both forward and reverse directions.
  • a heterostructure field effect transistor that has a reverse conducting function.
  • the present invention increases the diode conduction characteristics in the reverse direction compared to the prior art heterostructure field effect transistors. Only need to be in the barrier layer
  • the surface is designed with two sources, which can be achieved without adding any complicated process steps.
  • Parallel diodes reduce the cost by eliminating parallel diodes.
  • An enhanced or depleted heterojunction field effect transistor with reverse conduction capability can be easily obtained as needed .
  • the manufacturing method of the invention has fewer steps and simple process; and the working principle of the invention is easy to implement.
  • FIG. 1 is a schematic structural view of a prior art AlGaN/GaN HFET device
  • FIG. 2 is a schematic structural view of a heterostructure field effect transistor according to Embodiment 1 of the present invention.
  • Figure 3 is the first step in the fabrication of the device structure shown in Figure 2;
  • Figure 4 is the second step of the fabrication of the device structure shown in Figure 2;
  • Figure 5 is the third step of the fabrication of the device structure shown in Figure 2;
  • Embodiment 2 of the present invention is a schematic structural view of Embodiment 2 of the present invention.
  • Figure 7 is a schematic structural view of Embodiment 3 of the present invention.
  • Figure 8 is a schematic structural view of Embodiment 4 of the present invention.
  • Fig. 9 is a schematic structural view of a fifth embodiment of the present invention.
  • FIG. 2 is a schematic view showing the structure of a reverse conducting AlGaN/GaN HFET device according to the present invention.
  • the substrate 1 , the buffer layer 2 , the epitaxial layer 3 , and the barrier layer 4 are sequentially arranged from bottom to top; the epitaxial layer 3 and the barrier layer 4 form a heterojunction; and the barrier layer 4 on the heterojunction Set
  • the ohmic contact source electrode 5, the gate electrode 6, the source electrode 7, and the ohmic contact drain electrode 8 are provided.
  • the epitaxial layer 3 is a GaN thin film
  • the barrier layer 4 is an AlGaN thin film.
  • the AlGaN film and the GaN film form an AlGaN/GaN heterojunction;
  • the gate 6 is a Schottky gate, and the source electrode 7 is a Schottky source electrode; wherein the Schottky source electrode and the ohmic contact source electrode 5 Connected.
  • FIG. 3 to Figure 5 show the implementation of the structure shown in Figure 2.
  • the specific implementation steps are as follows:
  • a buffer layer 2 and an epitaxial layer are sequentially grown on the substrate 1 by chemical vapor deposition or molecular beam epitaxy.
  • GaN thin film, barrier layer 4 AlGaN thin film, GaN thin film and AlGaN thin film form a GaN/AlGaN heterojunction structure.
  • the ohmic contact source electrode 5 and the ohmic contact drain electrode 8 are defined on the surface of the AlGaN film, and evaporation is performed.
  • the Ti/Al/Ni/Au alloy serves as an ohmic contact source electrode 5 and an ohmic contact drain electrode 8 metal, and is annealed to form an ohmic contact.
  • the gate electrode 6 and the Schottky source electrode region are defined on the surface of the AlGaN film, and Ni/Au is evaporated.
  • the Schottky metal of the Schottky metal of the gate electrode 6 and the Schottky source electrode is connected to the ohmic contact source electrode 5. This step can also be made in two steps, defining and fabricating the gates separately. Metal and Schottky source electrode metal.
  • the second source electrode 12 is divided into two portions, a first source electrode 11 and a second source electrode 12, a first source electrode 11 and a second source electrode 12. Prepared by two steps.
  • the first source electrode 11 and the second source electrode 12 are composite Schottky source electrodes formed of metals having different work functions, and the first source electrode 11 and the second source electrode 12 are respectively connected to the ohmic contact source electrode. 5 connected.
  • FIG. 7 1 - substrate, 2 - buffer layer, 3 - epitaxial layer, 4 - barrier layer, 5 - Ohmic contact source electrode, 6 - gate, 7 - source electrode, 8 - ohmic contact drain electrode, 9 - dielectric material, 10 - gate metal; in this embodiment epitaxial layer 3 is InGaAs
  • the thin film and the barrier layer 4 are InAlAs thin films, and the heterojunction composed of the epitaxial layer 3 and the barrier layer 4 is an InAlAs/InGaAs heterojunction; the source electrode 7 is Schottky source electrode.
  • the implementation method of the embodiment shown in FIG. 5 is similar to the implementation method of the embodiment shown in FIG. 2, except that the gate 6 is changed to MIS.
  • the gate electrode may be formed by a diffusion or etching method to form a recess structure in the barrier layer, and then deposit a dielectric material, and then fabricate a MIS gate.
  • Figure 8 1 - substrate, 2 - buffer layer, 3 - epitaxial layer, 4 - barrier layer, 5 - An ohmic contact source electrode, a 6-gate, a 7-source electrode, an 8-ohm contact drain electrode, a 9-dielectric material;
  • the epitaxial layer 3 is a GaN film
  • the barrier layer 4 is In the InAlN film
  • the heterojunction composed of the epitaxial layer 3 and the barrier layer 4 is an InAlN/GaN heterojunction
  • the source electrode 7 is a Schottky source electrode.
  • Figure 6 shows an implementation method and diagram of the embodiment
  • the embodiment of the illustrated embodiment is similar in that the gate 6 metal is isolated from the ohmic contact source electrode 5 and the source electrode 7 by a dielectric material or air, and the gate 6 can be prepared.
  • the dielectric material or the sacrificial layer is deposited after the metal, and the dielectric material of the ohmic contact source electrode 5 and the source electrode 7 region is removed by etching.
  • the source electrode 7 The Schottky contact source electrode is fabricated, and finally the isolation material between the gate 6 metal and the Schottky contact source electrode metal may be selected to be completely or partially removed or completely removed.
  • Figure 9 1 - substrate, 2 - buffer layer, 3 - epitaxial layer, 4 - barrier layer, 5 - Ohmic contact source electrode, 6 - gate, 7 - source electrode, 8 - ohm contact drain electrode, 9 - dielectric material, 13 - Schottky contact source electrode metal.
  • the epitaxial layer 3 is GaN.
  • the thin film and the barrier layer 4 are InAlGaN thin films, and the heterojunction composed of the epitaxial layer 3 and the barrier layer 4 is an InAlGaN/GaN heterojunction.
  • the implementation method of the embodiment shown in FIG. 7 is similar to the implementation method of the embodiment shown in FIG. 2, except that the Schottky source electrode is Schottky contact and The composite structure of the MIS structure, and in this embodiment, the Schottky contact source electrode metal 13 may be a metal or a combination of metals.

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Abstract

一种兼具反向导通的异质结构场效应晶体管及其制作方法，其场效应晶体管，由下往上依次包括衬底（1）、缓冲层（2）、外延层（3）、势垒层（4）；外延层（3）、势垒层（4）形成异质结；异质结上的势垒层（4）上设有欧姆接触源电极（5）、栅极（6）、源电极（7）和欧姆接触漏电极（8）。与传统异质结构场效应晶体管相比，通过在表面多设计一个电极实现器件反向导通，工艺简单，成本低廉，与现有异质结构场效应晶体管工艺完全兼容。在功率电路中需要续流的情况下，使用所述兼具反向导通功能的异质结构场效应晶体管，可以不用并联反向导通二极管，因此节约大量芯片面积，减小测试与封装的成本，提高器件可靠性。

Description

一种兼具反向导通的异质结构场效应晶体管及其制作方法
技术领域
本发明属于半导体器件技术领域，特别涉及一种兼具反向导通的 异质结构场效应晶体管 及其制作方法 。
背景技术
随着微电子技术的发展，传统 Si 和 GaAs 半导体器件性能已接近其材料本身决定的理论极限。 GaN 与 Si 相比，具有宽禁带宽度、高临界击穿电场（高达 3MV/cm ）、高的饱和电子漂移速度和良好的热导率等优越的性能，更加适合制作高功率大容量、高开关速度的功率开关器件，成为下一代功率开关器件的理想材料。
GaN 材料具有较强的极化效应，极化方向上生长的 AlGaN/GaN 异质结的界面由于极化效应形成高浓度和高电子迁移率的二维电子气（ 2DEG ），使得 AlGaN/GaN 异质结构场效应晶体管（ HFETs ）具有极低的导通电阻，非常适合制作功率开关器件。由于 GaN 属于宽禁带半导体，其工作温度可达 500 ℃ 以上。因此 GaN 器件 有比较广的应用环境。在世界各国研究计划的启动和推动下， GaN 等宽禁带半导体材料和器件的研制获得了飞速的发展，国际上多家半导体厂商相继推出高功率、高频、高温的宽禁带半导体产品，其应用领域正不断扩展。
目前，基于 GaN 的功率 开关器件主要包括 A1GaN ／ GaN HFET (HFET) 、 GaN MOSFET 和 MIS-HFET 等结构。其中， AIGaN ／ GaN HFET 具有工艺简单、技术成熟、优良的正向导通特性和高的工作频率等优点，成为 GaN 功率开关器件中最受关注的器件结构。如图 1 所示， 是现有技术的 AlGaN/GaN HFET 器件结构示意图；其中， 1 - 衬底、 2 - 缓冲层、 3 - 外延层、 4 - 势垒层、 5 - 欧姆接触源电极 、 6 - 栅极、 8 - 欧姆接触漏电极 。 在传统的 AlGaN/GaN HFET 器件中外延层 3 为 GaN 薄膜，势垒层 4 为 AlGaN 薄膜。
A1GaN ／ GaN HFET 作为开关器件应用在电力电子电路中，常在开关器件两端反并联一个二极管，其作用一般包括在开关器件关断后为主电路电流提供续流回路 ( 续流二极管 ) 、防止可能出现的反向电压对开关器件造成损坏等。现有 A1GaN ／ GaN HFET 是具有正向导通特性，无法实现反向二极管导通特性。因而在实际应用中必须反并联一个二极管，从而增加系统成本。
发明内容
本发明目的是在 异质结构场效应晶体管 具有正向导通特性的基础上，为其增加反向二极管导通特性，可以使得在 异质结构场效应晶体管 需要反向导通的一些应用中不再并联反向二极管，提供一种节约芯片面积，减少测试与封装成本，提高反向导通性能，提高系统可靠性，降低功耗的一种兼具反向导通的 异质结构场效应晶体管 及其制 作方法 。
为实现上述目的，本发明的技术方案为：
一种兼具反向导通的 异质结构场效应晶体管 ， 由下往上依次 包括衬底 、 缓冲层、外延层和势垒层 ；所述 外延层和势垒层 形成异质结；所述异质结的 势垒层 上设有 欧姆接触源电极 、 栅极 和 欧姆接触漏电极 ；所述异质结的 势垒层上 还设有源电极。
所述衬底为 GaN 衬底、 SiC 衬底、 Si 衬底、 GaAs 衬底、 GeSi 衬底或蓝宝石衬底。
所述 异质结为 AlGaN/GaN 异质结、 AlGaAs/GaAs 异质结、 InAlGaAs/GaAS 异质结、 InP/InGaAs 异质结、 InP/GaAs 异质结、 InAlAs/InGaAs 异质结、 AlGaN/GaN 异质结、 InAlN/GaN 异质结或 InAlGaN/GaN 异质结。
其中 异质结的表达关系为： 势垒层 / 外延层异质结；即比如 AlGaN/GaN 异质结表示为势垒层为 AlGaN ， 外延层为 GaN ； AlGaAs/GaAs 异质结表示为势垒层为 AlGaAs ， 外延层为 GaAs ，其他按照相同方式理解。
所述欧姆接触源电极 的金属材料为以下一种或多种的组合： 钛、铝、镍、金、铂、铱、钼、钽、铌、钴、锆或钨；
所述 源电极为肖特基接触源极，其金属材料为以下一种或多种的组合： 钛、铝、镁、银、铅、铟、钯、钽、锆或钴。
所述 源电极 为 P 型材料形成 PN 结，或由 PN 结与肖特基接触结合形成 JBS 复合接触。
所述 源电极通过金属引线与 欧姆接触源电极 连接；或源电极横跨栅极与 欧姆接触源电极 连接， 欧姆接触源电极 、源电极与栅极通过介质材料隔离。
所述栅极为常开栅极或常关栅极，栅极的结构基栅极、常开栅极、常关栅极、 F 离子注入常关栅、凹型栅、具有 p 型覆盖层的栅极或 MIS 型栅。
本发明的又一目的是提供一种兼具反向导通的 异质结构场效应晶体管 的制作方法，包括以下步骤：
1 ）在衬底表面上依次外延生长缓冲层、外延层、势垒层；
2 ）在势垒层上通过欧姆接触定义欧姆接触源电极、欧姆接触漏电极 ；
3 ） 在势垒层上通过肖特基接触定义栅极、 源电极 ；欧姆接触源电极与 源电极 连接。
其中步骤 3 ） 在势垒层上通过肖特基接触定义栅极、第二源极可以一起进行或单独进行，其中第二源极所选取的金属与栅极金属相同或不同，或具有不同功函数的金属形成的复合电极。
更进一步的，步骤 1 ）所述 衬底为 GaN 衬底、 SiC 衬底、 Si 衬底、 GaAs 衬底、 GeSi 衬底或蓝宝石衬底。
更进一步的，步骤 1 ）所述外延生长法为 金属有机化学气相沉积法或分子束外延法。
本发明异质结构场效应晶体管的工作原理：假设源极电压为 0V ，当栅极所加电压大于阈值电压时，给漏电极施加正电压，器件可以像传统型异质结构场效应晶体管一样首先在欧姆接触漏电极和欧姆接触源极之间实现正向导通，器件开启。当器件关断时栅极所加电压小于阈值电压，器件中栅极区域下方的二维电子气被耗尽，此时给漏极施加一个负电压，器件在源电极和欧姆接触漏电极之间导通能够实现导通二极管特性。这样就使得器件在正向和反向时都具有导通特性，形成 兼具 反向导通功能的异质结构场效应晶体管。
本发明就比现有的 异质结构场效应晶体管 增加了反向时的二极管导通特性。只需要在 势垒层 表面设计两个源极，没有增加任何复杂的工艺步骤就能实现。同时在使用中比传统的 异质结构场效应晶体管 并联二极管形式少了并联二极管，降低成本。可以根据需要容易获得增强型或者耗尽型的兼具反向导通功能的 异质结构场效应晶体管 。本发明的制作方法，步骤较少，工艺简单；易实现本发明的工作原理。
附图说明
图 1 是现有技术的 AlGaN/GaN HFET 器件 结构示意图；
图 2 是本发明实施例一 的异质结构场效应晶体管 结构示意图；
图 3 是图 2 所示器件结构制作的第一步；
图 4 为图 2 所示器件结构制作的第二步；
图 5 为图 2 所示器件结构制作的第三步；
图 6 是本发明实施例二 的 结构示意图；
图 7 是本发明实施例三 的 结构示意图；
图 8 是本发明实施例四 的 结构示意图；
图 9 是本发明实施例五 的 结构示意图。
具体实施方式
实施例一
图 2 是本发明所提供的一种兼具反向导通的 AlGaN/GaN HFET 器件 结构 示意图 ； 由下往上依次 包括衬底 1 、 缓冲层 2 、外延层 3 、势垒层 4 ；所述 外延层 3 、势垒层 4 形成异质结；所述异质结上的 势垒层 4 上设有 欧姆接触源电极 5 、 栅极 6 、源电极 7 和 欧姆接触漏电极 8 。 在本实施例中外延层 3 为 GaN 薄膜，势垒层 4 为 AlGaN 薄膜， AlGaN 薄膜和 GaN 薄膜形成 AlGaN/GaN 异质结； 栅极 6 为肖特基栅极，源电极 7 为肖特基源电极；其中肖特基源电极与欧姆接触源电极 5 连接。
图 3 至图 5 是实现图 2 所示结构的实施方法， 具体的实施步骤为：
1 ）如图 3 所示，通过化学气相沉积或分子束外延法在衬底 1 上依次生长一层缓冲层 2 、外延层 3 GaN 薄膜、势垒层 4 AlGaN 薄膜， GaN 薄膜和 AlGaN 薄膜形成 GaN/AlGaN 异质结结构。
2 ）如图 4 所示，在 AlGaN 薄膜表面定义欧姆接触源电极 5 和 欧姆接触漏电极 8 区域，蒸镀 Ti/Al/Ni/Au 合金作为欧姆接触源电极 5 和 欧姆接触漏电极 8 金属，并通过退火形成欧姆接触。
3 ）如图 5 所示，在 AlGaN 薄膜表面定义栅极 6 和肖特基源电极区域，蒸镀 Ni/Au 作为栅极 6 的肖特基金属和肖特基源电极的肖特基金属，肖特基金属与欧姆接触源电极 5 相连。这一步也可以分为两个步骤制作，既分别定义与制作栅极 6 金属和肖特基源电极金属。
实施例二
图 6 中： 1 - 衬底、 2 - 缓冲层、 3 - 外延层、 4 - 势垒层、 5 - 欧姆接触源电极、 6 - 栅极、 7 -源电极、 8 - 欧姆接触漏电极、 11 -第一源电极， 12 -第二源电极；在本实施例 中外延层 3 为 GaAs 薄膜，势垒层 4 为 AlGaAs 薄膜 ，则外延层 3 和势垒层 4 组成的异质结为 AlGaAs/GaAs 异质结 ；图 4 所示的实施例的实施方法与图 2 所示实施例的实施方法类似，区别在于在制作图 2 中的源电极 7 分为两个部分第一源电极 11 与第二源电极 12 ，第一源电极 11 与第二源电极 12 通过两个步骤制备。第一源电极 11 与第二源电极 12 是不同功函数的金属形成的复合肖特基源电极，第一源电极 11 、第二源电极 12 分别与欧姆接触源电极 5 相连接。
实施例三
图 7 中： 1 - 衬底、 2 - 缓冲层、 3 - 外延层、 4 - 势垒层、 5 - 欧姆接触源电极、 6 - 栅极、 7 -源电极、 8 - 欧姆接触漏电极、 9 -介质材料， 10 -栅极金属；在本实施例中外延层 3 为 InGaAs 薄膜，势垒层 4 为 InAlAs 薄膜 ， 则外延层 3 和势垒层 4 组成的异质结为 InAlAs/InGaAs 异质结 ； 源电极 7 为 肖特基源电极。图 5 所示的实施例的实施方法与图 2 所示实施例的实施方法类似，区别在于在栅极 6 改为 MIS 栅极，可以通过分布外延或者刻蚀的方法，在势垒层形成凹槽结构，然后沉积介质材料，然后制作 MIS 栅极。
实施例四
图 8 中： 1 - 衬底、 2 - 缓冲层、 3 - 外延层、 4 - 势垒层、 5 - 欧姆接触源电极、 6 - 栅极、 7 -源电极、 8 - 欧姆接触漏电极、 9 -介质材料；在本实施例中 外延层 3 为 GaN 薄膜，势垒层 4 为 InAlN 薄膜， 则外延层 3 和势垒层 4 组成的异质结为 InAlN/GaN 异质结；源电极 7 为 肖特基源电极。图 6 所示的实施例的实施方法与图 2 所示实施例的实施方法类似，区别在于栅极 6 金属通过介质材料或空气与 欧姆接触源电极 5 及 源电极 7 金属隔离，可以在制备栅极 6 金属后沉积介质材料或牺牲层，通过刻蚀去除 欧姆接触源电极 5 和 源电极 7 区域的介质材料。最后将 源电极 7 制作肖特基接触源电极，最后可以选择全部保留或者部分去除或者全部去除栅极 6 金属与肖特基接触源电极金属之间的隔离材料。
实施例五
图 9 中： 1 - 衬底、 2 - 缓冲层、 3 - 外延层、 4 - 势垒层、 5 - 欧姆接触源电极、 6 - 栅极、 7 -源电极、 8 - 欧姆接触漏电极、 9 -介质材料、 13 -肖特基接触源电极金属。在本实施例中外延层 3为 GaN 薄膜，势垒层 4 为 InAlGaN 薄膜， 则外延层 3 和势垒层 4 组成的异质结为 InAlGaN/GaN 异质结 。
图 7 所示的实施例的实施方法与图 2 所示实施例的实施方法类似，区别在于肖特基源电极为肖特基接触与 MIS 结构的复合结构，而此实施例中，肖特基接触源电极金属 13 可以选用一种金属或多种金属的组合。

Claims (10)

  1. 一种兼具反向导通的 异质结构场效应晶体管 ， 由下往上依次 包括衬底（ 1 ） 、 缓冲层（ 2 ） 、外延层（ 3 ）和势垒层（ 4 ）；所述 外延层（ 3 ）和势垒层（ 4 ）形成异质结；所述异质结的 势垒层（ 4 ）上设有 欧姆接触源电极（ 5 ）、 栅极（ 6 ）和 欧姆接触漏电极 （ 8 ）；其特征在于所述异质结的 势垒层（ 4 ）上还设有源电极（ 7 ）。
  2. 根据权利要求书 1 所述的兼具反向导通的异质结构场效应晶体管 ，其特征在于所述衬底（ 1 ）为 GaN 衬底、 SiC 衬底、 Si 衬底、 GaAs 衬底、 GeSi 衬底或蓝宝石衬底。
  3. 根据权利要求书 1 所述的兼具反向导通的 异质结构场效应晶体管 ，其特征在于所述 异质结为 AlGaN/GaN 异质结、 AlGaAs/GaAs 异质结、 InAlGaAs/GaAS 异质结、 InP/InGaAs 异质结、 InP/GaAs 异质结、 InAlAs/InGaAs 异质结、 AlGaN/GaN 异质结、 InAlN/GaN 异质结或 InAlGaN/GaN 异质结。
  4. 根据权利要求书 1 所述的兼具反向导通的 异质结构场效应晶体管 ，其特征在于所述欧姆接触源电极（ 5 ）的金属材料为以下一种或多种的组合： 钛、铝、镍、金、铂、铱、钼、钽、铌、钴、锆或钨； 所述 源电极（ 7 ）为肖特基接触源极，其金属材料为以下一种或多种的组合： 钛、铝、镁、银、铅、铟、钯、钽、锆或钴。
  5. 根据权利要求书 1 所述的兼具反向导通的 异质结构场效应晶体管 ，其特征在于所述 源电极（ 7 ）可以 为 P 型材料形成 PN 结，或由 PN 结与肖特基接触结合形成 JBS 复合接触。
  6. 根据权利要求书 4 或 5 所述的兼具反向导通的 异质结构场效应晶体管 ，其特征在于所述 源电极（ 7 ）通过金属布线与 欧姆接触源电极（ 5 ）连接；或源电极（ 7 ）横跨栅极（ 6 ）与 欧姆接触源电极（ 5 ）连接， 欧姆接触源电极（ 5 ）、源电极（ 7 ）与栅极（ 6 ）通过介质材料隔离。
  7. 根据权利要求书 1 所述的兼具反向导通的异质结构场效应晶体管，其特征在于所述栅极（ 6 ）为常开栅极或常关栅极，栅极（ 6 ）的结构为肖特基栅极、 F 离子注入常关栅、凹型栅、具有 p 型覆盖层的栅极或 MIS 型栅。
  8. 一种兼具反向导通的 异质结构场效应晶体管 的制作方法，其特征在于包括以下步骤：
    1 ）在衬底（ 1 ）表面上依次外延生长缓冲层（ 2 ）、外延层（ 3 ）、势垒层（ 4 ）；
    2 ）在势垒层（ 4 ）上通过欧姆接触定义欧姆接触源电极（ 5 ） 、欧姆接触漏电极 （ 8 ）；
    3 ） 在势垒层（ 4 ）上通过肖特基接触定义栅极（ 6 ）、 源电极（ 7 ） ；欧姆接触源电极（ 5 ） 与 源电极（ 7 ） 连接。
  9. 根据权利要求 8 所述制作方法，其特征在于步骤 1 ）所述 衬底（ 1 ）为 GaN 衬底、 SiC 衬底、 Si 衬底、 GaAs 衬底、 GeSi 衬底或蓝宝石衬底。
  10. 根据权利要求 8 所述制作方法，其特征在于步骤 1 ）所述外延生长法为 金属有机化学气相沉积法或分子束外延法。
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