WO2014026307A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2014026307A1
WO2014026307A1 PCT/CN2012/001378 CN2012001378W WO2014026307A1 WO 2014026307 A1 WO2014026307 A1 WO 2014026307A1 CN 2012001378 W CN2012001378 W CN 2012001378W WO 2014026307 A1 WO2014026307 A1 WO 2014026307A1
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fins
semiconductor device
stack structure
gate stack
fin
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French (fr)
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马小龙
殷华湘
许森
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
    • H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
    • H10D62/8161—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW] potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a FinFET having a diamond-like fin and a quantum well and a method of fabricating the same. Background technique
  • FinFET fin field effect transistor
  • the prior art silicon Fin has a rectangular cross section due to the etching process, and the gate is correspondingly controlled. Therefore, the surface area/volume is relatively small, the gate control capability is weak, and the channel is continuous. For reduced devices, the ability to suppress short channel effects is limited.
  • an object of the present invention is to provide a FinFET having a diamond-like fin and a quantum well and a method of fabricating the same, which overcome the above drawbacks, effectively suppress short channel effects and improve carrier mobility in a channel region of a device, Thereby improving the overall performance of the device.
  • a semiconductor device comprising: a plurality of fins on a substrate, the fins extending in a first direction, and having a diamond-like cross section; a gate stack structure spanning each fin a piece, extending in a second direction; a channel region, located in each fin Below the middle gate stack structure; source and drain regions, located on each side of the gate stack structure in each fin.
  • a quantum well layer is further included between the fin and the gate stack structure.
  • the quantum well layer comprises a SiGe alloy.
  • the gate stack structure comprises a gate insulating layer of a high-k material and a gate conductive layer of a metal material.
  • the two sides of the gate stack structure on each fin further include a raised source and drain region.
  • the substrate is SOI and the fins comprise Si.
  • the present invention also provides a method of fabricating a semiconductor device, comprising: forming a plurality of fins on a substrate, wherein the fins extend in a first direction and have a diamond-like cross section; forming a gate stack structure on each of the fins, the gate The pole stack structure extends across the plurality of fins and extends in the second direction; wherein a portion of each of the fins under the gate stack structure constitutes a channel region of the device, and each of the fins is located along the gate stack structure
  • the portions on both sides in one direction constitute a source and drain region.
  • the step of forming a plurality of fins further includes: forming a plurality of fins on the substrate, wherein the fins extend in the first direction and have a rectangular cross section; forming an epitaxial layer on each of the fins; etching the epitaxial layer and the fins The sheet forms a fin having a diamond-like cross section.
  • the fins are wet-etched by KOH or TMAH.
  • the width of the middle portion of the fin-like fin is larger than the width of the bottom portion, and the top portion is an acute angle.
  • the method further includes forming a quantum well layer on the fin.
  • the quantum well layer comprises a SiGe alloy.
  • the gate stack structure comprises a gate insulating layer of a high-k material and a gate conductive layer of a metal material.
  • the method further includes: forming a gate spacer and a raised source and drain region on both sides of the gate stack structure.
  • the substrate is SOI and the fins comprise Si.
  • the corner portion of the fin is further rounded.
  • the use of the diamond-like fins improves the gate control capability to effectively suppress the short channel effect, and further utilizes the epitaxial quantum well to better limit the carriers and improve the device driving capability.
  • Figure 1 is a top plan view of a semiconductor device in accordance with the present invention.
  • FIGS. 2 to 9 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • FIG. 1 a top view of a semiconductor device in accordance with the present invention is illustrated.
  • the semiconductor device includes a plurality of fins 1 on the bottom of the SOI, the fins 1 extending in a first direction parallel to the plane of the substrate and parallel to each other.
  • the middle portion of the plurality of fins 1 constitutes a channel region 1C of the device (shown by a broken line frame), and both ends of the plurality of fins constitute a source region 1 S or a drain region 1D of the device, and have lift sources at both ends of the fins respectively.
  • Zone (or source zone contact) 1RS and lift-drain zone (or drain zone contact) 1RD are examples of the semiconductor device.
  • the gate 2 intersects the plurality of fins 1 and extends in a second direction parallel to the plane of the substrate, wherein the second direction is preferably perpendicular to the first direction.
  • the gate electrode 2 has a gate connection 2C at both ends of the plurality of fins 1 in the second direction.
  • a drawing A represents a cross-sectional view of the device along AA in the second direction of FIG. 1 (only a single fin is shown), and a drawing B represents the BB of the device along the first direction in FIG. Schematic diagram of the section (showing the fin corresponding to Figure A).
  • Substrate 10 is preferably an SOI wafer or a composite substrate having an oxide layer and a top thin Si formed on the silicon wafer.
  • the substrate 10 is photolithographically/etched until the buried oxide layer of the SOI wafer or the oxide layer in the middle of the composite substrate is exposed to form a plurality of fins 1 1 extending in parallel with each other in the first direction.
  • the fins 11 generally have a rectangular cross section, and the fins 1 1 are also distributed perpendicular to the surface of the substrate.
  • the fins 1 1 are identical to the top semiconductor material in the substrate 10, i.e., Si.
  • fins 11 may be formed by other nanowire forming processes other than etching.
  • the height of the fins 1 1 is, for example, 10 to 200 nm
  • the width in the second direction is, for example, 5 to 50 nm
  • the width in the first direction is, for example, 500 to 2000 mri.
  • the epitaxial layer 12 is formed long.
  • the epitaxial layer 12 is of the same material as the fins 1 1 and also extends in the first direction accordingly. Since the lower portion of the fins 1 1 is in contact with the insulating oxide surface of the substrate 10, the epitaxial growth grows slowly or substantially without growth at the bottom, and grows faster at the top. In addition, the growth on the (1 1 1 ) plane is slower. Thus, the resulting epitaxial layer 12 typically has a cross-section similar to a diamond.
  • the epitaxial layer 12 and the fins 1 1 are etched to form a diamond-like fin 13 which also extends in the first direction.
  • the epitaxial layer 12 and the fins 1 1 may be sequentially etched by using an anisotropic etching solution such as KOH or TMAH. Since the etching rate on the (1 1 1) crystal plane is slow, the etching stops on the (1 1 1 ) crystal plane to form a diamond-like fin 13 as shown in Fig. 4A.
  • the aforementioned so-called diamond-like shape means that the top width and the bottom width (where the width refers to the width in the second direction) are similar (for example, the top width is less than or equal to the bottom width, and preferably the vertex is an acute angle). And such a polygon whose middle width is greater than the bottom width and/or the top width.
  • a diamond-like shape is a diamond that removes a portion of the bottom (or also includes a small portion of the top removed).
  • the maximum width of the rhombic fins 13, i.e., the middle width is less than or equal to the width in the second direction of the rectangular fins 1, and thus the width of the fins 13 is preferably, for example, 4 to 40 nm.
  • the rhombic fins 13 have a higher surface area/volume ratio, can achieve a larger effective channel width per unit plane area, and have stronger gate control capability, effectively suppressing short channels. effect.
  • the corners (the apex angle, the side angle, and the bottom corner) of the fins 13 are further rounded by isotropic dry or wet etching to improve the device. reliability.
  • the quantum well layer 20 is epitaxially grown on the rhombic-like fins 13, and likewise extends in the first direction to surround the rhombic fins 13.
  • the process parameters such as pressure, temperature, and gas flow of the epitaxial growth are controlled by processes such as MBE, ALD, PECVD, etc., so that the quantum well layer 20 is uniformly wrapped on each side of the rhombic-like fins 13, and thus has a rhomboid-like shape. section.
  • the material of the quantum well layer 20 is selected from materials having a lattice constant close to Si, such as a SiGe alloy, in which the Ge content (percentage of atoms) is between 40 and 80%.
  • the quantum well layer 20 may be a single layer of SiGe or a stacked structure of a plurality of layers having different Ge contents.
  • the quantum well layer 20 utilizes energy band engineering to form a semiconductor material having a wide band gap under the conductive channel, and carriers are confined in a narrow band gap channel material for transport, thereby improving carrier mobility and thereby improving the device. Drive capability.
  • a gate extending in the second direction is formed on the quantum well layer 20.
  • the gate insulating layer 30A and the gate conductive layer 30B are sequentially deposited on the quantum well layer 20 by conventional deposition methods such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, sputtering, and the like.
  • the gate insulating layer 30A is a high-k material including, but not limited to, nitrides (eg, SiN, AlN, TiN), metal oxides (mainly subgroups and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2 0 3 ), perovskite phase oxides (eg PbZr x Ti 1-x 0 3 ( PZT ), Ba x Sr 1-x Ti0 3 ( BST ) ).
  • nitrides eg, SiN, AlN, TiN
  • metal oxides mainly subgroups and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 , La 2
  • the gate conductive layer 30B is a metal, a metal nitride, and a combination thereof, wherein the metal includes Al, Ti, Cu, Mo, W, Ta, and the metal nitride includes TiN, TaN.
  • the gate stack layers 30A/30B likewise extend in the first direction to surround the diamond-like fins 13 and the quantum well layer 20. It is worth noting that the gate stack layer spans the plurality of fins 13 as shown in FIG. 1 and thus will extend in the second direction and in the direction of AA.
  • the gate stack layer is photolithographically/etched in the first direction until the quantum well layer 20 is exposed to form a gate stack structure.
  • the quantum well layer 20 under the gate stack structure 30A/30B and the portion of the fin 13 constitute the channel region 1C of the device, and the two ends (in the first direction) respectively constitute the source region 1 of the device. S or drain 1D.
  • a gate spacer 40 is formed on the quantum well layer 20 on both sides of the gate stack structure (in the first direction). For example, PECVD, HDPCVD, sputtering, etc. are deposited and subsequently etched to form sidewalls of silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC).
  • PECVD PECVD, HDPCVD, sputtering, etc. are deposited and subsequently etched to form sidewalls of silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC).
  • a raised source region 1RS and a raised drain region 1 RD are formed on the quantum well layer 20 on both sides of the gate spacer 40 (in the first direction).
  • the formation method is, for example, an epitaxial technique such as MBE or CVD.
  • the use of the rhombic-like fin improves the gate control ability to effectively suppress the short channel effect, and further utilizes the epitaxial quantum well to better limit the carrier and improve the device driving capability.

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Abstract

一种半导体器件制造方法，包括：在衬底（10）上形成多个鳍片（13），其中鳍片（13）沿第一方向延伸并且具有类菱形截面；在每个鳍片（13）上形成栅极堆叠结构（30A/30B），栅极堆叠结构（30A/30B）横跨多个鳍片（13）并且沿第二方向延伸；其中，每个鳍片（13）中位于栅极堆叠结构（30A/30B）下方的部分构成器件的沟道区（1C），每个鳍片（13）中位于栅极堆叠结构（30A/30B）沿第一方向的两侧的部分构成源漏区（1S、1D）。采用类菱形鳍片（13）提高了栅控能力以有效抑制短沟道效应，此外利用外延量子阱（20）更好地限制载流子、提高了器件驱动能力。

Description

半导体器件及其制造方法 优先权要求
本申请要求了 2012年 8月 16日提交的、 申请号为 201210293347.0、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种具有、 类菱形鳍片以及量子阱的 FinFET及其制造方法。 背景技术
随着半导体器件的尺寸持续等比例缩小， 出现了阈值电压随沟道 长度减小而下降的问题， 也即在半导体器件中产生了短沟道效应。 为 了抑制这种短沟道效应， 业界采用了鳍片场效应晶体管 （FinFET ) 的 新结构， 也即在 SOI衬底的顶部薄硅层中形成多个相互平行的垂直于衬 底的硅鳍片 （Fin ) , 在这些硅 Fin中部形成沟道区、 以及在两端形成源 漏区， 而控制栅极则横跨这些多个硅 Fin分布。
然而， 现有技术的硅 Fin由于刻蚀制造工艺限制， 其截面均为矩形， 相应地控制栅极也与之共型， 因此表面积 /体积比较小， 栅极控制能力 较弱， 对于沟道持续缩减的器件而言， 抑制短沟道效应能力有限。
此外， 器件尺寸缩减之后， 载流子疏运问题也相应突出， 如何能 够有效限制载流子、 提高载流子迁移率， 成为制约器件驱动能力提高 的重要问题。 发明内容
有鉴于此， 本发明的目的在于提供一种具有、 类菱形鳍片以及量 子阱的 FinFET及其制造方法， 克服上述缺陷， 有效抑制短沟道效应并 且提高器件沟道区载流子迁移率， 从而改善器件整体性能。
实现本发明的上述目的， 是通过提供一种半导体器件， 包括： 衬 底上的多个鳍片， 鳍片沿第一方向延伸， 并且具有类菱形截面； 栅极 堆叠结构， 横跨每个鳍片， 沿第二方向延伸； 沟道区， 位于每个鳍片 中栅极堆叠结构下方； 源漏区， 位于每个鳍片中栅极堆叠结构两側。 其中， 鳍片与栅极堆叠结构之间还包括量子阱层。
其中， 量子阱层包括 SiGe合金。
其中， 栅极堆叠结构包括高 k材料的栅极绝缘层和金属材料的栅极 导电层。
其中， 每个鳍片上栅极堆叠结构两侧还包括抬升源漏区。
其中， 衬底为 SOI, 鳍片包括 Si。
本发明还提供了一种半导体器件制造方法， 包括： 在衬底上形成 多个鳍片， 其中鳍片沿第一方向延伸并且具有类菱形截面； 在每个鳍 片上形成栅极堆叠结构， 栅极堆叠结构横跨多个鳍片并且沿第二方向 延伸； 其中， 每个鳍片中位于栅极堆叠结构下方的部分构成器件的沟 道区， 每个鳍片中位于栅极堆叠结构沿第一方向的两侧的部分构成源 漏区。
其中， 形成多个鳍片的步骤进一步包括： 在衬底上形成多个鳍片， 其中鳍片沿第一方向延伸并且具有矩形截面； 在每个鳍片上形成外延 层； 刻蚀外延层和鳍片， 形成具有类菱形截面的鳍片。
其中， 采用 KOH或 TMAH湿法腐蚀鳍片。
其中， 类菱形截面的鳍片的中部宽度大于底部宽度， 顶部为锐角。 其中， 形成具有类菱形截面的鳍片之后、 形成栅极堆叠结构之前， 还包括在鳍片上形成量子阱层。
其中， 量子阱层包括 SiGe合金。
其中， 栅极堆叠结构包括高 k材料的栅极绝缘层以及金属材料的栅 极导电层。
其中， 形成栅极堆叠结构之后， 还包括： 在栅极堆叠结构两侧形 成栅极侧墙和抬升源漏区。
其中， 衬底为 SOI, 鳍片包括 Si。
其中， 形成具有类菱形截面的鳍片之后， 进一步对鳍片的角部进 行圆润化处理。
依照本发明的半导体器件及其制造方法， 采用类菱形鳍片提高了 栅控能力以有效抑制短沟道效应， 此外利用外延量子阱更好地限制载 流子、 提高了器件驱动能力。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1为根据本发明的半导体器件的顶视图； 以及
图 2至图 9为根据本发明的半导体器件制造方法各步骤的剖视图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "第一，，、 "第二" 、 "上" 、 "下" 、 "厚" 、 "薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
首先参照图 1 , 说明了根据本发明的半导体器件的顶视图。
如图 1所示， 半导体器件包括在 SOI村底上的多个鳍片 1 , 鳍片 1沿 平行于衬底平面的第一方向延伸并且彼此之间相互平行。 多个鳍片 1的 中部构成器件的沟道区 1C (虚线框所示） ， 多个鳍片的两端构成器件 的源区 1 S或者漏区 1D, 在鳍片的两端分别具有抬升源区 （或者源区接 触） 1RS和抬升漏区 （或者漏区接触） 1RD。 栅极 2与多个鳍片 1相交， 沿平行于衬底平面的第二方向延伸， 其中第二方向优选地与第一方向 垂直。 栅极 2沿第二方向在多个鳍片 1之外的两端具有栅极连接 2C。 在 后续附图中， 某附图 A代表器件沿图 1中第二方向的 AA，的剖面示意图 (仅示出了单条鳍片）， 某附图 B代表器件沿图 1中第一方向的 BB，的剖 面示意图 （示出了图 A对应的该条鳍片） 。
参照图 2A以及图 2B , 在衬底 10上形成多个硅鳍片。 衬底 10优选地 是 SOI晶片， 或者是在硅晶片上形成了氧化层以及顶部薄 Si的复合衬 底。光刻 /刻蚀衬底 10直至暴露 SOI晶片的埋氧层或者复合衬底中部的氧 化层， 形成了相互平行沿第一方向延伸的多个鳍片 1 1。 其中鳍片 11通 常具有矩形截面， 鳍片 1 1也垂直于衬底表面分布。 鳍片 1 1与衬底 10中 顶部半导体材料是一致的， 也即是 Si。 此外， 也可以采用刻蚀之外的其 他纳米线形成工艺， 形成鳍片 1 1。 鳍片 1 1高度例如是 10 ~ 200nm, 沿第 二方向的宽度例如是 5 ~ 50nm， 沿第一方向的宽度例如是 500 ~ 2000mri。
参照图 3A以及图 3B , 在鳍片 1 1上 （也即顶部以及侧壁上） 外延生 长形成外延层 12。 外延层 12与鳍片 1 1材质相同， 也相应地也沿第一方 向延伸。 由于鳍片 1 1下部相接的是衬底 10的绝缘氧化物表面， 因此外 延生长时在底部生长緩慢或者基本不生长， 而在顶部生长较快。 此外， 在 （ 1 1 1 ) 面上生长较慢。 因此， 最终形成的外延层 12通常具有类似于 菱形的截面。
参照图 4A以及图 4B , 刻蚀外延层 12和鳍片 1 1 , 形成类菱形鳍片 13 , 也沿第一方向延伸。 对于 Si鳍片而言， 可以采用 KOH、 TMAH等各向异 性的腐蚀液， 依次刻蚀外延层 12和鳍片 1 1。 由于（1 1 1)晶面上刻蚀速率 较慢， 因此刻蚀会停止在（ 1 1 1 )晶面上而形成如图 4A所示的类菱形鳍片 13。 其中， 前述的所谓的类菱形， 指的是顶部宽度与底部宽度 （此处 宽度均指的是沿第二方向上的宽度） 相近 （例如顶部宽度小于等于底 部宽度、 并且优选地顶点为锐角） 、 并且中部宽度大于底部宽度和 /或 顶部宽度的这样一种多边形。 简言之， 类菱形是去除了底部一部分（或 者还包括去除了顶部小部分） 的菱形。 类菱形鳍片 13的最大宽度也即 中部宽度， 要小于等于矩形鳍片 1 1的第二方向上的宽度， 因此鳍片 13 的宽度优选地例如是 4 ~ 40nm。 类菱形鳍片 13较之传统的矩形鳍片 1 1 , 提高了表面积 /体积比，可以实现单位平面面积上更大的有效沟道宽度， 同时具有更强的栅控能力， 有效抑制短沟道效应。 优选地， 形成类菱 形鳍片 13之后， 进一步采用各向同性的干法或者湿法腐蚀对鳍片 13的 角部 （顶角、 侧边夹角以及底角 ） 进行圆润化处理， 以提高器件可靠 性。
参照图 5A以及图 5B , 在类菱形鳍片 13上外延生长量子阱层 20, 同 样地沿第一方向延伸而包围类菱形鳍片 13。 通过 MBE、 ALD、 PECVD 等工艺， 控制外延生长的压力、 温度、 气流量等工艺参数， 使得量子 阱层 20均匀包裹在类菱形鳍片 13的各个侧面上， 并且因此也共型地具 有类菱形截面。 量子阱层 20的材质选用晶格常数与 Si相近地材料， 例如 SiGe合金， 其中 Ge含量 （原子数目百分比）在 40 ~ 80 %之间。 量子阱 层 20可以是 SiGe的单层， 也可以是 Ge含量不同的多层的层叠结构。 量 子阱层 20利用能带工程， 在导电沟道下方形成具有宽带隙的半导体材 料， 载流子就会被限制在窄带隙的沟道材料中输运， 提高载流子迁移 率， 从而提高器件的驱动能力。
参照图 6A以及图 6B , 在量子阱层 20上形成沿第二方向延伸的栅极 堆叠层 30A/30B。 采用 LPCVD、 PECVD、 HDPCVD、 MOCVD, MBE、 ALD、 蒸发、 溅射等常规沉积方法， 在量子阱层 20上依次沉积栅极绝 缘层 30A和栅极导电层 30B。 栅极绝缘层 30A是高 k材料， 包括但不限于 氮化物 （例如 SiN、 A1N、 TiN ) 、 金属氧化物（主要为副族和镧系金属 元素氧化物， 例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203、 La203 )、钙钛矿相氧化物（例如 PbZrxTi1-x03 ( PZT )、 BaxSr1-xTi03 ( BST ) ) 。 栅极导电层 30B是金属、 金属氮化物及其组合， 其中金属 包括 Al、 Ti、 Cu、 Mo, W、 Ta， 金属氮化物包括 TiN、 TaN。 栅极堆叠 层 30A/30B同样地沿第一方向延伸而包围类菱形鳍片 13以及量子阱层 20。 值得注意的是， 栅极堆叠层如图 1所示地横跨多个鳍片 13 , 因此将 沿第二方向以及 A A，方向延伸。
以下图 7至图 9均为沿图 1中 BB，方向的剖视图。
参照图 7， 其中， 沿第一方向光刻 /刻蚀栅极堆叠层， 直至暴露量子 阱层 20 , 而形成栅极堆叠结构。 如图 7所示， 栅极堆叠结构 30A/30B下 方的量子阱层 20以及鳍片 13的部分构成器件的沟道区 1C, (沿第一方 向的） 两端则分别构成器件的源区 1 S或者漏区 1D。
参照图 8, 在栅极堆叠结构 （沿第一方向的） 两侧的量子阱层 20上 形成栅极侧墙 40。 例如是 PECVD、 HDPCVD, 溅射等方法沉积并且随 后刻蚀形成的氮化硅、 氮氧化硅、 类金刚石无定形碳 （DLC ) 材质的 侧墙。
最后， 参照图 9， 在栅极侧墙 40 (沿第一方向的） 两侧的量子阱层 20上形成抬升源区 1RS和抬升漏区 1 RD。 形成方法例如是 MBE、 CVD 等外延技术。
依照本发明的半导体器件及其制造方法， 采用类菱形鳍片提高了 栅控能力以有效抑制短沟道效应， 此外利用外延量子阱更好地限制载 流子、 提高了器件驱动能力。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合 适的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特 定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实 一 一
ί

Claims

权 利 要 求
1. 一种半导体器件， 包括：
衬底上的多个鳍片， 鳍片沿第一方向延伸， 并且具有类菱形截面； 栅极堆叠结构， 横跨每个鳍片， 沿第二方向延伸；
沟道区， 位于每个鳍片中栅极堆叠结构下方；
源漏区， 位于每个鳍片中栅极堆叠结构两侧。
2. 如权利要求 1的半导体器件， 其中， 鳍片与栅极堆叠结构之间还 包括量子阱层。
3. 如权利要求 2的半导体器件， 其中， 量子阱层包括 SiGe合金。
4. 如权利要求 1的半导体器件， 其中， 栅极堆叠结构包括高 k材料 的栅极绝缘层和金属材料的栅极导电层。
5. 如权利要求 1的半导体器件， 其中， 每个鳍片上栅极堆叠结构两 侧还包括抬升源漏区。
6. 如权利要求 1的半导体器件， 其中， 衬底为 SOI , 鳍片包括 Si。
7. 一种半导体器件制造方法， 包括：
在衬底上形成多个鳍片， 其中鳍片沿第一方向延伸并且具有类菱 形截面；
在每个鳍片上形成栅极堆叠结构， 栅极堆叠结构横跨多个鳍片并 且沿第二方向延伸；
其中， 每个鳍片中位于栅极堆叠结构下方的部分构成器件的沟道 区， 每个鳍片中位于栅极堆叠结构沿第一方向的两侧的部分构成源漏 区。
8. 如权利要求 7的半导体器件制造方法， 其中， 形成多个鳍片的步 骤进一步包括：
在衬底上形成多个鳍片， 其中鳍片沿第一方向延伸并且具有矩形 截面；
在每个鳍片上形成外延层；
刻蚀外延层和鳍片， 形成具有类菱形截面的鳍片。
9. 如权利要求 8的半导体器件制造方法， 其中， 采用 KOH或 TMAH 湿法腐蚀鳍片。
10. 如权利要求 7或 8的半导体器件制造方法， 其中， 类菱形截面的 鳍片的中部宽度大于底部宽度， 顶部为锐角。
11. 如权利要求 7的半导体器件制造方法， 其中， 形成具有类菱形 截面的鳍片之后、 形成栅极堆叠结构之前， 还包括在鳍片上形成量子 阱层。
12. 如权利要求 11的半导体器件制造方法， 其中， 量子阱层包括
SiGe合金。
13. 如权利要求 7的半导体器件制造方法， 其中， 栅极堆叠结构包 括高 k材料的栅极绝缘层以及金属材料的栅极导电层。
14. 如权利要求 7的半导体器件制造方法， 其中， 形成栅极堆叠结 构之后， 还包括： 在栅极堆叠结构两侧形成栅极侧墙和抬升源漏区。
15. 如权利要求 7的半导体器件制造方法， 其中， 衬底为 SOI, 鳍片 包括 Si。
16. 如权利要求 7的半导体器件制造方法， 其中， 形成具有类菱形 截面的鳍片之后， 进一步对鳍片的角部进行圆润化处理。
PCT/CN2012/001378 2012-08-16 2012-10-12 半导体器件及其制造方法 Ceased WO2014026307A1 (zh)

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