WO2014024754A1 - Carte de circuit pour boîtier de semi-conducteur et procédé de fabrication de celle-ci - Google Patents

Carte de circuit pour boîtier de semi-conducteur et procédé de fabrication de celle-ci Download PDF

Info

Publication number
WO2014024754A1
WO2014024754A1 PCT/JP2013/070783 JP2013070783W WO2014024754A1 WO 2014024754 A1 WO2014024754 A1 WO 2014024754A1 JP 2013070783 W JP2013070783 W JP 2013070783W WO 2014024754 A1 WO2014024754 A1 WO 2014024754A1
Authority
WO
WIPO (PCT)
Prior art keywords
plating
semiconductor package
circuit board
semiconductor chip
mounting surface
Prior art date
Application number
PCT/JP2013/070783
Other languages
English (en)
Japanese (ja)
Inventor
英紀 岡本
良治 河合
智也 大地
太志 杉本
庸二 滝井
Original Assignee
三菱瓦斯化学株式会社
日本サーキット工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱瓦斯化学株式会社, 日本サーキット工業株式会社 filed Critical 三菱瓦斯化学株式会社
Priority to JP2014529450A priority Critical patent/JPWO2014024754A1/ja
Publication of WO2014024754A1 publication Critical patent/WO2014024754A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107—Using laser light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Definitions

  • the present invention relates to a circuit board for a semiconductor package on which a semiconductor chip is mounted, which is used for a circuit board used in an electronic device, an electric device, a computer, a communication device, and the like, and a manufacturing method thereof.
  • FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package.
  • a circuit board (100) for a semiconductor package covers a wiring board (103) in which through holes (TH) and a wiring pattern (102) are formed on an insulating base (101), and covers this.
  • a solder chip mounting surface (S2) connected to the substrate for the integrated circuit and a semiconductor chip mounting surface (S1) on which the semiconductor chip is mounted.
  • an electrode part (105) in which a part of the solder resist (104) is opened and a part of the wiring pattern (102) is exposed is formed on the semiconductor chip mounting surface (S1).
  • solder ball mounting surface (S2) On the solder ball mounting surface (S2), a part of the solder resist (104) is opened to expose a part of the wiring pattern (102), and a solder ball pad (106) is formed on the exposed wiring pattern (102).
  • a circuit board (100) for a semiconductor package is usually obtained by applying and drying a solder resist (104) on both surfaces of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2) of the wiring substrate (103). It is manufactured by exposing to UV through a mask, developing to form an opening, and providing an electrode portion (105) and a solder ball pad (106) in the opening.
  • FIGS. 7 (a) and 7 (b) are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board (100) shown in FIG.
  • the semiconductor package (900, 900 ′) shown in FIGS. 7A and 7B has the semiconductor chip (200, 200 ′) mounted on the semiconductor chip mounting surface (S1) of the circuit board for semiconductor package (100). It is formed by electrically connecting the two.
  • wire bonding, flip chip bonding, and the like can be cited as a method of electrical connection between the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ′. From the above, flip chip bonding is preferably used. In the example shown in FIGS.
  • the semiconductor package circuit board (100) and the semiconductor chip (200, 200 ') are electrically connected using flip chip bonding.
  • bumps (201, 201 ′) formed in advance on the electrode portions of the semiconductor chip (200, 200 ′) are used and electrically connected to the electrode portions (105) of the circuit board (100) for the semiconductor package. Is a way to connect.
  • the electrode part (105) of the semiconductor chip mounting surface (S1) used for flip chip bonding is called a flip chip bump pad.
  • the bumps (201, 201 ') of the semiconductor chip (200, 200') are formed by a pillar such as gold or copper or solder. FIG.
  • FIG. 7A shows an example using a semiconductor chip (200) having bumps (201) made of solder
  • FIG. 7 (b) shows a semiconductor chip (200 ′) having bumps (201 ′) made of pillars.
  • the example used is shown.
  • the bumps (201, 201 ′) of the semiconductor chip (200, 200 ′) and the semiconductor package circuit board (100) are usually mounted.
  • Flip-chip bump pads (105) are brought into contact with each other, and the electrode portions are bonded together by a treatment such as heating.
  • solder balls (300) for connecting the semiconductor package and the integrated circuit board are attached to the solder ball pads (106).
  • the solder ball (300) is generally attached by bringing the solder ball (300) into contact with the solder ball pad (106) and joining them by a process such as heating.
  • the number of electrodes of the semiconductor chip (200, 200 ′) is increased, and the bumps (201, 201 ′) formed on the electrodes are also increased in density and size.
  • the movement toward high-density mounting of semiconductor chips (200, 200 ′) is expanding.
  • FIG. 8 is a schematic view showing an example of the configuration of a semiconductor package circuit board (100 ′′) having embedded bumps
  • FIG. 9 is a semiconductor package (100 ′′) using the semiconductor package circuit board (100 ′′) of FIG. 900 ").
  • the semiconductor package circuit board (100") of FIG. 8 has a bump (107) formed by electrolytic plating on a flip chip bump pad (105).
  • the connecting surface is set at a position equal to or higher than the surface of the solder resist (104).
  • FIG. 9 shows an example in which a semiconductor chip (200 ′) having bumps (201 ′) made of pillars is used, but FIG.
  • the configuration is the same.
  • an electroplating bus line (108) is previously provided on the wiring circuit on the semiconductor mounting surface (S1) side of the circuit board for semiconductor package (100A).
  • the bus line (108) is a wiring in the work panel for supplying a current necessary for electrolytic plating to the flip chip bump pad (105) at a predetermined position of the circuit board for semiconductor package (100A).
  • bus line (108) is used only when the embedded bump (107) is formed by electrolytic plating, and becomes unnecessary after the completion of the semiconductor package circuit board (100A).
  • the existence of such an extra bus line (108) greatly hinders the increase in wiring density.
  • it is conceivable to remove the bus line (108) by means of a laser or the like after the completion of the semiconductor package circuit board (100A) it is difficult to remove all of the bus line (108). There is also a problem of adversely affecting the operation. Further, even if the bus line is removed afterwards, the area after removal cannot be used for wiring formation, and therefore the reduction in wiring density is inevitable.
  • a bus line is not formed on the semiconductor chip mounting surface (S1), and an electroless copper plating film for feeding (on the solder ball mounting surface (S2) (see FIG. 10B). 109) and using this as a power supply layer, current is supplied to the solder ball pad (106) and the flip chip bump pad (105) electrically connected (via the wiring pattern (102)).
  • a circuit board (100B) for a semiconductor package in which embedded bumps (107) are formed by electrolytic plating has been studied (for example, Patent Document 2 (Japanese Patent Laid-Open No. 2011-61179)).
  • the wiring that is electrically connected to the solder ball pad (106) on the solder ball mounting surface (S2) (that is, the wiring that connects the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2)). Since current can only be supplied to the flip chip bump pads (105a) connected to the pattern (102), they are not electrically connected to the solder ball pads (106) (that is, the semiconductor chip mounting surfaces (S1) are connected to each other). There is a problem that current cannot be supplied to the flip chip bump pad (105b) connected to the wiring pattern (102) to be connected, and the embedded bump (107) cannot be formed.
  • the present invention has been made in view of such a problem, and without providing excessive wiring such as a bus line, an electrode portion that facilitates conduction with a semiconductor chip is easily and reliably formed in all the blind vias.
  • an object is to provide a circuit board for a semiconductor package.
  • the present inventors reduced the diameter of the blind via using a laser, formed an electroless plating film on the semiconductor chip mounting surface, and supplied an electric current for electrolytic plating, and By forming the surface connection pads by via filling electroplating, the surface connection pads can be easily and reliably formed in all the blind vias without providing extra wiring such as bus lines, and electrical connection with the semiconductor chip is achieved.
  • the present inventors have found that the above-mentioned problems can be solved by increasing the wiring density of the semiconductor package.
  • the gist of the present invention is a method of manufacturing a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface, (1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material; (2) A step of forming a blind via having a hole diameter of 100 ⁇ m or less by a laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1), (3) A step of forming an electroless plating film on the solder resist surface on the semiconductor chip mounting surface side having the blind via formed in (2), (4) A step of forming an electroplating layer by performing via filling by electrolytic plating on a solder resist blind via having an electroless plating film formed on the surface thereof in (3), and (5) For portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side, the electrolytic plating layer formed in the above (4) and the electroless plating film formed in the above (3) are removed by etching
  • Another gist of the present invention resides in a circuit board for a semiconductor package manufactured by the above method.
  • Another gist of the present invention is a circuit board for a semiconductor package having a semiconductor chip mounting surface and a solder ball mounting surface, (A) a wiring board in which through holes and wiring patterns are formed on an insulating substrate; (B) a solder resist formed on the surface of the wiring board and having a plurality of blind vias on each of the semiconductor chip mounting surface and the solder ball mounting surface; (C) a plurality of surface layer connection pads provided in the plurality of blind vias on the semiconductor chip mounting surface and connected to the wiring pattern; (D) provided with a plurality of blind vias on the solder ball mounting surface, and provided with a plurality of solder ball pads connected to the wiring pattern; and (I) At least a part of the surface layer connection pad is electrically connected to a wiring pattern that is not electrically connected to the solder ball pad, (Ii)
  • the present invention resides in a semiconductor package circuit board, which is used for manufacturing a semiconductor package substrate but is not used as a wiring pattern and does not have a bus
  • Another gist of the present invention is the semiconductor package circuit board described above, and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and soldered to a solder ball pad of the semiconductor package circuit board.
  • a ball is provided and electrical connection between the surface layer connection pad of the circuit board for semiconductor package and the semiconductor chip is ensured.
  • Another gist of the present invention includes an integrated circuit substrate and the semiconductor package disposed on the integrated circuit substrate, wherein conduction between the solder balls of the semiconductor package and the integrated circuit substrate is provided. Remains in a secured, integrated circuit.
  • ⁇ layer connection pads are easily and surely formed in all the blind vias without providing excessive wiring such as bus lines, and electrical connection with the semiconductor chip is achieved. Can be secured. Moreover, the diameter of the blind via can be reduced by the laser without impairing the conduction with the semiconductor chip, which can contribute to the high density wiring of the semiconductor package.
  • the circuit board for a semiconductor package of the present invention is an excellent circuit board for a semiconductor package capable of achieving both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package. It can be suitably used for manufacturing packages and integrated circuits.
  • FIGS. 1A to 1G are flowcharts showing a manufacturing procedure of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • 2 (a) to 2 (f) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment.
  • 2 (g) to 2 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to an embodiment of the present invention. Further, the description will be applied to the description of the manufacturing procedure of the semiconductor package circuit board in the first embodiment.
  • 3A to 3F are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment.
  • 3 (g) to 3 (j) are flowcharts showing a manufacturing procedure of a circuit board for a semiconductor package according to another embodiment of the present invention. Also, the description will be made for the description of the manufacturing procedure of the circuit board for semiconductor package in the second embodiment.
  • FIG. 4 is a schematic diagram showing an example of the configuration of the circuit board for a semiconductor package of the present invention.
  • FIG. 5A1 and 5A2 are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad 14 region of the semiconductor package circuit board 16 fabricated in Example 1, respectively.
  • ) And (b2) are an SEM surface photograph and an optical cross-sectional photograph of the surface layer connection pad (14) region of the semiconductor package circuit board (18) fabricated in Example 2, respectively.
  • FIG. 6 is a schematic diagram showing an example of the configuration of a conventional circuit board for a semiconductor package.
  • FIGS. 7A and 7B are schematic views showing an example of the configuration of a semiconductor package using the semiconductor package circuit board of FIG.
  • FIG. 8 is a schematic diagram showing an example of the configuration of a circuit board for a semiconductor package having a conventional embedded bump.
  • FIG. 9 is a schematic diagram showing an example of the configuration of a semiconductor package using the conventional circuit board for a semiconductor package having embedded bumps shown in FIG.
  • FIGS. 10A and 10B are diagrams for explaining a conventional method of forming embedded bumps.
  • One aspect of the present invention relates to a method of manufacturing a circuit board for a semiconductor package having a surface layer connection pad in a blind via.
  • the solder ball pad is electrically connected (that is, the wiring connecting the semiconductor chip mounting surface and the solder ball mounting surface). Since the current can be supplied only to the flip chip bump pad (connected to the pattern), the flip chip bump is not electrically connected to the solder ball pad (that is, connected to the wiring pattern connecting the semiconductor chip mounting surfaces). There was a problem that embedded pads could not be formed on the pads.
  • the current for electrolytic plating is directly applied to the wiring pattern exposed in the blind via from the electroless plating film formed on the semiconductor chip mounting surface. This is used to perform via filling by electrolytic plating.
  • the surface layer connection pad for ensuring the resistance can be easily and reliably formed, and can contribute to the high density wiring of the semiconductor package.
  • the method for manufacturing a circuit board for a semiconductor package of the present invention includes the following steps.
  • the process which shows "*" at the beginning is an arbitrary process.
  • (1) A step of forming a solder resist on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • (2) A step of forming a blind via having a hole diameter of 100 ⁇ m or less by laser with respect to the solder resist on the semiconductor chip mounting surface side formed in (1).
  • * (2 ′) A step of subjecting the solder resist having the blind via formed in (2) to a surface roughening treatment.
  • (3) A step of forming an electroless plating film on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2).
  • the semiconductor package circuit board has a semiconductor chip mounting surface (S1) on which a semiconductor chip is mounted and a solder ball mounting surface (S2) connected to the integrated circuit substrate, as shown in FIG. .
  • S1 semiconductor chip mounting surface
  • S2 solder ball mounting surface
  • the wiring board used in the manufacturing method of the present invention is one in which through holes and wiring patterns are formed on an insulating base material.
  • an insulating base material any insulating material used in conventional semiconductor packages or the like can be used. Examples include organic materials such as epoxy resin, cyanate resin, bismaleimide triazine resin, polyamide resin, polyimide resin, polyester resin, polyphenylene ether resin, E glass, D glass, S glass, T glass, NE glass, quartz, etc. An inorganic material etc. are mentioned. One of these materials may be used alone, or two or more thereof may be used in any combination. Examples of the form of the insulating substrate include woven fabric, nonwoven fabric, roving, chopped strand mat, and surfacing mat.
  • Examples of the shape of the insulating substrate include a plate shape and a film shape.
  • the thickness of the insulating base material is arbitrary and may be appropriately selected depending on the application, configuration, etc., but a range of usually 10 ⁇ m or more, particularly 20 ⁇ m or more is preferable.
  • a wiring substrate used in the manufacturing method of the present invention is manufactured.
  • any conventionally known method is used, and examples thereof include a mechanical drill method and a laser method.
  • Arbitrary known methods are also used to form wiring patterns. Examples include subtractive methods (panel plating and etching methods), pattern plating methods (methods based on ultrathin metal foils), and semi-additive methods. (Method of attaching an electroless metal on an insulating base material to form a base metal) is not limited thereto.
  • the conductive material from which the wiring pattern is based is not particularly limited, but usually a metal such as copper or aluminum, preferably copper is used. Further, usually, the necessary conduction between the front and back sides is ensured by forming a metal layer on the inner surface of the through hole.
  • metal foil or a metal film metal foil or metal films, such as copper and aluminum, for example, Preferably copper foil or a copper film is mentioned. In particular, electrolytic copper foil, rolled copper foil, copper alloy film and the like are suitable.
  • the metal foil or metal film may be subjected to a known surface treatment such as nickel treatment or cobalt treatment.
  • the thickness of the metal foil or metal film is arbitrary, and may be appropriately selected according to the use or configuration, but is usually 1 ⁇ m or more, preferably 10 ⁇ m or more.
  • a wiring pattern is formed.
  • the method include a subtractive method and a pattern plating method, and any method may be used in the present invention.
  • electroless plating for example, electroless copper plating using a palladium catalyst
  • electrolytic plating for example, electrolytic copper plating
  • Plating resist is laminated on top, and after patterning the plating resist by exposure and development using a pattern mask film, the plating metal in the absence of plating resist is removed by etching, and finally the plating resist is removed, thereby wiring.
  • the pattern plating method a plating resist is first laminated on a metal-clad laminate, and after patterning the plating resist by exposure and development using a pattern mask film, only the pattern portion is subjected to electrolytic plating, and further required. Accordingly, the wiring pattern is formed by performing plating that serves as a resist metal for etching, removing the plating resist, and etching unnecessary metal.
  • the thickness of the wiring pattern is arbitrary, and may be appropriately selected according to the use and configuration, but is usually in the range of 1 ⁇ m or more, particularly 5 ⁇ m or more.
  • steps such as cleaning, soft etching, half etching, desmearing, and surface roughening may be added.
  • steps such as cleaning, soft etching, half etching, desmearing, and surface roughening may be added.
  • metal layers such as a wiring pattern
  • FIG. 1 (a) An example of the manufacturing procedure of the wiring board is shown in the flowcharts of FIGS.
  • a metal-clad laminate (3) having a metal foil (2) on both sides of an insulating substrate (1) is prepared (FIG. 1 (a)).
  • Through holes (TH) are formed in the metal-clad laminate (3), and half-etching and desmearing are performed (FIG. 1 (b)).
  • Electroless plating is performed on the entire surface including the inside of the through hole (TH) of the metal-clad laminate (3) to form an electroless plating layer (4) (FIG. 1 (c)).
  • Electroless plating is performed using the electroless plating layer (4) as a power supply layer to form an electrolytic plating layer (5) (FIG. 1 (d)).
  • a plating resist (6) is laminated on both surfaces of this laminate, and patterning is performed by exposure and development using a pattern mask film (FIG. 1 (e)).
  • the electroless plating layer (4) and the electrolytic plating layer (5) in the region where the plating resist (6) is absent are removed by etching (FIG. 1 (f)).
  • the plating resist (6) is removed to obtain a wiring board (7) (FIG. 1 (g)).
  • this procedure is merely an example, and the manufacturing procedure of the wiring board is not limited to this.
  • a multilayer wiring board in which conduction between the front and back sides is ensured through blind vias and inner vias can be obtained.
  • such a multilayer wiring board is also preferably used.
  • Step (1) Formation of solder resist In this step, a solder resist is formed on the surface of a wiring board in which through holes and wiring patterns are formed on an insulating base material.
  • the solder resist material is not limited as long as it is a solder resist material usually used for printed circuit boards and circuit boards for semiconductor packages. Examples include a thermosetting or photocurable resist material made of an epoxy resin, a photocurable resist material made of an acrylic-epoxy resin, or the like. Specific examples include PSR-4000 (liquid form) and PFR-800 (film form) manufactured by Taiyo Ink Co., Ltd.
  • the solder resist is formed by laminating a solder resist material on the surface of the wiring board, and patterning and curing the solder resist material as necessary.
  • a liquid resist material it is applied to the wiring board surface and dried by drying.
  • a coating method generally used coating methods such as a screen printing method, a roll coater method, a spray coater method, a curtain coater method, a dip coater method and the like are used.
  • lamination is performed by laminating or vacuum pressing on the surface of the wiring board.
  • the solder resist material is cured by applying an appropriate stimulus according to the type of the solder resist material, for example, irradiation with light such as UV (ultraviolet) light or heating.
  • the solder resist is patterned by forming a masking pattern on the resist material layer, curing the resist material of the patterned portion by light irradiation, and then non-curing resist material of the masking portion. This can be done by removing.
  • the method for removing the non-cured solder resist material can be appropriately selected depending on the type of the solder resist material, and examples thereof include a method using sodium carbonate (sodium carbonate). Further, post-curing by heating or UV light may be performed.
  • the thickness of the solder resist is not limited as long as the wiring pattern can be covered without exposing it to the surface, but it is usually 5 ⁇ m or more, especially 10 ⁇ m or more because it is necessary to completely cover the wiring pattern. preferable. On the other hand, from the viewpoint of reducing the energy consumption during laser processing as much as possible, it is usually 50 ⁇ m or less, preferably 30 ⁇ m or less.
  • blind vias are formed by laser on the solder resist on the semiconductor chip mounting surface side formed in (1).
  • the laser used for forming the blind via is not particularly limited as long as it is a laser generally used for forming a via on a printed wiring board or a circuit board for a semiconductor package.
  • a carbon dioxide laser, a UV laser, or the like is used.
  • Trepanning is a method of drilling while rotating the laser beam on the circumference (concentric or spiral) during drilling, and is a method commonly used when machining holes larger than the beam diameter. is there.
  • a shape in which the wall of the opening is almost vertical and the diameter of the opening (solder resist surface) is the same as the diameter of the bottom (wiring pattern surface) for example, in FIG.
  • Taper shape for example, a shape as shown in FIG.
  • the diameter of the blind via is usually 100 ⁇ m or less, preferably 80 ⁇ m or less, more preferably 50 ⁇ m or less, from the viewpoint of high integration of a semiconductor package or the like. According to the manufacturing method of the present invention, even such fine blind vias are preferable because the surface layer connection pads can be easily and reliably formed and the conduction with the semiconductor chip can be ensured. However, from the viewpoint of ensuring the conduction with the semiconductor chip, the lower limit of the diameter of the blind via is usually 5 ⁇ m or more, preferably 10 ⁇ m or more.
  • a larger blind via having a diameter exceeding 100 ⁇ m may be formed.
  • a part of the blind via formed in the solder resist is a fine blind via having a diameter of 100 ⁇ m or less, a remarkable effect can be obtained by applying the present invention.
  • the blind via is usually formed so as to penetrate the solder resist and expose the wiring pattern (metal layer) below it. For this reason, the depth of the blind via is usually the same as the thickness of the solder resist on the wiring pattern.
  • Process (2 ′) surface roughening treatment In this step, a surface roughening process is performed on the solder resist having the blind via formed in (2).
  • this process is arbitrary, it is preferable to implement this process from a viewpoint which performs formation of the electroless-plating film in postscript (3) suitably.
  • Surface roughening methods include physical treatment by spraying fine particles, such as chemical treatment, etching using a solution containing potassium permanganate or potassium chromate, plasma treatment, jet scrub treatment, sandblast treatment, etc. The physical process which performs roughening is mentioned. Among these, the jet scrub method is preferable because roughening can be performed easily and uniformly.
  • Step (3) Formation of electroless plating film In this step, an electroless plating film is formed on the surface of the solder resist on the semiconductor chip mounting surface side having the blind via formed in (2). Since the wiring pattern (metal layer) is exposed inside the blind via, an electroless plating film is formed on the exposed wiring pattern (metal layer). As a result, a power supply layer for electrolytic plating described later (4) can be secured on the solder resist surface on the semiconductor chip mounting surface side and the surface of the wiring pattern (metal layer) exposed inside the blind via.
  • the metal used as the material for electroless plating is not particularly limited, copper, nickel, tin, and the like are preferable, and copper is particularly preferable.
  • the method of electroless plating is not particularly limited, and a conventionally known method may be appropriately used. Usually, after making a metal catalyst adhere to the plating object surface, the method of processing with a plating solution is mentioned.
  • the metal catalyst examples include metals such as Pd, Ag, Pt, Au, Ni, and Co. In the case of electroless copper plating, palladium (Pd) is particularly preferable. These may be used individually by 1 type and may use 2 or more types together by arbitrary ratios and combinations.
  • the method for attaching the metal catalyst to the surface of the plating target include a method of immersing the plating target in an activator solution containing the metal catalyst and a method of depositing the metal catalyst on the plating target.
  • the amount of the metal catalyst is not particularly limited, but is preferably in the range of usually 0.1 to 2 mg / mm 2 per unit surface.
  • the composition of the plating solution is not particularly limited.
  • an electroless copper plating solution usually, copper ions and / or a salt thereof (such as copper sulfate) and a reducing agent (such as formaldehyde) And a complexing agent (for example, Rochelle salt (sodium potassium tartrate) or EDTA (ethylenediaminetetraacetic acid)) is used.
  • a complexing agent for example, Rochelle salt (sodium potassium tartrate) or EDTA (ethylenediaminetetraacetic acid)
  • the treatment is usually performed by immersing the plating object in the plating solution.
  • the thickness of the electroless copper plating film is arbitrary and may be selected as appropriate. However, from the viewpoint of ensuring conduction, it is usually 0.2 ⁇ m or more, preferably 1.0 ⁇ m or more.
  • the upper limit is not particularly limited, but is usually about 2 ⁇ m or less.
  • Step (3'-1) Formation of plating resist In this step, the plating resist is formed on both surfaces of the circuit board having the solder resist on which the electroless plating film is formed on the surface in (3). Although this step (3′-1) and steps (3′-2) and (4 ′) described later are optional, the removal amount of electrolytic plating and electroless plating can be reduced to increase the surface layer connection pad height. From the viewpoint of bringing the thickness closer to the solder resist surface, it is preferable to carry out this step.
  • the material for the plating resist is not particularly limited as long as it is a plating resist material that is usually used for printed circuit boards and circuit boards for semiconductor packages. It is preferable to use a stable material that does not dissolve or peel off. In addition, when removing the plating resist in the following (4 ′), it can be removed by a method different from the method of removing the solder resist material so that even the solder resist of the lower layer is not removed together. It is preferable to use materials. Examples of such a plating resist material include solid materials such as an alkali developing type photosensitive film (dry film).
  • the dry film examples include the Sunfort (registered trademark) series (made by Asahi Kasei E-materials), the RY series (made by Hitachi Chemical Co., Ltd.), the Liston series (made by DuPont MRC dry film). It is done.
  • the plating resist is formed by laminating plating resist materials on both sides of the circuit board.
  • the plating resist material is in the form of a film (dry film)
  • the dry resist film is laminated or vacuum-pressed on the surface of the circuit board.
  • the thickness of the plating resist is arbitrary and may be selected as appropriate. From the viewpoint of preventing plating overhang, it is usually 15 ⁇ m or more, preferably 20 ⁇ m or more, and from the viewpoint of the resolution of the dry film. Is usually in the range of 40 ⁇ m or less, particularly 30 ⁇ m or less.
  • Plating resist opening formation In this step, an opening is formed with respect to the plating resist formed in (3′-1) so that at least the blind via of the solder resist on the semiconductor chip mounting surface side is exposed.
  • a light (UV) curable material is used as the plating resist material
  • a masking pattern is formed on the resist material layer, and the resist material in the patterned portion is cured by light irradiation. Thereafter, the uncured resist material in the masking portion can be removed.
  • the method for removing the non-cured plating resist can be appropriately selected depending on the type of the plating resist, and examples thereof include a method such as treatment with an alkaline aqueous solution such as sodium carbonate.
  • the shape of the opening formed in the plating resist on the semiconductor chip mounting surface side is arbitrary, and may be any shape as long as at least the blind via of the solder resist is exposed. That is, only the blind via portion may be substantially opened, the entire semiconductor chip mounting surface may be opened (that is, all the plating resist on the semiconductor chip mounting surface may be removed), or other shapes of openings may be formed. Good.
  • substantially opening only the portion of the blind via, in the postscript (4) formation of the electrolytic plating layer in the portion other than the blind via is suppressed, and the amount of etching required in the postscript (5) is reduced.
  • the circuit board for a semiconductor package having such a thick surface layer connection pad has an advantage that it is easy to ensure electrical continuity with the semiconductor chip (this mode will be described later with reference to FIGS. 2A to 2J). To do.) On the other hand, if all of the plating resist on the semiconductor chip mounting surface is removed, there is an advantage that the labor of patterning the plating resist on the semiconductor chip mounting surface can be saved, and a circuit board for a semiconductor package can be more easily manufactured (such a case). Such a mode will be described later with reference to FIGS. 3 (a) to 3 (j).
  • via filling is performed by electrolytic plating on the solder resist blind via having the electroless plating film formed on the surface in (3) to form an electrolytic plating layer.
  • the electrolytic plating layer is applied to the semiconductor chip mounting surface while supplying power using the electroless plating film as a power feeding layer.
  • the metal used as the material for electrolytic plating is not particularly limited, copper, nickel, tin and the like are preferable, and copper is particularly preferable.
  • the electrolytic plating layer is formed so that the electrolytic plating layer in the blind via portion and the electrolytic plating layer in the other portion have almost the same height.
  • the inside of the blind via can be filled with electrolytic plating (this is referred to as “via filling”).
  • via filling the method of filled plating is not particularly limited, for example, the method described in JP-A-11-145621 can be used.
  • the surface to be plated (semiconductor chip mounting surface) is immersed in a copper sulfate plating bath and in contact with the copper sulfate plating bath, and the surface to be plated is used as a cathode. This is performed by applying an electric current from an external power source to the anode immersed in the copper sulfate plating bath.
  • a copper sulfate plating bath called a high-throw bath with a low copper concentration and a high sulfuric acid concentration in order to improve the throwing power.
  • a copper sulfate plating bath in which the copper concentration is further lowered and the sulfuric acid concentration is increased as compared with the conventional high-throw bath is used, and the current density of the cathode (cathode) is made lower than before.
  • Electrolytic plating is performed. Thereby, plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • the mass ratio of copper sulfate / sulfuric acid in the copper sulfate plating bath is usually 30 or less, preferably 8.33 or less.
  • plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • the mass ratio of copper sulfate / sulfuric acid is usually 0.66 or more, preferably 1.5 or more.
  • the copper sulfate plating bath is prepared by dissolving copper sulfate and sulfuric acid using water or the like as a solvent so that the mass ratio of copper sulfate / sulfuric acid is the above ratio.
  • the amount of copper sulfate used relative to the solvent is usually 100 g / L or more, preferably 150 g / L or more, and usually 300 g / L or less, preferably 250 g / L or less.
  • the amount of sulfuric acid used in the solvent is usually 10 g / L or more, preferably 30 g / L or more, and usually 150 g / L or less, preferably 100 g / L or less.
  • the chlorine ion content is usually 20 mg / L or more, preferably 30 mg / L or more, and usually 70 mg / L or less, especially 50 mg / L or less.
  • the copper sulfate plating bath may contain other components.
  • other components include brighteners, carriers, and leveling agents.
  • brighteners include sulfur-containing organic compounds such as thiourea and thiocarbamate.
  • the carrier include polyoxyalkylene glycol.
  • leveling agents include polyamines. The amount of these components used is the same as before.
  • the current density of the cathode (cathode) during electrolytic plating is usually 5 A / dm 2 or less, preferably 3 A / dm 2 or less.
  • plating is preferentially formed inside the blind via, and via filling by filled plating is achieved.
  • it is usually preferably 0.5 A / dm 2 or more, and more preferably 1 A / dm 2 or more.
  • the temperature at the time of electroplating is not particularly limited, it is preferably 15 ° C. or higher, particularly 20 ° C. or higher, and usually 30 ° C. or lower, especially 25 ° C. or lower.
  • the time of electrolytic plating is not limited, but at least the inside of the blind via is filled with filled plating, and the difference in height of the electrolytic plating layer between the blind via portion and the other portions is almost eliminated and it is carried out until it is substantially flat. Good.
  • the thickness of the electroplating layer is not particularly limited, but the thickness of the electroplating layer other than the blind via is usually 3 ⁇ m or more, preferably 5 ⁇ m or more, and usually 40 ⁇ m or less, especially 30 ⁇ m or less. is there.
  • the thickness of the electrolytic plating layer in the blind via portion is substantially equal to the sum of the thickness of the electrolytic plating layer in the portion other than the blind via and the depth of the blind via (that is, the thickness of the solder resist on the wiring pattern). Therefore, the thickness is much larger than the thickness of the electrolytic plating layer in the portion other than the blind via.
  • Step (4 ′) Plating resist removal In this step, the plating resist formed in (3′-1) is removed.
  • the plating resist can be removed by appropriately selecting a technique that can remove the plating resist material and that does not adversely affect electrolytic plating or solder resist such as erosion or modification. Examples include treatment with an alkaline aqueous solution such as an aqueous sodium hydroxide solution or an amine-based aqueous solution.
  • Etching removal of surplus plating, formation of surface layer connection pad In this step, the excess electrolytic plating layer (formed in (4) above) and the electroless plating film (formed in (3) above) deposited on portions other than the blind vias on the solder resist surface on the semiconductor chip mounting surface side are etched. To remove the solder resist. This eliminates conduction between blind vias and achieves electrical independence between blind vias.
  • the electrolytic plating layer filled in the blind via according to the above (4) is much thicker than the electrolytic plating layer in the portion other than the blind via. It is not removed by an etching amount enough to remove the layer and the electroless plating film, but remains in the blind via.
  • a surface layer connection pad is formed by the electrolytic plating layer and the electroless plating film remaining in the blind via.
  • the etching method is not particularly limited, and any conventionally known method can be used.
  • etching is performed using a copper etchant.
  • the copper etchant those capable of selectively etching the copper plating layer are suitable, and among them, a hydrogen peroxide / sulfuric acid based etchant is preferred. Examples include SE-07 (Mitsubishi Gas Chemical Co., Ltd.), CPE-700 (Mitsubishi Gas Chemical Co., Ltd.), CPE-810 (Mitsubishi Gas Chemical Co., Ltd.), CPE-770D (Mitsubishi Gas Chemical Co., Ltd.). ), CPE-800 (Mitsubishi Gas Chemical Co., Ltd.), CPE-820 (Mitsubishi Gas Chemical Co., Ltd.) and the like.
  • the etching conditions are not limited, but the electrolytic plating layer and the electroless plating film in the portion other than the blind via are removed, and the electrolytic plating layer and the electroless plating film in the blind via portion remain, What is necessary is just to select suitably so that the surface layer connection pad of desired thickness may be formed.
  • preferable etching conditions are as follows: It is as follows. That is, the copper etching solution exemplified above is adjusted to a hydrogen peroxide concentration of 5.0 to 30 g / L, a sulfuric acid concentration of 10 to 100 g / L, and a copper concentration of about 10 to 50 g / L. It is preferable to apply the above-mentioned means, treat the solder resist surface at a temperature of about 20 to 40 ° C. until it is exposed, and then wash with an aqueous solution of sodium hydroxide, sulfuric acid or the like.
  • the metal catalyst is removed.
  • an appropriate metal removal solution may be selected and used. Examples include removal solutions such as nitric acid / chlorine ion / cationic polymer type, nitrate / inorganic acid salt or its salt type, mercapto compound type, nitrogen-containing aliphatic organic compound / iodine-containing inorganic compound type, hydrochloric acid type removing solution, etc. use.
  • Mekku Remover PJ-9710 made by Mec Co., Ltd.
  • Mekku Remover PJ-9720 made by Mec Co., Ltd.
  • Melstrip PD-3110 made by Meltex Co., Ltd.
  • Dynemat PD-280 Dynemat PD-280 (Daiwa Kasei) Co., Ltd.
  • Parastrip IC made by Atotech Co., Ltd.
  • a surface treatment is performed on the exposed portion of the electrolytic plating in the blind via after the etching of (5).
  • this step is optional, it is preferable to carry out this step from the viewpoint of poor connection due to corrosion of the surface connection pad surface.
  • the type of surface treatment is not particularly limited because it is appropriately selected depending on the use of the semiconductor package substrate and the mounting method of the semiconductor chip, but is not limited to electroless tin plating, electroless gold plating, electroless nickel gold plating, electroless Nickel palladium gold plating treatment, organic rust prevention treatment and the like are used.
  • the electroless tin plating treatment is preferably performed by immersion treatment using, for example, a substitution tin plating bath or a substitution reduction tin plating bath.
  • the electroless gold plating treatment is preferably performed by immersion treatment using, for example, a displacement gold plating bath.
  • the electroless nickel gold plating treatment is preferably performed by dipping treatment in the order of electroless nickel plating and electroless gold plating using, for example, a reduced nickel plating bath, a displacement gold plating bath or a reduced gold plating bath.
  • the electroless nickel palladium gold plating treatment uses, for example, a reduced nickel plating bath, a reduced palladium plating bath, a displacement gold plating bath or a reduced gold plating bath, in the order of electroless nickel plating, electroless palladium plating, and electroless gold plating. It is preferable to carry out by immersion treatment.
  • the method for manufacturing a circuit board for a semiconductor package of the present invention may have an optional step in addition to the above-described steps. For example, after forming the solder resist in the step (1), the solder resist on the solder ball mounting surface is opened by patterning separately from the blind via formation on the semiconductor chip mounting surface side solder resist in the step (2). It is preferable to carry out a surface treatment such as formation of an electroplating layer, formation of an electrolytic plating layer, or a treatment such as attachment of a solder ball.
  • FIGS. 2A An example of a method for manufacturing a semiconductor package circuit board of the present invention is shown in the flowcharts of FIGS.
  • a wiring board (7) in which through holes and wiring patterns are formed on an insulating base material is prepared (FIG. 2A).
  • a solder resist (8) is formed on the surface of the wiring board (7) (step (1)), the solder resist on the solder ball mounting surface (S2) is patterned, the wiring pattern is exposed, and a solder ball pad (9) Is formed (FIG. 2B).
  • An electrolytic plating layer (10) is formed on the solder ball pad (9) as a surface treatment layer (FIG. 2 (c)).
  • a blind via (BV) is formed on the semiconductor chip mounting surface (S1) side solder resist with a laser (step (2): FIG. 2 (d)).
  • the wiring pattern (2) in the blind via (BV) is exposed.
  • step (2 ′) after subjecting the solder resist on the semiconductor chip mounting surface (S1) side to surface roughening (step (2 ′)), the surface of the solder resist (and the surface of the wiring pattern (2) exposed in the blind via (BV)) ) To form an electroless plating film (11) (step (3): FIG. 2 (e)).
  • a plating resist (12) is formed on both surfaces of the wiring board (step (3'-1)), and openings (O) are formed so that the solder resist blind vias on the semiconductor chip mounting surface (S1) side are exposed.
  • step (3′-2) FIG. 2 (f)
  • blind via (BV) via filling is performed by electrolytic plating to form an electrolytic plating layer (13) (step (4): FIG. 2 (g)).
  • the plating resist (12) is removed (step (4 ′): FIG. 2 (h)).
  • a surface layer connection pad (14) comprising an electrolytic plating layer (13) and an electroless plating film (11) is formed in the via (BV) (step (5): FIG. 2 (i)). Thereafter, the surface layer connection pad (14) is subjected to a surface treatment to form an electroless plating layer (15), thereby producing a circuit board (16) for a semiconductor package (step (5 ′): FIG. 2 (j). )).
  • FIGS. 3A to 3J Another specific example of the method for manufacturing a circuit board for a semiconductor package of the present invention is shown in the flowcharts of FIGS.
  • the procedures of FIGS. 3A to 3J are the same as the procedures of FIGS. 2A to 2J except for the points described below. That is, a plating resist is formed only on the solder ball mounting surface (S2) side of the wiring board (step (3′-2): FIG. 3 (f)). This increases the amount of the electrolytic plating layer (13) and the electroless plating film (11) to be removed by etching in the step (5) (FIGS. 3 (h) and (i)), so that the resulting surface layer Although the thickness of the connection pad (14) is smaller than that of the above example (FIG. 3 (j)), the semiconductor package circuit board (18) can be obtained by a simpler operation.
  • the above manufacturing method is merely an example, and the manufacturing method of the circuit board for a semiconductor package of the present invention is not limited to this.
  • circuit board for semiconductor packages Another aspect of the present invention relates to a circuit board for a semiconductor package manufactured by the method for manufacturing a circuit board for a semiconductor package of the present invention.
  • the semiconductor package circuit board (16, 18) of the present invention has a semiconductor chip mounting surface (S1) and a solder ball mounting surface (S2), (A) a wiring substrate (7) in which a through hole (TH) and a wiring pattern (2) are formed on an insulating substrate (1); (B) a solder resist (8) formed on the surface of the wiring board (7) and having a plurality of blind vias (BV) on each of the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2); (C) a plurality of surface layer connection pads (14) provided in the plurality of blind vias (BV) on the semiconductor chip mounting surface (S1) and electrically connected to the wiring pattern; (D) A plurality of solder ball pads (9) provided on the plurality of blind vias (BV) on the solder ball mounting surface (S2) and connected to the wiring pattern.
  • S1 semiconductor chip mounting surface
  • S2 solder ball mounting surface
  • A a wiring substrate (7) in which a through hole (TH) and a wiring pattern (2) are formed on
  • a surface treatment layer reference numerals 10, 15, and 17 in FIGS. 2 and 3
  • the details of each component are as described above in the method for manufacturing a circuit board for a semiconductor package of the present invention.
  • the circuit board (16, 18) for a semiconductor package of the present invention has a blind via (BV) formed on a wiring pattern (2a) connecting the semiconductor chip mounting surface (S1) and the solder ball mounting surface (S2). ) As well as the blind vias (BV) formed on the wiring pattern (2b) connecting the semiconductor chip mounting surfaces (S1) to each other, have the surface layer connection pads (14).
  • the semiconductor package circuit board (16, 18) of the present invention at least a part of the surface layer connection pads is electrically connected to the wiring pattern that is not electrically connected to the solder ball pads. Thereby, conduction
  • Such a configuration is a conventional technique in which a current is supplied from the electroless plating film on the solder ball mounting surface into the blind via and a buried bump is formed by electrolytic plating (FIG. 10B: Patent Document 2 (JP 2011-61179 A). ) Etc.) is a configuration that could not be achieved.
  • the semiconductor package circuit boards (16, 18) of the present invention are used in the manufacture of general semiconductor package circuit boards (for example, for surface treatment of flip chip bump pads, formation of embedded bumps, surface treatment, etc.). Although used, it is not used as a wiring pattern and does not have unnecessary bus lines.
  • the bus line for forming the embedded bump FIG. 10A: Patent Document 1 (Japanese Patent Laid-Open No. 52-12575), etc.)
  • the presence of such an unnecessary bus line is caused by the high wiring height.
  • the configuration of the present invention that eliminates the need for such bus lines is very advantageous in terms of increasing the wiring density and stabilizing the operation.
  • the wiring of the circuit board for semiconductor package can be made higher in density than in the past.
  • the bump pitch (distance between the bump centers) of the circuit board for semiconductor package can be set to 200 ⁇ m or less, particularly 130 ⁇ m or less, for example.
  • the circuit board for semiconductor package of the present invention is clearly differentiated in configuration from the circuit board for semiconductor package having embedded bumps manufactured by the prior art, and has a very remarkable effect. Is clear.
  • a semiconductor package of the present invention includes the above-described semiconductor package circuit board of the present invention and a semiconductor chip provided on a semiconductor chip mounting surface of the semiconductor package circuit board, and a surface layer connection pad of the semiconductor package circuit board; It has a configuration in which conduction with a semiconductor chip is ensured.
  • semiconductor chips such as a CPU and a semiconductor memory (SRAM, DRAM, etc.). These semiconductor chips are appropriately selected according to the specifications and applications of the target semiconductor package, and are arranged on the semiconductor chip mounting surface of the semiconductor package circuit board to form electrical continuity with the semiconductor package circuit board.
  • Examples of the method for forming electrical connection between the circuit board for semiconductor package and the semiconductor chip include wire bonding and flip chip bonding. From the viewpoint of integration of the semiconductor chip and miniaturization of the semiconductor package, the semiconductor package according to the present invention.
  • flip chip bonding is preferable.
  • flip chip bonding is a method of electrically connecting a bump formed in advance on an electrode portion of a semiconductor chip to an electrode portion (flip chip bump pad) of a circuit board for a semiconductor package.
  • pillars and solder balls made of metal such as gold or copper are used as the bumps of the electrode portions of the semiconductor chip, and these are appropriately selected according to the specifications and applications of the target semiconductor package.
  • the semiconductor package of the present invention is configured by bringing the electrode portions (bumps) of the semiconductor chip into contact with the surface layer connection pads of the semiconductor package circuit board of the present invention and electrically connecting them. Thereby, electrical continuity with the electrode part (bump) of the semiconductor chip can be ensured easily and reliably when the semiconductor chip is mounted.
  • the semiconductor chip is fixed to the circuit board for semiconductor package by means such as adhesion in a state where conduction is ensured.
  • various processes such as mounting of other electronic components and storage in a housing may be added as necessary.
  • An integrated circuit of the present invention includes an integrated circuit substrate and the above-described semiconductor package of the present invention disposed on the integrated circuit substrate, and electrical connection between a solder ball of the semiconductor package and the integrated circuit substrate is provided. It has a secured configuration.
  • the integrated circuit substrate is a substrate on which an integrated circuit is configured by mounting a semiconductor package or the like.
  • a through hole and a circuit pattern are formed on an insulating base material, and an electrode portion for ensuring electrical connection between the circuit pattern and the semiconductor package is formed.
  • connection by solder balls is mainly used to form continuity in manufacturing.
  • the connection by the solder ball is a method of connecting the solder ball of the semiconductor package and the electrode part of the substrate for the integrated circuit with the solder ball. Specific conditions and the like are appropriately selected according to the specifications and application of the target integrated circuit.
  • the semiconductor package is fixed to the integrated circuit substrate by means of adhesion or the like in a state where conduction is ensured.
  • FIGS. 1 (a) to 1 (g) a wiring board having through holes and wiring patterns formed on an insulating base material was produced (note that FIG. 1 is used to explain an embodiment of the present invention). This figure is also used to explain the manufacturing procedure of the wiring board in the reference example.) Specifically, it is as follows.
  • a copper-clad laminate (3) having a copper foil (2) (thickness 12 ⁇ m) on both sides of an insulating substrate (1) (thickness 0.1 mm) (CCL-HL832HS manufactured by Mitsubishi Gas Chemical Co., Ltd.) was prepared (FIG. 1 (a)).
  • a through hole (TH) hole diameter ⁇ 100 ⁇ m
  • TH hole diameter ⁇ 100 ⁇ m
  • SE-07 half etching solution SE-07 (Mitsubishi Gas Chemical Co., Ltd.).
  • the foil (2) was etched to a thickness of 5 ⁇ m, and desmeared with an alkali swelling treatment liquid / permanganate treatment liquid (FIG. 1B).
  • a palladium catalyst was attached to the entire surface including the inside of the through hole (TH) of the copper-clad laminate (3) using an activator Neogant U (manufactured by Atotech Co., Ltd.) (0.1 mg / dm2), and printing was performed. Electroless copper plating was performed using Gantt P-DK (Atotech Co., Ltd.) to form an electroless copper plating layer (4) (thickness 1 ⁇ m) containing a palladium catalyst (FIG. 1 (c)).
  • electrolytic panel plating with copper was performed to form an electrolytic copper plating layer (5) (thickness: 15 ⁇ m) (FIG. 1 (d)).
  • a plating resist (dry film) (6) was laminated on both sides, exposed and developed using a pattern mask film, and patterning of the plating resist (dry film) (6) was performed (FIG. 1 (e)). .
  • etching was performed with a copper chloride solution to remove the electroless copper plating layer (4) and the electrolytic copper plating layer (5) in the region where the plating resist (dry film) (6) does not exist (FIG. 1 (f )).
  • the plating resist (dry film) (6) was removed with caustic soda solution to obtain a wiring board (7) in which through holes (TH) and a wiring pattern (2) were formed on the insulating base material (FIG. 1 (g)).
  • Example 1 -Fabrication of circuit boards for semiconductor packages: Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (16) was produced as described below in accordance with the procedure shown in FIGS.
  • FIG. 2 is a diagram used to explain the embodiment of the present invention, but it is also used to explain the manufacturing procedure of the circuit board for semiconductor package in Example 1.
  • a wiring board (7) obtained by the procedure of the reference example was prepared (FIG. 2 (a)), and the surface of the electrolytic copper plating layer (5) was etched with etch bond CZ-8100 (MEC Co., Ltd.).
  • photosensitive solder resist ink PSR-4000AUS308 manufactured by Taiyo Ink Manufacturing Co., Ltd.
  • the solder resist layer (8) having a solder ball pad (9) on the solder ball mounting surface is exposed by UV exposure through a pattern mask and developed with a sodium carbonate aqueous solution to expose the wiring pattern (2).
  • An electrolytic nickel plating layer and an electrolytic gold plating layer (10) were formed on the surface of the solder ball pad (9) of the obtained solder resist layer (8) using a bus line (FIG. 2 (c)). Thereafter, blind vias (BV) (opening diameter ⁇ 50 ⁇ m, bottom diameter ⁇ 30 ⁇ m) were formed in the solder resist layer (8) on the semiconductor chip mounting surface by trepanning using a UV-YAG laser (step (2): FIG. 2 (d)).
  • BV blind vias
  • the surface of the solder resist layer (8) is roughened by applying a jet scrub process (Permis # 240, 60 seconds) (step (2 ′)), and then the entire surface is activated by an activator Neogant U (manufactured by Atotech Co., Ltd.).
  • a palladium catalyst was adhered (0.1 mg / dm 2 ), electroless copper plating was applied to the entire surface by Print Gantt P-DK (Atotech Co., Ltd.), and an electroless copper plating film (11) containing the palladium catalyst (thickness) 1 ⁇ m) was formed (step (3): FIG. 2 (e)).
  • a plating resist (dry film) (12) is laminated on both surfaces (step (3'-1)), exposed and developed using a pattern mask film, and plating on the blind via (BV) portion of the semiconductor chip mounting surface
  • the resist (dry film) (12) was removed.
  • the entire surface of the solder ball was left with a plating resist (dry film) (12) (step (3'-2): FIG. 2 (f)).
  • the surface layer connection pad (14) was formed by performing a palladium removal process by MEC Co., Ltd. (step (5): FIG. 2 (i)).
  • Electroless nickel plating 5 ⁇ m) by Nicolon GIB (Okuno Pharmaceutical Co., Ltd.
  • electroless palladium plating (0.06 ⁇ m) by Neoparabright (High Purity Chemical Co., Ltd.)
  • Gobright TWX-40 Uemura Industry Co., Ltd.
  • Electroless gold plating 0.1 ⁇ m was applied to form an electroless nickel / palladium / gold plating layer (15) (step (5 ′): FIG. 2 (j)).
  • the semiconductor package circuit board (16) was produced by the above procedure.
  • the conduction between the surface connection pads (14) connected by the wiring pattern (2) and the conduction between the surface layer connection pads (14) was verified by a conduction tester (Yokogawa Electric Corporation 7555). There was no connection failure.
  • Example 2 -Fabrication of circuit boards for semiconductor packages: Using the wiring board (7) obtained by the procedure of the reference example, a semiconductor package circuit board (18) was produced according to the procedure shown in FIGS. 3 (a) to 3 (j). Although it is a figure used to explain the embodiment, it is also used for explanation of the manufacturing procedure of the circuit board for semiconductor package in Example 2. The procedure is the same as the procedure of the first embodiment shown in FIGS. 2A to 2J except for the points described below.
  • the opening diameter of the blind via (BV) was set to 45 ⁇ m and the bottom diameter was set to 25 ⁇ m.
  • the plating resist (12) is not formed on the semiconductor chip mounting surface (S1), and only the solder ball mounting surface (S2). A plating resist (12) was formed on the substrate.
  • electroless tin plating (thickness 1.5 ⁇ m) is applied by Stanatech 2000V (manufactured by Atotech Japan Co., Ltd.) An electrolytic tin plating layer (17) was formed.
  • the connection between the surface connection pads (14) connected by the wiring pattern (2) and the connection between the surface layer connection pads (14) was verified by the same method as in Example 1, and no connection failure occurred.
  • the present invention it is possible to easily and inexpensively manufacture a semiconductor package circuit board in which surface connection pads are formed in all the blind vias without providing extra wiring such as a bus line.
  • the obtained circuit board for a semiconductor package can achieve both easy and reliable conduction when mounting a semiconductor chip and high wiring density of the semiconductor package.
  • the present invention has great applicability in the field of semiconductor packages and integrated circuits.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

Selon l'invention, (1) un résist de soudure est formé sur une surface d'un substrat de câblage obtenu par formation de trous traversants et de motifs de câblage sur un substrat isolant ; (2) des trous d'interconnexion borgnes sont formés par laser dans le résist de soudure sur un côté de montage de puce à semi-conducteur, chaque trou d'interconnexion ayant un diamètre de 100 µm ou inférieur ; (3) un revêtement par dépôt autocatalytique est formé sur une surface du résist de soudure sur le côté de montage de puce à semi-conducteur ayant les trous d'interconnexion borgnes ; (4) les trous d'interconnexion borgnes du résist de soudure ayant le revêtement par dépôt autocatalytique formé sur la surface de celui-ci sont soumis à un remplissage de trous d'interconnexion par revêtement électrolytique, ce par quoi des couches par dépôt électrolytique sont formées par rapport aux trous d'interconnexion borgnes ; et (5) les couches par dépôt électrolytique et le revêtement par dépôt autocatalytique sont retirés par gravure des zones autres que les trous d'interconnexion borgnes sur la surface du résist de soudure sur le côté de montage de puce à semi-conducteur, de telle sorte que le résist de soudure est exposé, ce par quoi une pastille de connexion en surface formée avec la couche par dépôt électrolytique et le revêtement par dépôt autocatalytique est formée dans chaque trou d'interconnexion borgne.
PCT/JP2013/070783 2012-08-07 2013-07-31 Carte de circuit pour boîtier de semi-conducteur et procédé de fabrication de celle-ci WO2014024754A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014529450A JPWO2014024754A1 (ja) 2012-08-07 2013-07-31 半導体パッケージ用回路基板及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012175058 2012-08-07
JP2012-175058 2012-08-07

Publications (1)

Publication Number Publication Date
WO2014024754A1 true WO2014024754A1 (fr) 2014-02-13

Family

ID=50067985

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/070783 WO2014024754A1 (fr) 2012-08-07 2013-07-31 Carte de circuit pour boîtier de semi-conducteur et procédé de fabrication de celle-ci

Country Status (3)

Country Link
JP (1) JPWO2014024754A1 (fr)
TW (1) TW201411740A (fr)
WO (1) WO2014024754A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017077837A1 (fr) * 2015-11-05 2017-05-11 株式会社村田製作所 Substrat à composant monté
JP2023110828A (ja) * 2022-01-28 2023-08-09 巨擘科技股▲ふん▼有限公司 積層基板の表面処理層構造
TWI844319B (zh) 2023-03-24 2024-06-01 景碩科技股份有限公司 印刷電路板封裝結構及其製作方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9443780B2 (en) * 2014-09-05 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having recessed edges and method of manufacture

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000244125A (ja) * 1999-02-22 2000-09-08 Ibiden Co Ltd 多層ビルドアップ配線板及びその製造方法
JP2001110940A (ja) * 1999-10-12 2001-04-20 Nippon Circuit Kogyo Kk 半導体パッケージ用基板とその製造法
JP2003046243A (ja) * 2001-07-27 2003-02-14 Toppan Printing Co Ltd 高密度多層ビルドアップ配線板の製造方法
JP2004327744A (ja) * 2003-04-24 2004-11-18 Kyocera Corp 多層配線基板及びその製造方法
WO2005076682A1 (fr) * 2004-02-04 2005-08-18 Ibiden Co., Ltd. Carte imprimee multicouche

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000244125A (ja) * 1999-02-22 2000-09-08 Ibiden Co Ltd 多層ビルドアップ配線板及びその製造方法
JP2001110940A (ja) * 1999-10-12 2001-04-20 Nippon Circuit Kogyo Kk 半導体パッケージ用基板とその製造法
JP2003046243A (ja) * 2001-07-27 2003-02-14 Toppan Printing Co Ltd 高密度多層ビルドアップ配線板の製造方法
JP2004327744A (ja) * 2003-04-24 2004-11-18 Kyocera Corp 多層配線基板及びその製造方法
WO2005076682A1 (fr) * 2004-02-04 2005-08-18 Ibiden Co., Ltd. Carte imprimee multicouche

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017077837A1 (fr) * 2015-11-05 2017-05-11 株式会社村田製作所 Substrat à composant monté
JP6323622B2 (ja) * 2015-11-05 2018-05-16 株式会社村田製作所 部品実装基板
JPWO2017077837A1 (ja) * 2015-11-05 2018-06-14 株式会社村田製作所 部品実装基板
US10154597B2 (en) 2015-11-05 2018-12-11 Murata Manufacturing Co., Ltd. Component mount board
JP2023110828A (ja) * 2022-01-28 2023-08-09 巨擘科技股▲ふん▼有限公司 積層基板の表面処理層構造
JP7445717B2 (ja) 2022-01-28 2024-03-07 巨擘科技股▲ふん▼有限公司 多層基板の表面処理層構造
TWI844319B (zh) 2023-03-24 2024-06-01 景碩科技股份有限公司 印刷電路板封裝結構及其製作方法

Also Published As

Publication number Publication date
JPWO2014024754A1 (ja) 2016-07-25
TW201411740A (zh) 2014-03-16

Similar Documents

Publication Publication Date Title
TWI383719B (zh) Printed wiring board and manufacturing method thereof
KR101368034B1 (ko) 반도체 칩 탑재용 기판 및 그의 제조 방법
US8592691B2 (en) Printed wiring board
JP2011129903A (ja) プリント配線板及びプリント配線板の製造方法
WO2014024754A1 (fr) Carte de circuit pour boîtier de semi-conducteur et procédé de fabrication de celle-ci
JP4592889B2 (ja) 多層回路基板
JP2013093359A (ja) 半導体チップ搭載用基板及びその製造方法
JP5938948B2 (ja) 半導体チップ搭載用基板及びその製造方法
JP2009239184A (ja) 多層印刷配線板
JP2013089913A (ja) 半導体チップ搭載用基板及びその製造方法
JP5682678B2 (ja) 半導体チップ搭載用基板及びその製造方法
JP5942514B2 (ja) 半導体パッケージの製造方法及び半導体パッケージ
JP5432228B2 (ja) プリント配線板およびその製造方法
JP4592890B2 (ja) 多層回路基板
JP4180192B2 (ja) 多層プリント配線基板の製造方法
JP2005012035A (ja) ビアインパッド構造の半導体搭載用プリント配線板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13827860

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014529450

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13827860

Country of ref document: EP

Kind code of ref document: A1