WO2014023013A1 - 具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路 - Google Patents

具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路 Download PDF

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WO2014023013A1
WO2014023013A1 PCT/CN2012/079938 CN2012079938W WO2014023013A1 WO 2014023013 A1 WO2014023013 A1 WO 2014023013A1 CN 2012079938 W CN2012079938 W CN 2012079938W WO 2014023013 A1 WO2014023013 A1 WO 2014023013A1
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film transistor
thin film
source
drain
gate
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French (fr)
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康基善
柯智胜
何文超
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/636,702 priority Critical patent/US20150144950A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines

Definitions

  • the present invention relates to a thin film transistor structure having a large channel width and a thin film transistor substrate circuit, and more particularly to a thin film transistor structure and a thin film transistor substrate circuit of a liquid crystal display having a spiral source and drain.
  • TFT Thin film transistor
  • FPD flat panel display device.
  • the liquid crystal display (LCD) is light and portable. Low power consumption and easy integration have become the research hotspots and leading technologies in the field of information display technology.
  • LCD liquid crystal display
  • Low power consumption and easy integration have become the research hotspots and leading technologies in the field of information display technology.
  • GPS global navigation systems
  • TFT has become a core component of the electronic flat panel display industry. According to the advantages and disadvantages of TFT, how to improve the TFT charging capability has become the direction of many designers.
  • TFTs are mainly available in two forms, symmetric and asymmetric. As the size of the panel increases, more TFTs are obtained in a limited space.
  • the W/L ratio width/length ratio improves the charging capability of the TFT in the same space, and the current LCD panel generally uses an asymmetric TFT.
  • FIG. 1 is a partial schematic view of a conventional TFT substrate circuit of a liquid crystal display.
  • a conventional liquid crystal display TFT substrate 100 includes a plurality of gate lines 110 (horizontal direction) and a plurality of source lines 120 (vertical direction) which together form a matrix line.
  • Each of the pixel cells 130 includes a pixel electrode 130, and each of the pixel electrodes 130 is electrically connected to the gate line 110 and the source line 120 through a thin film transistor 90.
  • each of the thin film transistors 90 is a thin film transistor structure mainly comprising a gate 91 , a source 92 and a drain 93 .
  • the gate electrode 91 is electrically connected to the gate line 110; the source electrode 92 is electrically connected to the source line 120; and the drain electrode 93 is electrically connected to the pixel electrode 130. Therefore, the liquid crystal display TFT substrate circuit controls the pixel electrode 130 (display of a single pixel) through the plurality of gate lines 110 and the plurality of source lines 120 to form an image through the pixel array.
  • FIG. 2 is a top plan view showing the structure of a conventional liquid crystal display thin film transistor, which shows the shape of each electrode of a single one of the thin film transistors 90 (in FIG. 1).
  • the thin film transistor 90 is an asymmetric TFT form in which the gate electrode 91 is disposed on a TFT substrate 100 (in FIG. 1), and the gate electrode 91 forms a main area of the entire thin film transistor structure 90.
  • a gate insulating layer (not shown and labeled for simplicity of the figure) is further disposed on the gate electrode 91, and the source electrode 92 and the drain electrode 93 are disposed on the gate insulating layer ( On the same plane).
  • the source 92 is a U-shaped electrode
  • the drain 93 is an I-shaped electrode
  • the I-shaped drain 93 is surrounded by the U-shaped source 92.
  • the gate electrode 91 is electrically connected to the gate line; the source electrode 92 is electrically connected to the source line; and the drain electrode 93 is electrically connected to the pixel electrode (not shown for the simplified figure but not shown) ).
  • a U-shaped channel 94 is formed between the source 92 and the drain 93. (channel), the length L of the channel 94 is the distance between the source 92 and the drain 93, and the width W (not labeled) of the channel 94 is the source 92 and the drain. The length of the U-shape (the dotted line area in the figure) formed between 93.
  • the charging ability of the TFT is mainly related to the width W and the length L of the channel 94
  • the reduction of the length L and the increase of the width W can enhance the charging ability of the TFT, and the channel 94
  • the length L is limited by the process capability and accuracy of the actual process machine. Therefore, when the exposure accuracy of the exposure machine becomes a bottleneck and it is difficult to break through, the length L of the channel 94 is relatively fixed and it is difficult to adjust to a finer adjustment. Therefore, the TFT design which increases the width W of the channel 94 is more important. .
  • gate drive circuit gate on array
  • the main object of the present invention is to provide a thin film transistor structure having a large channel width and a thin film transistor substrate circuit to solve the problem in the prior art that the channel length and width of the thin film transistor are limited and the charging capability of the thin film transistor cannot be improved. .
  • the invention provides a thin film transistor substrate circuit comprising:
  • a plurality of pixel electrodes respectively located in a matrix square formed by the plurality of gate lines and the plurality of source lines;
  • each of the thin film transistor structures comprising:
  • the source and the drain are in the same plane, respectively spiral and symmetrical and corresponding to each other, forming a double spiral configuration, and a source is formed between the source and the drain
  • the channel, the number of rotations of the source and the drain is between 1 and 2 turns.
  • the present invention further provides a thin film transistor substrate circuit, comprising:
  • a plurality of pixel electrodes respectively located in a matrix square formed by the plurality of gate lines and the plurality of source lines;
  • each of the thin film transistor structures comprising:
  • the source and the drain are in the same plane, respectively spiral and symmetrical and corresponding to each other, forming a double spiral configuration, and a source is formed between the source and the drain aisle.
  • the present invention further provides a thin film transistor structure having a large channel width, comprising:
  • the source and the drain are in the same plane, respectively spiral and symmetrical and corresponding to each other, forming a double spiral configuration, and a source is formed between the source and the drain aisle.
  • a gate insulating layer is further disposed on the gate, and the source and the drain are disposed on the gate insulating layer.
  • the number of rotations of the source and the drain is between 1 and 2 turns.
  • the thin film transistor has a large area of 5850 ⁇ m 2 and the channel has a width of 324 ⁇ m.
  • the thin film transistor structure is applied to a gate driving circuit.
  • the source and the drain of the present invention respectively have a spiral shape and are symmetrical and corresponding to each other, forming a double spiral configuration, so that the channel width between the two is increased, thereby increasing the channel width to length ratio (W/ L) to improve the charging ability of the thin film transistor
  • TFT liquid crystal display thin film transistor
  • FIG. 2 is a top plan view showing the structure of the liquid crystal display thin film transistor of FIG. 1.
  • FIG 3 is a partial schematic view showing a TFT substrate circuit of a liquid crystal display according to an embodiment of the present invention.
  • FIG. 4 is a top plan view showing the structure of a thin film transistor of a liquid crystal display according to an embodiment of the present invention.
  • FIG. 5 is a top plan view showing the structure of a thin film transistor of a liquid crystal display according to another embodiment of the present invention.
  • FIG. 3 is a thin film transistor of a liquid crystal display according to an embodiment of the present invention.
  • Transistor A partial schematic view of a TFT substrate circuit.
  • a liquid crystal display TFT substrate 100 includes a plurality of gate lines 110 (horizontal direction) and a plurality of source lines 120 (vertical direction) which together form a matrix line.
  • Each of the pixel cells 130 includes a pixel electrode 130.
  • Each of the pixel electrodes 130 is electrically connected to the gate line 110 and the source line 120 through a thin film transistor 20 .
  • each of the thin film transistors 20 is a thin film transistor structure mainly comprising a gate electrode 21, a source electrode 22 and a drain electrode 23.
  • the gate electrode 21 is electrically connected to the gate line 110; the source electrode 22 is electrically connected to the source line 120; and the drain electrode 23 is electrically connected to the pixel electrode 130. Therefore, the liquid crystal display TFT substrate circuit controls the pixel electrode 130 (display of a single pixel) through the plurality of gate lines 110 and the plurality of source lines 120 to form an image through the pixel array.
  • FIG. 4 is a top plan view showing the structure of a thin film transistor of a liquid crystal display according to an embodiment of the present invention, showing the shape of each electrode of the single thin film transistor 20 (in FIG. 3).
  • the thin film transistor 20 is an asymmetric TFT form in which the gate electrode 21 is disposed on a TFT substrate 100 (in FIG. 3), and the gate electrode 21 forms a main area of the entire thin film transistor structure 20.
  • a gate insulating layer (not shown and labeled for simplicity of the figure) is further disposed on the gate electrode 21, and the source electrode 22 and the drain electrode 23 are disposed on the gate insulating layer ( On the same plane).
  • the source 22 and the drain 23 respectively have a spiral shape (one rotation, respectively. 360°), the spiral source 22 and the drain 23 are symmetrical and corresponding to each other to form a double spiral configuration.
  • the gate electrode 21 is electrically connected to the gate line; the source electrode 22 is electrically connected to the source line; and the drain electrode 23 is electrically connected to the pixel electrode (not shown for the simplified figure but not shown) ).
  • a channel 24 is formed between the source 22 and the drain 23. (channel), the channel 24 is in the shape of a "spiral in-spiral out".
  • the length L of the channel 24 is the distance between the source 22 and the drain 23, and the width W (not labeled) of the channel 24 is between the source 22 and the drain 23.
  • the length of the shape of "spiral in-helix out" (dotted line area in the figure) is formed.
  • the area of the thin film transistor 20 is, for example, 3400 ⁇ m 2
  • the width W of the channel 24 is, for example, 161 ⁇ m. Since the charging ability of the TFT is mainly related to the width W and the length L of the channel 24, the reduction of the length L and the increase of the width W (increasing the W/L ratio) can enhance the charging ability of the TFT.
  • the width W of the channel 24 is made by forming the source 22 and the drain 23 into a mutually symmetrical and corresponding double helix shape. The increase is made to increase the W/L ratio to increase the charging ability of the thin film transistor 20.
  • FIG. 5 is a schematic top plan view showing a structure of a liquid crystal display thin film transistor according to another embodiment of the present invention.
  • the thin film transistor 20' of the present embodiment is substantially similar to the thin film transistor 20 of the embodiment of the present invention, and thus the same component name is used, but the difference is that in the present embodiment, the source 22'
  • the number of spiral turns of the drain 23' is greater than the number of spiral turns of the source 22 and the drain 23 in the embodiment of FIG. 4, the source 22' and the The drain 23' is rotated by 1.5 turns (540°), respectively, so that the width W of the channel 24' (the dotted line area in the drawing) can be further increased, thereby increasing the W/L ratio.
  • the area of the thin film transistor 20' is, for example, 5850 ⁇ m 2
  • the width W of the channel 24' is, for example, 324 ⁇ m.
  • the present invention does not limit the area size of the thin film transistors 20, 20' and the number of rotations of the source 22 and the drain 23.
  • the number of rotations of the source 22 and the drain 23 is between 1 turn (360°) and 2 turns (720°), and the user can design the source 22, 22 according to actual needs. 'The number of revolutions with the drains 23, 23' to obtain a larger channel width for better charging capability.
  • the channel length and width of the thin film transistor are limited to change, and the W/L ratio cannot be effectively improved to improve the charging capability of the thin film transistor.
  • the thin film transistor 20, 20' of the present invention forms a mutual symmetry between the source 22, 22' and the drain 23, 23' when the length L of the channel 24, 24' is fixed.
  • the corresponding double helix shape increases the width W of the channels 24, 24', thereby increasing the W/L ratio to increase the charging capability of the thin film transistors 20, 20'.

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Description

具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路 技术领域
本发明涉及一种具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路，特别是涉及一种具有螺旋形源极与漏极的液晶显示器的薄膜晶体管构造及薄膜晶体管基板电路。
 背景技术
薄膜晶体管( thin film transistor, TFT) 技术是一种从20世纪90年代开始发展起来的大规模半导体全集成电路制造技术，是液晶平板显示装置(flat panel display，FPD)发展的基础。而液晶显示器(liquid crystal display，LCD)以其轻巧便携、 低功耗和易集成等特点成为目前信息显示技术领域的研究热点和主导技术，目前主要应用于数字照相机、笔记本计算机、全球导航系统(GPS)、各种监视器等。随着信息社会的到来，平板显示技术的应用领域不断拓宽，该领域的研究工作也不断深入，向高层次发展。目前TFT已经成为电子平板显示行业的核心部件，根据TFT存在的优缺点，如何提高TFT充电能力成为许多设计者努力的方向。
传统的TFT主要有两种形式，即对称式以及非对称式，随着面板尺寸的不断增大，为了在有限的空间内获得更大的TFT W/L比(宽/长比)，而使同样的空间下的TFT的充电能力提升，目前的LCD Panel普遍使用非对称式TFT。
请参照图1所示，图1是一种现有液晶显示器TFT基板电路的局部示意图。如图1所示，一现有液晶显示器TFT基板100包含多条栅极线110(水平方向)及多条源极线120(垂直方向)，其共同形成一矩阵式线路。其中，每一矩阵方格中包含一像素电极130，每一所述像素电极130通过一薄膜晶体管90分别与所述栅极线110及所述源极线120电性连接。
详细说来，如图1所示，每一所述薄膜晶体管90是一薄膜三极管构造，其主要包含一栅极91、一源极92及一漏极93。其中，所述栅极91电性连接所述栅极线110；所述源极92电性连接所述源极线120；以及所述漏极93电性连接所述像素电极130。因此，液晶显示器TFT基板电路通过所述多条栅极线110及多条源极线120来控制所述像素电极130(单一像素的显示)，从而通过像素阵列以组成影像。
请参照图2所示，图2是一种现有液晶显示器薄膜晶体管构造的俯视示意图，其显示单一个所述薄膜晶体管90(在图1中)的各个电极的形状。所述薄膜晶体管90是一种非对称式的TFT形态，其中所述栅极91是设于一TFT基板100(在图1中)上，而所述栅极91形成整个薄膜晶体管构造90主要面积。另外，所述栅极91上还设有一栅极绝缘层(为简化图形故未绘示与标示)，而所述源极92与所述漏极93则是设于所述栅极绝缘层(同一平面)上。
再者，所述源极92是一U字形电极，所述漏极93则是一I字形电极，所述I字形的漏极93被所述U字形的源极92所包围。并且，所述栅极91电性连接于栅极线；所述源极92电性连接于源极线；以及所述漏极93电性连接于像素电极(为简化图形亦省略而未绘示)。
如图2所示，所述源极92与所述漏极93之间形成一U字形的通道94 (channel)，所述通道94的长度L即所述源极92与所述漏极93的间距，而所述通道94的宽度W(未标示)则为所述源极92与所述漏极93之间所形成U字形(图中点线区域)的长度。
由于TFT的充电能力主要与所述通道94的宽度W和长度L相关，降低长度L和提高宽度W(提高W/L比)都可以对TFT的充电能力有提升的作用，而所述通道94的长度L受限于实际制程机台的制程能力和精度。因此，当曝光机的曝光精度成为瓶颈而难以突破的时候，所述通道94的长度L则相对固定难以向更精细化调整，因此增加所述通道94的宽度W的TFT设计则显得更为重要。
再者。随着栅极驱动电路(gate on array, GOA)技术的成熟，GOA电路中所需用具有大通道宽度的TFT被越来越广范的应用，更迫切需求一种具有更大通道宽度的薄膜晶体管构造。
因此，有必要提供一种具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路，以解决现有技术所存在的问题。
 技术问题
本发明的主要目的是提供一种具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路，以解决现有技术中，因为薄膜晶体管的通道长度与宽度改变有限，无法提高薄膜晶体管的充电能力的问题。
 技术解决方案
本发明提供一种薄膜晶体管基板电路，其包含：
多条栅极线，呈水平方向排列；
多条源极线，呈垂直方向排列；
多个像素电极，分别位于所述多条栅极线及所述多条源极线形成的矩阵方格中；及
多个薄膜晶体管，每一所述薄膜晶体管分别对应一个像素电极，每一所述薄膜晶体管构造包含：
一栅极，电性连接一所述栅极线；
一源极，电性连接一所述源极线；及
一漏极，电性连接一所述像素电极；
其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道，所述源极与所述漏极的旋转圈数是介于1圈至2圈。
为达上述目的，本发明另提供一种薄膜晶体管基板电路，其包含：
多条栅极线，呈水平方向排列；
多条源极线，呈垂直方向排列；
多个像素电极，分别位于所述多条栅极线及所述多条源极线形成的矩阵方格中；及
多个薄膜晶体管，每一所述薄膜晶体管分别对应一个像素电极，每一所述薄膜晶体管构造包含：
一栅极，电性连接一所述栅极线；
一源极，电性连接一所述源极线；及
一漏极，电性连接一所述像素电极；
其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道。
为达上述目的，本发明另提供一种具有大通道宽度的薄膜晶体管构造，其包含：
一栅极，电性连接一栅极线；
一源极，电性连接一源极线；及
一漏极，电性连接一像素电极；
其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道。
在本发明的一实施例中，所述栅极上还设有一栅极绝缘层，所述源极与所述漏极是设于所述栅极绝缘层上。
在本发明的一实施例中，所述源极与所述漏极的旋转圈数是介于1圈至2圈。
在本发明的一实施例中，所述薄膜晶体管的面积大为5850μm2，所述通道的宽度为324μm。
在本发明的一实施例中，所述薄膜晶体管构造应用于一栅极驱动电路中。
 有益效果
本发明的所述源极与所述漏极分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，使两者间的通道宽度增加，从而提高通道宽长比(W/L)，以提高所述薄膜晶体管的充电能力
 附图说明
图1是一种现有液晶显示器薄膜晶体管(TFT)基板电路的局部示意图。
图2是图1的液晶显示器薄膜晶体管构造的俯视示意图。
图3是本发明一实施例的液晶显示器的TFT基板电路的局部示意图。
图4是本发明一实施例的液晶显示器薄膜晶体管构造的俯视示意图。
图5是本发明另一实施例的液晶显示器薄膜晶体管构造的俯视示意图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明。为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图3所示，图3是本发明一实施例的液晶显示器的薄膜晶体管( thin film transistor, TFT)基板电路的局部示意图。如图3所示，一液晶显示器TFT基板100包含多条栅极线110(水平方向)及多条源极线120(垂直方向)，其共同形成一矩阵式线路。其中，每一矩阵方格中包含一像素电极130，每一所述像素电极130通过一薄膜晶体管20分别与所述栅极线110及所述源极线120电性连接。
详细说来，如图3所示，每一所述薄膜晶体管20是一薄膜三极管构造，其主要包含一栅极21、一源极22及一漏极23。其中，所述栅极21电性连接所述栅极线110；所述源极22电性连接所述源极线120；以及所述漏极23电性连接所述像素电极130。因此，液晶显示器TFT基板电路通过所述多条栅极线110及多条源极线120来控制所述像素电极130(单一像素的显示)，从而通过像素阵列以组成影像。
请参照图4所示，图4是本发明一实施例的液晶显示器薄膜晶体管构造的俯视示意图，其显示单一个所述薄膜晶体管20(在图3中)的各个电极的形状。所述薄膜晶体管20是一种非对称式的TFT形态，其中所述栅极21是设于一TFT基板100(在图3中)上，而所述栅极21形成整个薄膜晶体管构造20主要面积。另外，所述栅极21上还设有一栅极绝缘层(为简化图形故未绘示与标示)，而所述源极22与所述漏极23则是设于所述栅极绝缘层(同一平面)上。
再者，所述源极22与所述漏极23分别呈一螺旋形(分别旋转1圈, 360°)，所述螺旋形的源极22与漏极23相互对称及对应，形成一种双螺旋形的配置。并且，所述栅极21电性连接于栅极线；所述源极22电性连接于源极线；以及所述漏极23电性连接于像素电极(为简化图形亦省略而未绘示)。
如图4所示，所述源极22与所述漏极23之间形成一通道24 (channel)，所述通道24是一“螺旋入-螺旋出”的形状。所述通道24的长度L即所述源极22与所述漏极23的间距，而所述通道24的宽度W(未标示)则为所述源极22与所述漏极23之间所形成“螺旋入-螺旋出”(图中点线区域)形状的长度。
在本实施例中，所述薄膜晶体管20的面积大小例如为3400μm2，所述通道24的宽度W例如为161μm。由于TFT的充电能力主要与所述通道24的宽度W和长度L相关，降低长度L和提高宽度W(提高W/L比)都可以对TFT的充电能力有提升的作用。在本实施例中，在所述通道24的长度L固定的情况下，通过将所述源极22与所述漏极23形成相互对称及对应的双螺旋形状，使所述通道24的宽度W增加，从而提高W/L比，以提高所述薄膜晶体管20的充电能力。
再者。随着栅极驱动电路(gate on array, GOA)技术的成熟，GOA电路中所需用具有大通道宽度的TFT被越来越广范的应用，本实施例亦能应用于此GOA电路中。
如图5所示，图5是本发明另一实施例的液晶显示器薄膜晶体管构造的俯视示意图。本实施例的薄膜晶体管20’与本发明图4实施例的薄膜晶体管20大致相似，因此沿用相同的组件名称，但二者的不同之处在于：在本实施例中，所述源极22’与所述漏极23’的螺旋形旋转圈数较图4实施例中的所述源极22与所述漏极23的螺旋形旋转圈数更为增加，所述源极22’与所述漏极23’分别是旋转1.5圈(540°)，因此所述通道24’(图中点线区域)的宽度W可进一步增加，从而提高W/L比。
在本实施例中，所述薄膜晶体管20’的面积大小例如为 5850μm2，所述通道24’的宽度W例如为324μm。
再者，本发明并不限制所述薄膜晶体管20,20’的面积大小以及所述源极22与所述漏极23的旋转圈数。优选地，所述源极22与所述漏极23的旋转圈数是介于1圈(360°)至2圈(720°)，使用者可依实际需要来设计所述源极22,22’与所述漏极23,23’的旋转圈数以获得更大的通道宽度，从而获得更好的充电能力。
综上所述，相较于现有技术中，薄膜晶体管的通道长度与宽度改变有限，无法有效提高W/L比，以提高薄膜晶体管的充电能力。本发明的所述薄膜晶体管20,20’在所述通道24,24’的长度L固定的情况下，通过将所述源极22,22’与所述漏极23,23’形成相互对称及对应的双螺旋形状，使所述通道24,24’的宽度W增加，从而提高W/L比，以提高所述薄膜晶体管20,20’的充电能力。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
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Claims (14)

  1. 一种薄膜晶体管基板电路，其包含：
    多条栅极线，呈水平方向排列；
    多条源极线，呈垂直方向排列；
    多个像素电极，分别位于所述多条栅极线及所述多条源极线形成的矩阵方格中；及
    多个薄膜晶体管，每一所述薄膜晶体管分别对应一个像素电极，所述薄膜晶体管基板电路的特征在于：每一所述薄膜晶体管构造包含：
    一栅极，电性连接一所述栅极线；
    一源极，电性连接一所述源极线；及
    一漏极，电性连接一所述像素电极；
    其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道，以及所述源极与所述漏极的旋转圈数是介于1圈至2圈。
  2. 如权利要求1所述的薄膜晶体管基板电路，其特征在于：所述栅极上还设有一栅极绝缘层，所述源极与所述漏极是设于所述栅极绝缘层上。
  3. 如权利要求1所述的薄膜晶体管基板电路，其特征在于：所述薄膜晶体管的面积大为5850μm2，所述通道的宽度为324μm。
  4. 如权利要求1所述的薄膜晶体管构造，其特征在于：所述薄膜晶体管基板电路是一栅极驱动电路。
  5. 一种薄膜晶体管基板电路，其包含：
    多条栅极线，呈水平方向排列；
    多条源极线，呈垂直方向排列；
    多个像素电极，分别位于所述多条栅极线及所述多条源极线形成的矩阵方格中；及
    多个薄膜晶体管，每一所述薄膜晶体管分别对应一个像素电极，所述薄膜晶体管基板电路的特征在于：每一所述薄膜晶体管构造包含：
    一栅极，电性连接一所述栅极线；
    一源极，电性连接一所述源极线；及
    一漏极，电性连接一所述像素电极；
    其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道。
  6. 如权利要求5所述的薄膜晶体管基板电路，其特征在于：所述栅极上还设有一栅极绝缘层，所述源极与所述漏极是设于所述栅极绝缘层上。
  7. 如权利要求5所述的薄膜晶体管基板电路，其特征在于：所述源极与所述漏极的旋转圈数是介于1圈至2圈。
  8. 如权利要求5所述的薄膜晶体管基板电路，其特征在于：所述薄膜晶体管的面积大为5850μm2，所述通道的宽度为324μm。
  9. 如权利要求5所述的薄膜晶体管构造，其特征在于：所述薄膜晶体管基板电路是一栅极驱动电路。
  10. 一种具有大通道宽度的薄膜晶体管构造，其特征在于：所述薄膜晶体管构造包含：
    一栅极，电性连接一栅极线；
    一源极，电性连接一源极线；及
    一漏极，电性连接一像素电极；
    其中，所述源极与所述漏极在同一平面上，分别呈一螺旋形且相互对称及对应，形成一种双螺旋形的配置，并且所述源极与所述漏极之间形成一通道。
  11. 如权利要求10所述的薄膜晶体管构造，其特征在于：所述栅极上还设有一栅极绝缘层，所述源极与所述漏极是设于所述栅极绝缘层上。
  12. 如权利要求10所述的薄膜晶体管构造，其特征在于：所述源极与所述漏极的旋转圈数是介于1圈至2圈。
  13. 如权利要求10所述的薄膜晶体管构造，其特征在于：所述薄膜晶体管的面积大为5850μm2，所述通道的宽度为324μm。
  14. 如权利要求10所述的薄膜晶体管构造，其特征在于：所述薄膜晶体管构造应用于一栅极驱动电路中。
PCT/CN2012/079938 2012-08-09 2012-08-10 具有大通道宽度的薄膜晶体管构造及薄膜晶体管基板电路 Ceased WO2014023013A1 (zh)

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