WO2014019752A1 - Verfahren zur herstellung eines optoelektronischen halbleiterchips und optoelektronischer halbleiterchip - Google Patents
Verfahren zur herstellung eines optoelektronischen halbleiterchips und optoelektronischer halbleiterchip Download PDFInfo
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- WO2014019752A1 WO2014019752A1 PCT/EP2013/062022 EP2013062022W WO2014019752A1 WO 2014019752 A1 WO2014019752 A1 WO 2014019752A1 EP 2013062022 W EP2013062022 W EP 2013062022W WO 2014019752 A1 WO2014019752 A1 WO 2014019752A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
- H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/814—Bodies having reflecting means, e.g. semiconductor Bragg reflectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
- H10P14/274—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using seed materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
- H10P14/276—Lateral overgrowth
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2921—Materials being crystalline insulating materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
- H10P14/3216—Nitrides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3416—Nitrides
Definitions
- optoelectronic semiconductor chip specified.
- an optoelectronic semiconductor chip is specified.
- An object to be solved is a method for producing an optoelectronic semiconductor chip
- the method comprises the step of providing a growth substrate.
- the growth substrate is, for example, a sapphire substrate.
- other substrates such as out
- Silicon, silicon carbide, gallium nitride, gallium arsenide or gallium phosphide, can be used.
- the growth substrate has a growth side, which is designed to epitaxially deposit thereon a semiconductor layer sequence.
- the method comprises the step of growing or applying at least one nucleation layer on the growth side.
- Nucleation layer can be grown directly on the growth side, so that the growth side and the Touch nucleation layer. It is likewise possible for a buffer layer to be applied, in particular directly between the growth side and the nucleation layer.
- the nucleation layer is produced, for example, by sputtering or epitaxial growth.
- y -S is 0.15 or y ⁇ 0.05 or y ⁇ 0.025.
- the nucleation layer is an aluminum nitride layer or an aluminum oxynitride layer.
- Nucleation layer can over the entire thickness of a same within the manufacturing tolerances
- the method comprises the step of growing or applying one
- the masking layer is preferably produced directly on the nucleation layer.
- Masking layer preferably comprises one or more of the following materials or consists of one or more of these materials: a silicon nitride, a
- Silica a silicon oxynitride, a boron nitride, a magnesium oxide.
- the masking layer is structured.
- the structuring is preferably carried out phototechnically and lithographically.
- the masking layer removes a material of the previously applied masking layer.
- the masking layer is already applied structured. Will be a material of
- the nucleation layer preferably remains unaffected or substantially
- the method optionally includes the step of growing a gallium nitride based growth layer.
- the growth layer is in such areas particularly directly on the
- the term based may mean that the essential crystal components are each formed from the materials mentioned. Other substances in low concentrations, in particular dopants, may also be present.
- the method comprises the step of partially removing the nucleation layer and / or the growth layer in not of the
- Masking layer covered areas In other words, the nucleation layer and / or the growth layer is then partially etched back. Alternatively or additionally, it is possible for a further, thinner masking layer to be applied to the nucleation layer or to the growth layer
- the method comprises the step of growing a n Al In] __ n _ m N m Ga-based semiconductor layer sequence, where 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1, and n + m ⁇ 1.
- the semiconductor layer sequence comprises one or more active layers.
- the method is used to produce an optoelectronic semiconductor chip.
- the semiconductor chip to be produced is, in particular, a light-emitting diode chip, a laser diode chip or even a photodiode.
- the method is configured for producing an optoelectronic semiconductor chip, such as a light-emitting diode. The method comprises
- Step D) is optional.
- a monocrystalline substrate is usually used as the growth substrate for an epitaxy.
- a reduction in a defect density or to allow a better light extraction is on such
- Semiconductor layer sequence is achieved a significant improvement in the crystal quality of the semiconductor layer sequence.
- Such a process is also known as Facet Assisted Epitaxial Lateral Overgrowth, or FACELO for short.
- the individual layers by means of epitaxy, about with
- Masking layer can be produced by sputtering.
- the semiconductor layer sequence and the growth layer are
- step D) is carried out. That means, in particular directly on the
- the partial removal of the growth layer in step E) takes place with the addition of a reactant gas for hydrogen and preferably with the addition of a reactant gas for nitrogen.
- the reactant gas for nitrogen is in particular NH3 or N2H4.
- the reactant gas for hydrogen may be H2 or SiH4.
- the second masking layer is a nitride masking.
- the nitride masking is in particular a silicon nitride layer. It is the nitride masking of a reactant gas for Silicon and a reactant gas out for nitrogen out. The generation of the nitride masking takes place in step E).
- these two reactant gases may be formed by the same gas, a partial material removal of the growth layer and / or the nucleation layer. In other words, etching back the growth layer and / or the nucleation layer is achieved by generating the nitride masking at the same time.
- Areas that are not covered by the masking layer in plan view of the growth side at least 50% or at least 60%. Alternatively or additionally, this degree of coverage is at most 90% or at most 80%.
- the degree of coverage is between 65% and 75% inclusive.
- step E) only or substantially only material is removed from the growth layer and not from the nucleation layer. This does not necessarily exclude that at a the
- the nitride masking may in this case cover the masking layer, which is preferably located directly on the nucleation layer.
- a material of the growth layer is removed only so far that the underlying
- a thickness of the nitride masking is at least a factor of 50 or
- Masking layer For example, the thickness of the
- Nitride masking at most 2.0 nm or at most 1.0 nm or at most 0.5 nm.
- the thickness of the masking layer is for example at least 25 nm or at least 50 nm or at least 100 nm. Alternatively or additionally, the thickness or the average thickness nitride masking between one and three atomic layers.
- Degree of coverage with the Nitridmask ist is preferably between 50% and 85% inclusive, in particular at about 70%.
- the partial removal of the growth layer and / or the nucleation layer in step E) is effected by a lack of the reactant gas for
- step E) in regions not covered by the masking layer, at the nucleation layer and / or at the growth layer, a
- the growing islands are set to that of these growing islands
- the growing islands are such areas of
- Anwachsinseln an average diameter of at least 10 nm or at least 15 nm or at least 25 nm. Alternatively or additionally, the average
- Diameter of the growing islands at most 250 nm or at most 150 nm or at most 80 nm.
- Structure size of the masking layer For example, the feature size of the growth islands on the nanometer scale and the feature size of the masking layer on the
- the method comprises a step E1).
- step E1) epitaxial lateral overgrowth of smaller structures to triangular or trapezoidal cross-sectional structures is performed starting from the growing islands.
- a lateral overgrowth is started in each case starting from the growing islands.
- a multiplicity of small, separate pyramid-like structures first form.
- Emerging pyramidal structures then grow together in the course of the process to form a larger structure.
- This larger structure as seen in plan view of the growth side, is essentially limited to those areas that are not covered by the masking layer.
- a vertical growth rate in step E1) is greater than a horizontal growth rate.
- the vertical growth rate refers to growth in the direction perpendicular to the growth side and the horizontal growth rate refers to a growth parallel to the growth side
- the horizontal growth rate by at least a factor of 1.5 or by at least a factor of 2 and / or by a maximum of a factor of 5 or by a factor of at most 4.
- the method comprises a step E2), which follows the step E1) and / or the step E).
- step E2) an epitaxial lateral overgrowth occurs to a continuous one
- the coalescing layer is preferably a coherent, hole-free layer.
- the Coalescing layer preferably covers the entire growth side of the growth substrate.
- step E2) the horizontal growth rate exceeds the vertical one
- Growth rate for example by at least a factor of 1.25 or by at least a factor of 1.5.
- step E1) and / or step E2) is performed after step E) and before step F).
- a middle layer of the masking layer is formed from silicon nitride.
- this middle layer is on both sides depending on layers
- the layer of silicon nitride serves as a predetermined breaking point upon detachment of the semiconductor layer sequence from the growth substrate.
- the nitride masking can serve as a predetermined breaking point in the areas not covered by the masking layer.
- the detachment from the semiconductor layer sequence is hereby preferably a laser lift-off method.
- Masking layer formed by a plurality of masking islands.
- the masking islands are preferably disc-like Areas that have a circular, a hexagonal or an octagonal basic shape, seen in plan view.
- a mean diameter of the masking islands is at least 0.5 ⁇ m or at least 0.8 ⁇ m or at least 1.0 ⁇ m.
- the average diameter is at most 7.5 ym or at most 5 ym or at most 4 ym. According to at least one embodiment, the
- Masking islands a mean distance from each other of at least 0.5 ym or at least 1 ym or from
- this distance is at least 2 ym up. Alternatively or additionally, this distance is at most 10 ym or at most 7.5 ym.
- the Bragg mirror is alternately made of layers of aluminum nitride and of layers of silicon, in particular silicon oxide or
- the Bragg mirror can be mounted directly on the growth side.
- the subsequent layers immediately and in the following order follow one another: the growth substrate, the nucleation layer, the growth layer, the nitride masking
- the masking layer is preferably located directly between the nucleation layer and the coalescing layer.
- an optoelectronic semiconductor chip is specified.
- the semiconductor chip is made by a method as described in connection with one or more of the above embodiments. Characteristics of the method are therefore also for the
- LED chip is, a growth substrate with a
- a masking layer opposite side of the nucleation layer is a masking layer.
- a n Al In] __ n _ m N m Ga-based semiconductor layer sequence with at least one active layer is formed.
- a nitride masking is located in areas which are not covered by the masking layer in a plan view of the growth side, between the nucleation layer and the semiconductor layer sequence.
- Figures 1, 3 and 4 are schematic representations of
- Figure 2 is a schematic plan view of a growth side in a method described herein.
- FIGS 5 to 7 are schematic sectional views of
- FIG. 1 shows an exemplary embodiment of a method for producing an optoelectronic semiconductor chip 1 in schematic sectional views.
- a growth substrate 2 having a growth side 20 is provided.
- the growth substrate 2 is, in particular, a sapphire substrate.
- Nucleation layer 3 is generated.
- the nucleation layer 3 is, for example, an aluminum nitride layer.
- Nucleation layer 3 may contain small amounts of oxygen. In particular, an oxygen content increases
- the nucleation layer 3 may be an AlGaN layer. In the direction away from the growth substrate 2, a gallium content in the nucleation layer 2 may increase.
- the nucleation layer 3 preferably has a thickness between 10 nm and 3000 nm inclusive, in particular between 20 nm and 200 nm inclusive. It is also possible that the nucleation layer 3 has a plurality of partial layers.
- the nucleation layer 3 is produced by means of epitaxy, such as MOVPE, HVPE or MBE, or else by means of sputtering.
- epitaxy such as MOVPE, HVPE or MBE
- sputtering there is a buffer layer 31 between the nucleation layer 3 and the growth substrate 2.
- the nucleation layer 3 may also be produced directly on the growth side 20.
- Nucleation layer 3 preferably directly, a
- Masking layer 3 has a plurality of
- Masking islands which have a diameter of preferably less than 5 ym, in particular about 2 ym, see also Figure 2A.
- a spacing of adjacent masking islands is about 1 ym.
- a thickness of the masking islands is about 200 nm.
- the masking layer 4 is defined by a silicon oxide layer, followed by a silicon nitride layer, and a silicon nitride layer
- Masking layers are also specified in the publication DE 10 2011 012 608 AI, whose disclosure content by
- FIG. 1D it is shown that in not of the
- the growth layer 5 is a group III-V nitride layer, preferably a doped or undoped GaN layer.
- the growth layer 5 has, for example, a thickness of at least 10 nm or at least 20 nm or at least 50 nm. Alternatively or additionally, the thickness of the growth layer 5 is at most 300 nm or at most 200 nm. The thickness of the growth layer is preferred 5 by at least a factor of 2 or at least one
- a reactant gas for hydrogen is added, preferably S1H4.
- etching back of the growth layer 5 is performed.
- the addition of the reactant gas to hydrogen may be with or without the addition of a nitrogen reactant gas.
- a reactant gas is also added for nitrogen, for example NH3.
- Nitride masking 7 is preferably between inclusive
- the nitride masking 7 is preferably only thin. By not covered by the Nitridmask réelle 7 areas of the growth layer 5 are
- the growth islands 55 have dimensions in the nanometer range.
- a nitride masking 7 produced in this way can also be used as in situ masking
- a material of the growing out of the growing islands 55 areas is preferably GaN.
- the lateral overgrowing is continued so that, seen in cross-section, larger, triangular
- Growth structures 58 are formed. The from the Growth islands 55 formed smaller areas that grow together to the growth structures 58 are symbolized in Figure IG as dashed lines. In FIG. 1H, starting from the growth structures 58, a lateral overgrowth takes place to form a coalescing layer 8, which covers the entire growth side 20. On the
- Coalescing layer 8 a semiconductor layer sequence 6 is deposited with at least one active layer 65.
- a process, as carried out in conjunction with FIG. 1, preferably takes place with the following
- Masking layer 4 photolithographically structured, wherein
- Masking islands with a diameter of about 2 ym and a distance of about 1 ym are generated.
- the areas masked by the masking layer 4 are approximately regular octagons.
- an approximately 90 nm thick, undoped GaN layer is now deposited as growth layer 5 in the openings between the masking islands.
- a reactant gas for gallium, in particular trimethylgallium, stopped and SiH4 is in the
- Headed epitaxy reactor It then prevails preferably a N2 / H2 / NH3 environment with additional S1H4. During this
- the deposition of the nitride masking 7 and the back etching of the growth layer 5 are competing processes.
- a re-etching time is about five minutes. Subsequently, the growth conditions for
- Gallium nitride selected such that the triangular growth structures seen in cross section 58 form.
- the reactant gas for hydrogen and for silicon is closed again.
- the coalescing layer 8 is produced, so that a 2D-GaN layer results, which the
- Masking layer 4 has laterally overgrown.
- Dislocation density of the coalescing layer 8 is then less than 10 ⁇ per square centimeter.
- the Hall order layer sequence 6 is deposited on this planar coalescing layer 8.
- the coalescing layer 8 is doped or undoped gallium nitride.
- FIG. 2A shows a plan view of the growth side 20 after the method step according to FIG. A
- Sectional view along the line B can be seen in FIG. 2B, along the line C in FIG. 2C, a height h in nm is plotted along a section line x in ym. In FIG. 2C, therefore, a middle region in FIG. 2B is shown
- Aluminum-containing layers such as AlGaN or A1N or A10N have a smaller lattice constant than GaN. Accordingly, GaN typically grows compressively
- Growth layer 5 arise GaN nano islands.
- the growth layer 5 is thus no longer closed laterally. This enables a lateral relaxation of the growth layer 5.
- the degree of relaxation determined by a size of the GaN nano-islands of the growth layer 5, can be adjusted approximately via the thickness of the growth layer 5 and / or over a duration of etching back. The more that is etched back and / or the thinner the growth layer 5 is produced, the less strong is the deflection of the growth substrate 2 during the epitaxial generation of the semiconductor layer sequence 6.
- etching back of the growth layer 5 takes place without addition of a reactant gas Silicon. Accordingly, no nitride masking is formed.
- FIG. 4 shows an exemplary embodiment of the semiconductor chip 1.
- the nucleation layer 3 is in this case part of a Bragg mirror 33, which has a plurality of nucleation layers 3, which are formed from aluminum nitride. Between the aluminum nitride layers 3 are each layers 32 of silicon dioxide or silicon nitride. At the
- FIG. 6 shows that on the semiconductor layer sequence 6 a carrier substrate 9, for example made of silicon,
- FIG. 6 also schematically illustrates a defect reduction, with reference to drawn crystal defects 85. These crystal defects 85, in particular dislocations, buckle at lateral boundary surfaces of the growth structures 58 and the structures formed from the growth islands 35, 55. As a result of the multiplicity of growth islands 35, 55, an efficient defect reduction can already be achieved within the growth structures 58. After the growth structures 58 have been produced and before, during and / or after the generation of the coalescing layer 8 from GaN, it is additionally possible to grow an AlGaN layer, not shown, as in all others
- a thickness of this AlGaN layer is preferably at least 1 nm or 5 nm and / or
- an Al content of this AlGaN layer is preferably at least 1% or 5% or 20% and / or at most 100% or 85% or 60%.
- This AlGaN layer is preferably undoped but may be doped.
- this AlGaN layer nucleates directly on the masking layer 4.
- This AlGaN layer can thus be in direct contact with the masking layer 4 and / or with the coalescing layer 8 and / or with the
- this AlGaN layer can be grown within the coalescing layer 8. It may also be in this AlGaN layer to a
- Growth structures 58 are overgrown by this AlGaN layer, or this AlGaN layer is a layer which is penetrated by the growth structures 58 and projected away from the growth substrate 58 in the direction away from the growth substrate 2.
- FIG. 7 schematically illustrates a separation of the growth substrate 2 from the semiconductor layer sequence 6. The separation takes place in particular by a
- Silicon nitride layer 42 which is located between silicon dioxide layers 41, 43 of masking layer 4, acts as a predetermined breaking point. On the sapphire growth substrate 2 remain the
- Nucleation layer 3 made of aluminum nitride and the first layer 41 of silicon oxide.
- the layer of silicon oxide remaining on the semiconductor layer sequence 6 can serve as a hard mask for the generation of structured light coupling-out structures. Corresponding coupling-out structures for
- the silicon dioxide layer 41 can be subsequently removed. This is a repeated one
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Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201380041098.9A CN104508840B (zh) | 2012-07-31 | 2013-06-11 | 用于制造光电子半导体芯片的方法和光电子半导体芯片 |
| US14/418,424 US9293640B2 (en) | 2012-07-31 | 2013-06-11 | Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip |
| DE201311003800 DE112013003800A5 (de) | 2012-07-31 | 2013-06-11 | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102012107001.6 | 2012-07-31 | ||
| DE102012107001.6A DE102012107001A1 (de) | 2012-07-31 | 2012-07-31 | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2014019752A1 true WO2014019752A1 (de) | 2014-02-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| PCT/EP2013/062022 Ceased WO2014019752A1 (de) | 2012-07-31 | 2013-06-11 | Verfahren zur herstellung eines optoelektronischen halbleiterchips und optoelektronischer halbleiterchip |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9293640B2 (de) |
| CN (1) | CN104508840B (de) |
| DE (2) | DE102012107001A1 (de) |
| WO (1) | WO2014019752A1 (de) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102012217644A1 (de) | 2012-09-27 | 2014-03-27 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement |
| DE102014106505A1 (de) * | 2014-05-08 | 2015-11-12 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung einer Halbleiterschichtenfolge |
| DE102014115253A1 (de) * | 2014-10-20 | 2016-04-21 | Osram Opto Semiconductors Gmbh | Verfahren zur Strukturierung einer Schichtenfolge und Halbleiterlaser-Vorrichtung |
| DE102014116999B4 (de) | 2014-11-20 | 2025-09-18 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips |
| US12146237B2 (en) * | 2018-10-31 | 2024-11-19 | The Regents Of The University Of California | Method of obtaining a smooth surface with epitaxial lateral overgrowth |
| WO2022181686A1 (ja) * | 2021-02-26 | 2022-09-01 | 京セラ株式会社 | 半導体基板並びにその製造方法および製造装置、テンプレート基板 |
| EP4315434A4 (de) * | 2021-04-02 | 2025-02-12 | Applied Materials, Inc. | Keimbildungsschichten zum wachstum von gallium- und stickstoffhaltigen regionen |
| US20230115980A1 (en) * | 2021-10-11 | 2023-04-13 | Applied Materials, Inc. | Masking layers in led structures |
| US20230124414A1 (en) * | 2021-10-14 | 2023-04-20 | Applied Materials, Inc. | SUBSTRATE PROCESSING FOR GaN GROWTH |
| US12557436B2 (en) * | 2021-10-14 | 2026-02-17 | Applied Materials, Inc. | Substrate processing for GaN growth |
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| EP1501117A1 (de) * | 2002-04-30 | 2005-01-26 | Sumitomo Electric Industries, Ltd. | Substrat zum züchten von galliumnitrid, verfahren zur herstellung des substrats zum züchten von galliumnitrid und verfahren zur herstellung eines galliumnitridsubstrats |
| EP1806790A2 (de) * | 2006-01-06 | 2007-07-11 | Sony Corporation | Leuchtdiode mit einer Silber-basierten Elektrode und Verfahren zu deren Herstellung |
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Also Published As
| Publication number | Publication date |
|---|---|
| US20150187985A1 (en) | 2015-07-02 |
| US9293640B2 (en) | 2016-03-22 |
| DE112013003800A5 (de) | 2015-04-23 |
| CN104508840A (zh) | 2015-04-08 |
| DE102012107001A1 (de) | 2014-02-06 |
| CN104508840B (zh) | 2017-06-30 |
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