WO2022090446A1 - Verfahren zum herstellen eines halbleiterkörpers und halbleiteranordnung - Google Patents
Verfahren zum herstellen eines halbleiterkörpers und halbleiteranordnung Download PDFInfo
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- WO2022090446A1 WO2022090446A1 PCT/EP2021/080087 EP2021080087W WO2022090446A1 WO 2022090446 A1 WO2022090446 A1 WO 2022090446A1 EP 2021080087 W EP2021080087 W EP 2021080087W WO 2022090446 A1 WO2022090446 A1 WO 2022090446A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
Definitions
- the present invention relates to a method for producing a semiconductor body, in particular an optoelectronic component.
- the invention also relates to a semiconductor arrangement, in particular an optoelectronic component.
- InGaN quantum wells which emit at wavelengths of more than 600 nm, causes difficulties, for example due to the increased indium content (more than 30%). The reason for this is the increased lattice spacing, which increases with increasing In content.
- InGaN-rich alloys have a large lattice. When depositing such a material on a GaN buffer layer, the different lattice constants generally result in a constant mismatch to the underlying GaN layers, which causes a higher defect density and/or phase separation with different In concentrations.
- the inventors propose a method for producing a semiconductor body which, in a first step, provides for the provision of an auxiliary carrier.
- a layer sequence is then deposited on the carrier, comprising a first layer with a doped semiconductor material, in particular a II-V semiconductor material, and a second layer with an undoped semiconductor material on the first layer.
- the first layer is porosified electrochemically, the degree of porosity being at least 20% by volume.
- the inventors now also propose an optional formation of mesa structures in the first porous first layer and in the second layer.
- a functional layer sequence is then produced on the second layer.
- the functional layer sequence has at least one planar third layer which is applied to the second layer provided with mesa structures, the at least one planar third layer having a different specific lattice constant than the second layer.
- a degree of porosity can also be between 50% by volume and 90% by volume.
- porosification By means of porosification, intermediate or inserted cavities. These cavities make it possible to compensate for tension without getting in an increased number of defects occur in a layer applied to this porous layer. In other words, the porosification can compensate for stresses due to different lattice constants in such a way that no lattice effects occur. This effect is further intensified by means of an optional additional mesa structure. In some material systems, mesa structuring with porosification of the first layer is particularly suitable for compensating for larger differences in the lattice constants.
- a lattice constant is understood to mean the length of a unit cell in a defined material system.
- the material system is uniform and contains no defects or lattice errors. So it's unstressed.
- the lattice constant is a characteristic variable for each material system and is also referred to as the specific lattice constant in relation to the unstressed material system.
- Different material systems can therefore have different specific lattice constants, as shown in the link above. Therefore, if material systems with different lattice constants are brought together, a strain occurs in a border area of these systems, i. H . the lattice constants change. This change decreases with increasing distance from the boundary area.
- the differences in the lattice constants are too large, there may be gaps or defects. This effect can be exploited in a targeted manner with the proposed method and also the embodiments according to the invention.
- a functional semiconductor layer sequence or a functional semiconductor body designates a layer sequence which is structured in such a way that it can assume an electrical function as a finished component.
- a functional semiconductor layer sequence can be isolated, with each individual element then having the desired functionality having .
- An example of a functional semiconductor layer sequence would be a layer sequence which, for example, has a region suitable for light emission.
- Another example would be an npn junction, which has a transistor function.
- the layer sequence can also combine several functions with one another.
- An auxiliary carrier is a carrier made of an inert material, which serves as a basis for later methods, in particular an epitaxial deposition of semiconductor materials.
- a material for an auxiliary carrier is, for example, sapphire (Al2O3), but also silicon nitride or another material. It may be desirable for the material to be inert to various etching processes used in the creation of semiconductor devices.
- the auxiliary carrier remains on the component and becomes part of it; in this case, the auxiliary carrier is also simply referred to as the carrier substrate. In other cases, a component produced on the auxiliary carrier is detached (as explained further below).
- a semiconductor material is generally understood to be an undoped compound semiconductor material, unless this is explicitly mentioned otherwise.
- the term “undoped” means in this case that a dedicated, conscious and intentional doping with another element or material is not made. Defects or impurities, which are always present in practice, do not fall under doping within the meaning of this application
- Compound semiconductor material is a combination of two , 3 or more elements that are created in a crystal structure so that a band structure is formed and that the resulting element has electrical semiconductor properties .
- a typical compound semiconductor is a so-called II IV compound semiconductor , which consists of one or more elements of the fifth and one or more elements of the third main group. Examples of compound semiconductor material are GaAs, AlGaAs, GaN, AlGaN, InGaN, GaP, InGaP, AlGaP, AlInGaN, AlInGaP, and others mentioned here.
- a doped semiconductor is a semiconductor material into which a dopant has been introduced.
- the dopant can be Si, Te, Se, Ge or Ge for an n-doping and, for example, Mg, Be or C for a p-doping in the case of an I II-V compound semiconductor.
- Other dopants are listed in this application.
- the dopant is introduced during an epitaxial deposition of the II-IV compound semiconductor material, but the doping can also take place afterwards using various methods.
- the doping concentration is several orders of magnitude lower than the concentration of the atoms in the starting or base material. For example, the concentration is in the range from 1*10 17 doping atoms/cm 3 to 5*10 21 doping atoms/cm 3 .
- Electrochemical decomposition or electrochemical etching is a process in which a semiconductor material is dissolved with the help of an electrical voltage and current. This allows a layer of semiconductor material to be dissolved or etch . However, this process does not take place evenly, but unevenly z. B. due to misalignments or material defects. This can be achieved with a suitable choice of parameters, e.g. B. exploit applied voltage and concentration of a dopant and the semiconductor material to be etched. For example, a different speed and porosity of the material to be etched can be achieved.
- electrochemical porosification is thus understood to mean an electrochemical process that selectively dissolves material out of a body, leaving a porous or spongy structure.
- a porous semiconductor body or a semiconductor layer thus produces a network framework structure similar to a Schwann or a bone, which has sufficient stability while at the same time having a low mass or material volume.
- a layer can be subjected to a selective porosification process in which a structured mask is applied before the process. This reduces or prevents a current flow in areas of the layer due to so-called shadowing, so that no or only very little porosification takes place in areas over which a mask is arranged.
- a non-porous semiconductor body does not show any net-like or spongy structure, although it can nevertheless have various defects or lattice defects.
- effects can occur in some versions in the border area, in which a section of an area that is not porous per se shows a low level of porosification, in particular at the edges of such an area, with the so-called degree of porosity (see below) increasing with increasing distance decreases from the edges.
- the area is not porous, it is more difficult or impossible for an electrolyte to penetrate under the shaded areas during the electrochemical etching process. also prevented, so that no further etching channels can form there, or. existing channels are not widened by the electrolyte. As a result, the removal rate is significantly lower under the shaded areas, so that the material there is significantly less porous or not porous at all.
- degree of porosity describes the ratio of material volume to the total volume of the layer. A degree of porosity in the region of 30% thus means that 30% of the material has been removed compared to the original volume. With a degree of porosity of 90%, 90% of the material is dissolved out by the electrochemical deposition process and only 10% of the material remains.
- the functional layer sequence can be detached from the first layer, with the second layer optionally remaining on the functional layer sequence.
- the functional layer sequence can also be detached from the auxiliary carrier in such a way that the porous first layer remains on the functional semiconductor layer sequence and can optionally be used as a coupling-out structure for electromagnetic radiation.
- the porous first layer can also be further processed. For example, contact areas can be applied to this.
- the mesa structures are formed by first applying a patterned mask to the second layer. Then the second and the porosified first layer are etched to form depressions. In some examples, these are designed as trenches in the porous first layer.
- the mesa structures are formed after porosification of the first layer. However, depending on the material system used, it is probably also possible to form the mesa structures before the electrochemical porosification step.
- the first layer is applied in partial steps, with application being interrupted after the first partial step and a thin separating layer, in particular an undoped separating layer, being deposited.
- the epitaxial deposition of the first layer is then continued.
- the first layer is divided into an area facing the wearer and an area remote from the wearer.
- this also includes the doping level between the regions of the first layer different, or a different material system for the separating layer is possible.
- Different degrees of porosity can be achieved by producing the first layer with dopings that differ in strength in some areas and/or thin separating layers. In this way, the degree of porosity can be adapted both for the entire wafer and locally to the needs for the growth of further layers.
- the step of creating a layer sequence includes creating non-porous iced areas. This is done by applying a structured mask to the second layer of the layer sequence in order to produce areas below the structured mask that are not to be porous and then removing the structured mask after electrochemically porosifying the first layer. This means that areas of the first layer remain below “shaded" areas, i.e. they are not porous or only to a very small extent. These areas now show other mechanical and electrical properties Application of the third layer creates stresses in this In some aspects, this is exploited to form, for example, active regions that emit light with different wavelengths.
- the functional layer sequence can be designed with an active area designed to emit light of a first wavelength over a porous area and an active area for emitting light of a second wavelength over a non-porous area.
- the different wavelengths are caused, among other things, by the stresses due to different lattice constants over the porous or non-porousif ed area.
- the dimensions in the structured mask may be expedient in some aspects to choose the dimensions in the structured mask somewhat larger than the region or regions of the first layer that are not to be porous below the structured mask.
- the shading of the mask prevents or reduces current flow along and below these areas in the first layer in the electrochemical process. This leaves the material of the first layer essentially intact.
- the slightly larger dimensions of the mask also compensate for any slight undercutting that may be present.
- a mesa structure can be performed before or after the selective porosification described above. This also allows porosification to be at least partially controlled.
- a combination of structured mask and mesa structuring can thus be provided, so that after the individual method steps, a structure results in which porous areas and non-porous areas of the first layer alternate, separated by a trench.
- the depressions in particular in the form of trenches, have a width in the range from 5 nm to 500 nm, in particular in the range from 20 nm to 300 nm and more particularly less than 200 nm.
- the trenches can extend as far as the auxiliary carrier, but can also end in front of it, or if there is a separating layer in the first layer, end there.
- the mesa structures designed as trenches or depressions should not be too large. Experiments have shown that the above values are appropriate. However, the distance between mesa structures should not be too large either, so that stresses caused by the trenches or depressions are compensated for can become .
- a ratio between a width of a mesa structure and a distance between 2 mesa structures can be defined. This can be in the range from 4 to 15, in particular in the range from 8 to 12, and in particular 9.5 to 10.5.
- a further aspect relates to a deviation in the lattice constants, in particular between the second layer and the third layer, which forms part of the functional layer sequence.
- the lattice constant of the planar third layer can be increased by at most 20%, in particular in the range of approx. 0.4% to 3%, in particular in the range from 0.5% to 2.7%, from a lattice constant of the second layer.
- Materials based on GaN or GaAs can be used as the material for the various layers, which in turn can be doped with Si, C, Ge or also Mg.
- the third layer of the functional layer sequence can in particular comprise an indium-containing layer.
- the layer can also be in the form of a superlattice or itself can comprise a layer sequence.
- the indium content can be in the range from 0.0001% to 25%, for example in the range from 2% to 20%.
- the layer can also be in the form of a superlattice or itself can comprise a layer sequence.
- Subsequent layers of the second semiconductor layer sequence in particular those that contribute to an optical functionality, can have an indium content of at least 20%, in particular at least 40% and in particular in the range from 30% to 60%. In some designs, the indium content can also be up to 100%.
- Alternative base materials are listed above. Doping can take place during the epitaxial deposition. This also allows the doping concentration to be adjusted continuously.
- the second layer has undoped GaN and the planar third layer has an indium-containing material, for example InGaN.
- the Indium Portion The first layer is formed from doped GaN, with the doping concentration being in the range from 1*10 17 atoms/cm 3 to 5*10 21 atoms/cm 3 .
- coalescence planes should be oriented perpendicular to the a-axis [1120].
- the epitaxial creation of a functional layer sequence includes creation of a multiple quantum well structure. This is designed to emit light of one wavelength.
- the multiple quantum well structure can extend over at least one mesa structure.
- the multiple quantum well structure extends over both porous and non-porous areas of the first layer.
- the Ga/In ratio is shifted in the direction of indium and thus to longer wavelengths as the lattice constant increases. This allows light of different wavelengths to be generated.
- the inventors have recognized that, contrary to an obvious assumption, when the third layer is deposited on the mesa-structured second layer, material of the third layer does not get into the trenches, or only very little. In particular, the material of the third layer does not fill up these trenches, but rather forms a bridge across the trenches, leaving a cavity.
- the mesa structure in combination with the porous first layer, compensates for the stresses due to the changed lattice constant.
- this comprises an auxiliary carrier and a layer sequence with a first layer having a doped semiconductor material and a second layer applied thereon.
- This has an undoped semiconductor material, with the first layer comprising at least one porous region whose degree of porosity is at least 20 by volume 5
- a mesa structure made up of a number of depressions is introduced into the first and second layers.
- a functional layer sequence with at least one planar third layer is applied to the second layer provided with the mesa structure, the at least one planar third layer having a different lattice constant than the second layer.
- the introduced mesa structure in combination with the porous first layer reduces or eliminates tension in the third flat layer. even prevented.
- material systems with a different lattice constant can also be used, with the third layer and the functional layer sequence being able to relax as a result of the porosification.
- the width of the pit or even a trench is less than 200 nm, the distance between two Pits is less than 2000 nm. Other dimensions for trenches and the distances between them are given above. In some examples, a width of the indentation is approx. a 1/5 to 1/20 of the distance between two adjacent wells.
- the first layer is not porous throughout. Rather, at least one non-porosified area can be provided, which is at least partially surrounded by a porous area.
- the at least one non-porousified region can be designed as a holding structure for a functional semiconductor body later to be seated thereon.
- the non-porousified area could be used to locally introduce a strain in further layers and thus to realize a change in a band gap or a change in electrical properties.
- the at least one non-porosified area is separated from the porous area by a trench forming the mesa structure.
- a further aspect relates to an embodiment of the functional layer sequence.
- the functional layer sequence is formed with a multiple quantum well structure, which is applied to the third layer.
- a first region of the multiple quantum well structure overlying a porous region of the first layer is configured to emit light of a first wavelength and a second region of the multiple quantum well structure overlying a nonporous region of the first layer is configured to emit light of a second, shorter wavelength .
- the first layer can have a first portion with a first porosity level and a comprise a second partial region separated by a separating layer and having a second degree of porosity.
- various applications can be implemented which, for example, require locally separate different lattice constants.
- a defect density in the third layer can also be further reduced by an additional separating layer.
- the first layer includes n-doping while the second layer is undoped, with the first and second layers having the same base material.
- the second layer can comprise an undoped GaN layer and the third layer can be formed with InGaN having an indium content in the range from 0.0001% to 25%, in particular less than 15%.
- the third layer can also be in the form of a superlattice or itself can comprise a layer sequence.
- Subsequent layers of the second semiconductor layer sequence in particular those that contribute to an optical functionality, can have an indium content of at least 20%, in particular at least 40% and in particular in the range from 30% to 60%. In some versions, an indium content of 100% can also be used, especially if the indium layer is very thin.
- stress causes a local change in the lattice constant, so that the stoichiometric composition of the grown material changes during a growth process.
- the indium content in the growing material system can be varied locally, which changes the band gap.
- areas can be created that generate light of different wavelengths in one operation.
- FIGS. 1 and 2 show several steps in a method for producing a functional semiconductor body, which implements some aspects of the proposed principle
- FIGS. 3A and 3B some aspects of a further exemplary embodiment according to the proposed principle
- FIGS. 4 and 5 show a further exemplary embodiment with a number of method steps for producing a functional semiconductor body, which implement some aspects of the proposed principle
- FIG. 6 shows an embodiment of a possible mesa structure for a material system with a litter structure
- FIG. 7 shows a further embodiment of a possible mesa structure for a material system with a litter structure
- FIG. 8 shows a further exemplary embodiment with a number of method steps for producing a functional semiconductor body which implement a number of aspects of the proposed principle
- FIG. 9 shows two plan views of emission areas of optoelectronic components that can be produced using the method according to FIG.
- the inventors have recognized that the partial electrochemical decomposition (referred to here as porosification) of a precisely defined layer containing GaN leads to a strong reduction in the holding force of a GaN epitaxial stack to the epitaxial substrate (sapphire or also Si, GaN) or to others growing layers causes .
- Very uniform pores in the range from 20 nm to 100 nm) - homogeneously distributed - are etched into the specific GaN layer.
- the selectivity of the "porosification" can be achieved by high n-doping (Si) of the GaN layer.
- Si n-doping
- D. H only sufficiently highly doped layers are made porous. In addition to a reduced adhesive force, improved relaxation is also achieved.
- the indium proportion is incorporated with a different stoichiometric composition depending on the existing strain and thus the different lattice constants.
- the band gap is changed by the now local change in the indium proportion in the material system.
- this effect can also be achieved with Al or another material, which is incorporated in a stoichiometrically modified manner depending on the lattice constant and thus causes a change in the band gap.
- the layer to be porous can be buried under further GaN or other material layers.
- a laterally selective etching attack can be carried out by partially passivating the surface during the “porosification”.
- the buried areas in the first layer to be porousized below the masked surface areas are not porous laterally in the plane, or only slightly porous, or etched, like that that these have different chemical and mechanical properties in subsequent process steps.
- an additional second layer can be inserted between the first layer to be porosified and the further layers forming the semiconductor component, so that this additional layer can serve as a mechanical fracture point in a further process step. In this way, depending on the application and design, different areas can have different degrees of porosity laterally or vertically.
- FIGS. 1 and 2 show an exemplary first embodiment of a method according to the proposed principle for producing a semiconductor body in which the lattice stresses are reduced and which can be removed particularly easily from a carrier by means of a porous separating layer.
- a carrier substrate 1 is provided as an auxiliary carrier in a first step S1.
- this is a sapphire carrier substrate, but a carrier substrate with a different material system can also be used.
- carrier substrates based on silicon, silicon nitrite, or, as shown, sapphire are possible.
- the auxiliary carrier is also selected according to the material system later used, among other things.
- a first layer 2 of the layer sequence 4 is applied to the auxiliary carrier 1 .
- This first layer 2 is also provided with a dopant during the epitaxial deposition on the substrate of the auxiliary carrier 1 .
- the thickness of the layer is in the range between 500 nm and 3 ⁇ m, for example 1.5 ⁇ m.
- the material can be GaN or AlInGaP or AlGaAs can be used as a further material system, the latter for the production of red LEDs.
- GaN is used as the material for the first layer, which with silicon Si as a dopant on the Auxiliary carrier 1 is deposited epitaxially.
- the doping concentration of the silicon atoms is in the range of 10*10 19 atoms/cm 3 .
- one or more thin buffer layers in the range from less than 10 nm to 100 nm can also be applied to the material of the auxiliary carrier 1. These are not shown separately in step S2, but can be used for further planarization of the auxiliary carrier 1.
- the additional buffer layers also serve as an etch stop or lattice matching structure or as a current spreading layer for the subsequent electrochemical dissolution process.
- an undoped GaN layer 3 is applied to the doped, epitaxially deposited GaN layer 2 .
- AlInGaP can also be used if layer 2 consists of doped AlGaAs or AlInGaP.
- the thickness of the layer 3 is, for example, 100 nm (range from 20 nm to 150 nm) and is designed to be significantly thinner than the doped GaN layer 2 in terms of its dimensions. As a result, layer 3 also shows different mechanical, chemical and electrical properties compared to this layer.
- the undoped GaN layer 3 and the doped GaN layer 2 together form the layer sequence 4 .
- step S4 the wafer produced in this way is now subjected to an electrochemical detachment process.
- This is also referred to as the porosification process or porosification process.
- a voltage is applied to the formed wafer structure and the layer sequence 4 so that a current flows through the undoped GaN layer 3 and the doped GaN layer 2 .
- the current flow causes a partial chemical decomposition of the doped GaN layer.
- This process is called porosification.
- pores with a size are uniform in the doped GaN layer 2 by the electrochemical process etched in the range from a few 10 nm to 100 nm. It has been found that the distribution of the pores is essentially homogeneous and is mainly perpendicular to the sapphire surface.
- the etching rate as well as the pore size and the material removal associated therewith is dependent on the applied voltage, the current flow during the electrochemical process, the electrolyte used and a concentration of the doping atoms in the GaN layer 2 .
- the undoped GaN layer 3 is basically also attacked by the electrochemical process. Material is removed in both layers, since these are not electrically insulating. However, the conductivity of the undoped GaN layer is significantly lower, so that doping with silicon in layer 2 achieves selectivity during the porosification process.
- the doped GaN layer 2 is attacked, etched and thus material is dissolved to a significantly greater extent during the electrochemical process than is the case in the undoped GaN layer 3 . Since the current is introduced over the entire surface of the wafer during the porosification in the present example, the electrochemical process in the layer stack 4 follows over the entire surface. The layer 2a made porous in this way in step S4 is thus buried under the non-doped GaN layer 3.
- the amount of material removed by the porosification can be adjusted by the duration and the parameters described above.
- the inventors propose a degree of porosity of at least 20% by volume. It was found that up to a degree of porosity of approximately 90% by volume to 95% by volume, the mechanical stability of the remaining material is still sufficient to enable the further production steps. Nevertheless, due to the high level of material removal an adhesive force between the carrier 1 and the porosif iced GaN layer 2a or 2a. greatly reduced between this and the undoped GaN layer 3 . In this respect, therefore, a degree of porosity between 40% by volume and 90% by volume is considered expedient.
- the wafer produced in this way can be further processed in order to prepare it for the application of further layers which have a different lattice constant.
- a structured mask is applied to the undoped GaN layer 3 in step S5.
- this is designed as a multiplicity of strips in plan view.
- a ratio of the strip width to the distance between two adjacent strips is approx. 10 .
- the distance between 2 strips is in the range from 1 pm to 2 pm.
- Such a distance and a width of approx. 100 nm to 200 nm can still be produced lithographically with current technologies.
- a selective etching process then takes place in step S6, in which etching takes place through the undoped GaN layer and the porous layer up to just before the auxiliary carrier.
- step S6 in which etching takes place through the undoped GaN layer and the porous layer up to just before the auxiliary carrier.
- a depth to width ratio of a trench is in the range of 5 to 14, and in particular in the range of 10.
- the mesa-structured, porous layer 2a is tensed, so that a further layer can be grown without major tensing on its part.
- a layer that has grown on the mesa-structured porousized layer can be produced without major defects and in an essentially planar manner, and this can thus serve as a base layer for a functional semiconductor body or a functional semiconductor layer sequence.
- step S7 in FIG. 2 shows such a first step of growing an n-doped indium-containing layer 10, for example an InGaN layer, whose lattice constant is greater than the lattice constant of the layer sequence 4.
- the growth process of the n-doped InGaN layer 10 results in strains in the layer sequence 4, which are compensated for by the porous regions 2a and the mesa structure in the layer sequence 4.
- the InGaN layer 10 grows essentially free of errors and defects.
- bridges of material are formed during the growth process that span the trenches 20 .
- the InGaN material of the layer 10 grows only slightly into the trenches 20 essentially in the surface area of the undoped GaN layer 3, but does not fill up these trenches.
- step S7 This creates cavities, as shown in step S7, which can absorb the crystal strains in the layer sequence 4.
- step S7 By varying the degree of porosity over the layer 2 c across or more lithographic or. A large degree of relaxation in the layer sequence 4 can be achieved by epitaxial measures, so that the defect density in the layer 10 remains low.
- the layer 10 that has been grown on has an essentially planar and defect-free surface, so that further layers of a functional semiconductor or a functional layer sequence 6 can be deposited with high quality.
- Step S8 shows the production of such a layer sequence 6, in which the layer is n-doped during the growth process. Further layers 11 and 12 are deposited on this n-doped layer 10 .
- the layer 11 forms a multiple quantum well for emitting light of a defined wavelength.
- the layer 12 is formed by a p-doped GaN or formed a p-doped AlInGaP layer.
- the use of a GaN layer is particularly easy to perform.
- layer combinations z. B. form p-doped InGaN / AlGaN / GaN layers.
- the layer sequence 6 thus forms a component which, when current flows through it during operation, generates light of a defined wavelength.
- the wavelength is given by the band structure of the multiple quantum well, which in turn is dependent on possible strains in the underlying layer 10 . Due to the low defect density and the essentially planar surface, the defect density of the multiple quantum well is also low in this example, so that a high radiating recombination rate can be achieved.
- step S9 the component produced in this way is the components are applied from the auxiliary carrier 1 to a final carrier substrate 5 .
- the end carrier substrate 5 is covered with a metallization layer 70 which forms the p-contact for making contact with the functional layer sequence 6 .
- the p-doped layer 12 is attached to the metallization layer 70 by means of a solder.
- the auxiliary carrier 1 is then removed by means of a laser lift-off or another method. Due to the porosification of the areas 2a, the adhesive force between the auxiliary carrier 1 and the porous areas 2a is greatly reduced. As a result, the energy input that is necessary for a laser lift-off process is also lower, so that only minor damage develops in the surface.
- step S10 structures of the layer sequence 4 that are left over after a laser lift-off can be removed, so that the planar layer 10 is exposed.
- step S10 structures of the layer sequence 4 that are left over after a laser lift-off can be removed, so that the planar layer 10 is exposed.
- step S10 structures of the layer sequence 4 that are left over after a laser lift-off can be removed, so that the planar layer 10 is exposed.
- step S10 structures of the layer sequence 4 that are left over after a laser lift-off can be removed, so that the planar layer 10 is exposed.
- On the- Another metallized contact area 7 is applied on top of this, so that the resulting component is now in the form of a vertical light-emitting diode. This structure is shown as a result for a single diode in step S10.
- the mesa-structured and porous layer 2a can also remain on the component and serve both for electrical contacting and as a decoupling structure.
- step S10' of FIG. metallic contacts 7a are deposited on the porous areas 2a. Since the porous areas and the underlying layer 3 are conductive, current also flows through the various layers 2a, 3, 10 and 12 in this example, so that charge carriers recombine in the multiple quantum well 11 .
- the porous areas 2a are used as a decoupling structure, since they form a refractive index transition between the layer 3 and the air medium.
- an additional roughening of the layer 10 or further outcoupling structures and measures could be dispensed with.
- FIG. 3A shows such an example, in which differently doped areas are proposed for producing different degrees of porosity.
- FIG. 3A shows the result of the first steps of a manufacturing process of a semiconductor component.
- a first layer 2 was deposited on an auxiliary carrier 1, which layer comprises an area 2′, adjacent to the auxiliary carrier 1, and an area 2′′.
- the areas 2' and 2'' are separated from one another by a thin separating layer 3b.
- Separating layer 3b serves on the one hand as a predetermined breaking point and includes AlGaInN or silicon nitride, SiN, the latter for example as a monolayer.
- the layer 3b separates different doping concentrations from one another.
- the degree of doping of the areas 2' and 2'' differs, so that different degrees of porosity are also achieved during a later electrochemical process.
- the doping in region 2' is selected to be significantly higher than in region 2''. As a result, significantly more material is removed and decomposed during the electrochemical process in area 2' than in area 2'', which is closer to the undoped GaN layer 3.
- the structure produced in this way is particularly suitable, for example, as a decoupling structure.
- the auxiliary carrier is separated from the material 2' and the separating layer 3b.
- the predetermined breaking point 3b can also be removed in a further step, so that only the porous area 2'' of the first layer remains on the component.
- the degree of porosity of this porosified layer is selected in such a way that layer 2'' serves as a decoupling structure, since its pore structure forms a suitable jump in refractive index. Subsequent roughening with KOH or other measures is therefore unnecessary.
- FIG. 3B shows the structure of FIG. 3A after a mesa structure, as was carried out, for example, in the previous example of FIG. 1 in steps S5 and S6.
- the etching process has penetrated the two partial areas 2′ and 2′′ as well as through the thin separating layer 3b and extends to just before the auxiliary carrier 1.
- FIG. 4 and 5 show various steps of a further embodiment of the proposed principle, in which additional measures and structuring of the layer sequence 4 are carried out before a mesa structure is formed. This allows further applications to be implemented.
- Steps S1 and S2 are the same as in the exemplary embodiment in FIGS.
- a doped GaN layer 2 is again grown epitaxially.
- a thin sol breaking or separating layer 3a is now deposited. This can be formed, for example, from AlGaInN or also from intrinsic silicon nitrite, for example a monolayer SiN, and in the present exemplary embodiment also extends over the entire wafer.
- the undoped GaN layer 3 is in turn applied epitaxially over the thin predetermined breaking layer 3a.
- the resulting layer sequence 4 on the carrier substrate 1 is shown in FIG. 4 in step S3.
- a structured mask 8 is then applied to 2 locations on the undoped GaN layer 3, for example.
- the mask 8 is chemically inert with respect to the following electrochemical porosification step and is listed, for example, as a hard mask.
- the electrochemical porosification is carried out. In this case, however, the structure of the mask 8 acts as a shadow, so that areas below the mask 8 in the first layer 2a are not made porous or etched, but remain as non-porousified areas 2b. In the example of steps S3 and S4 in FIG. 4, these are 2 areas that are a few ⁇ m wide and essentially form squares when viewed from above.
- the shape can also be designed differently, for example as polygons or also as circles or rectangles.
- the background for such a selective porosification is the fact that a current flow is largely prevented due to the insulating behavior of the mask 8 through the layer 3 , the layer 3a and the first layer 2 .
- the current always seeks the path of least resistance (and thus usually the shortest path if the specific resistance is constant) and would therefore not flow below the area covered or covered by the mask 8 during the electrochemical process. shaded areas flow .
- porosification takes place because of the current flow, primarily in the non-shaded areas of the first layer, so that porosified areas 2c form there.
- penetration of an electrolyte during the electrochemical etching process under the shaded areas is made more difficult or impossible. also prevented, so that no further etching channels can form there, or. existing channels are not widened by the electrolyte.
- the dimensions of the mask 8 are adapted to the dimensions of the later non-porous area 2b. Although the surface resistance below the mask is greater and the current flow there is significantly smaller, slight undercutting occurs within a small frame in the edge area. Due to the undercutting during the electrochemical porosification, it is expedient to design the dimensions of the lacquer mask 8 somewhat larger than the later non-porosification area should be. This compensates for slight undercutting below the mask and thus in the shaded area. For nitrides, this undercutting can range from 200 nm to approx. 800 nm, for materials based on GaAs or GaP the undercut can also be larger than 1000 nm. The dimension and lateral extent must be selected accordingly. In the subsequent process step S5, the mask 8 is removed again and, instead, the mask 8a is applied to the surface of the layer 3 to produce the mesa structure.
- the mask is designed in such a way that parts of the non-porous areas 2b are covered by the mask structure. Recesses are provided in the mask only at the edges between the porous areas and the non-porous areas of layer 2 .
- a mask structure is also arranged over the remaining modified areas 2c, which has recesses at periodic intervals. This creates a mask structure 8a, with the aid of which the mesa structure described in the previous examples can be etched.
- Process step S 6 in FIG. 5 shows the result after such a selective etching process, in which trenches 20 are etched into the layer sequence 4 at regular intervals.
- trenches 20 are etched into the layer sequence 4 at regular intervals.
- two trenches 20 are provided adjacent to the non-porousified areas, so that in each case one trench 20 separates a porous area 2c from a non-porousified area 2b.
- the AlInGaN layer 10 is then applied to the structure produced in this way. As in the previous examples, depending on the application and the desired design of the component, this is p- or n- or also undoped.
- the additional mesa structures reduce stress in the layer 10 so that it grows as planarly and free of defects as possible.
- a multiple quantum well 11 is deposited on the grown layer 10, followed by a further doped layer 12.
- the layers 10, 11 and 12 form the layer sequence 6 of the functional semiconductor layer sequence.
- a structured mask 8 b is then arranged on the deposited layer 12 . In this case, mask components cover the non-porosified areas 2b and the neighboring trenches 20 and part of the subsequent porosified areas 2c. Parts of the surface of the layer 12 are still exposed between the individual masks 8b.
- step S7 of FIG. 5 the free areas of the layer 12 and the underlying areas of the multiple quantum well structure 11 of the layer 10 and the layer sequence 4 are etched.
- the semiconductor layer sequence is subdivided into individual functional components.
- the etched trench 20' extends from the surface of the semiconductor layer sequence 6 to approximately the carrier 1.
- contact regions 7A and 7 are also provided in the respective components.
- the contact region 7a is electrically insulated from the layer 12 and from the multiple quantum well 11 and makes contact with the doped buried layer 10 .
- the contact area 7 directly electrically connects the layer 12 .
- the porous regions 2c can be reached and removed with a wet-chemical and selective etching process.
- the columnar structures 20b made of non-porous material, shown in process step S8 remain and thus form a holding structure for the components located thereon.
- the layer 3a and the layer 3 are slightly roughened by the selective process, so that they can serve as a decoupling structure for the light generated in the multiple quantum well.
- These pillars can take different forms depending on the design.
- the support structure may form a truncated cone, truncated pyramid, or trapezoid, with the smaller base of this body being connected to the building element.
- the diameter decreases towards the component.
- This decrease in the diameter, or more generally a change in the diameter is achieved by a different doping during the epitaxial deposition of the first layer reached .
- the doping also controls the rate of porosification, among other things, so that undercutting under the shaded areas is also influenced.
- a stamp pad 30 is applied selectively to the functional semiconductor body 60 and then by means of a mechanical method or. Laser lift-off process separated the functional semiconductor body from the column and support structure 20b. Semiconductor body 60 now adheres to stamp pad 30 and can be transferred for further process management or processing.
- the still existing, caused by the structuring depressions in the layer 3a or. 3 can serve as a further decoupling structure or can also be filled with a suitable material.
- the height of the layer to be porosified later, and thus also the height of the trenches, should not exceed a few micrometers, so that adequate stress compensation is still ensured.
- a trench would not be able to be etched uniformly if the ratio between depth and trench width was too large, so that instead of an essentially rectangular progression as shown in the cross-sectional illustration, a depression with a triangular cross-section is formed.
- a height of the layer 2 to be made porous according to the previous examples should therefore be approximately 1 ⁇ m to 2 ⁇ m, possibly only 500 nm.
- the width of the trenches can be chosen to be approximately ten times smaller than the width of the respective section of layer 2 to be porous. This results in the square cross-sectional area shown in FIG. 1 in step S6.
- the trenches should be as narrow as possible, but large enough to allow relaxation, d. H . to ensure stress compensation of the stressed layer applied to the layer sequence 4 .
- etching and masking steps are achieved by different lithographic processes.
- a wet-chemical, but also a dry-chemical etching process for layer 2a can be implemented for the formation of the mesa structure.
- FIGS. 6 and 7 show different geometries for such a mesa structure in plan view.
- the trenches of the mesa structure are also etched parallel to the coalescence surfaces, and the structures shown in FIG. 6 are produced, for example.
- FIG. 7 shows another embodiment in which mesa structures are designed as periodic hexagons.
- the trenches and the coalescing areas 21 are designed in such a way that they form polygons and, in particular, a hexagonal structure.
- the edge length of this hexagonal structure is, as shown, less than 2 pm, the width of a trench is essentially a tenth less, i. H . in the range of 200 nm or less.
- FIG. 8 shows a further exemplary embodiment and an application in which porous areas and non-porous areas are used to produce a light-emitting semiconductor body, which emits light of different wavelengths.
- an auxiliary carrier 1 is provided, to which a doped GaN layer 2 is applied.
- An undoped layer of the same material system is in turn deposited on this, resulting in the layer sequence 4 shown in process step S1.
- a mask structure 8 is first deposited on the surface of the undoped GaN layer 3 .
- the structure obtained in this way is then subjected to an electrochemical detachment and decomposition process, so that primarily non-shaded areas of the doped layer 2 are made porous.
- the Mas ke 8 covers the layer 2 takes place through the reduced or.
- there is no dedicated porosification leaving these areas essentially with continuous doped GaN material. This means that no subsequent reduction in the stresses due to the porosification is to be expected in the areas 2b.
- the mask 8 is now removed and the mask 8b is applied to the layer 3 again.
- the mask structuring takes place in such a way that part of the mask 8b is arranged over the non-porous areas 2b.
- mask sections are deposited over the porous areas 2c. In this case, it is provided that a small part remains open between the individual mask sections, so that the layer 3 underneath is exposed. The position of this free part is chosen so that it is essentially along the interface between the porous areas 2c or . the non-porosified areas 2b takes place.
- a selective etching process can then in turn be carried out, which produces trenches at the interfaces between the regions 2b and 2c down to the auxiliary carrier 1 .
- a structuring is thus carried out, which separates the porous areas 2c from the non-porous areas 2b by a trench.
- the mesa structure contained in this way is overgrown with an indium-containing layer, in the embodiment with a GaN layer 10, see step S4 in FIG.
- the InGaN layer forms bridges between the individual trenches 20, so that the trenches essentially remain as cavities and are not overgrown.
- the InGaN material can at least partially get into the upper region of the trenches between the undoped layer 3 .
- the deposited material of the layer 10 is strained over these areas, which is noticeable in a change and straining of the lattice structure. Whether this strain now leads to additional lattice defects depends on the design of the dimensioning and the difference in the two lattice constants between the doped InGaN layer 10 and the undoped layer 3 .
- layer 12 is now deposited on layer 10 with another multiple quantum well contained therein.
- the layer 12 comprises AlInGaN, which is doped or also provided with a doping gradient, depending on the configuration. Due to the strains introduced by the non-porous areas 2b, the band structure and thus also the band gap of the multiple quantum well 11 changes. This is caused by the stresses propagating through layer 10 and into layer 12 and reach into the multiple quantum well 11 . To do this, it is necessary to design the InGaN layer 10 as thinly as possible, but planar, in order to conduct the strain through the layer 10 into the layer 11 . As a result, the tension leads to the emission of light of different wavelengths. It was achieved that a wide range of possible wavelengths can be reached by a suitable choice of the tension and the material system.
- FIG. 9 An electronic component produced in this way is shown in various alternative configurations in FIG. 9 in a plan view.
- the emission surfaces can be seen, with the multiple quantum well and any porosified areas of different degrees of porosity below them.
- a suitable porosification and the introduction of a mesa structure different stresses can be generated in the material arranged above.
- the different band gaps resulting from the strain due to a changed proportion of indium now causes light to be emitted with different wavelengths.
- a suitable material system for example the AlInGaN mentioned above, light emission in the blue, green and red range can be achieved by the strain.
- area b shows the greatest stresses at the top left, for example a non-porous layer 2b is arranged there.
- the region r in turn is much less strained, so that the result is that the multiple quantum well emits essentially red light there.
- the two lower regions g are provided with a degree of porosity that lies between the blue and the red region b, r, so that the multiple quantum well is slightly strained here and thus emits light in the green region.
- a pixel with a blue, red and green emitter surface can also be arranged next to one another.
- Such an embodiment is shown in the right part of FIG. are designed in which differently porous areas are designed to generate light in the blue, red and green spectrum.
- a different degree of porosity provision is made, for example, for the individual masks 8 to be selectively removed, as shown in step S2 of FIG. 8 above, and then for the electrochemical deposition process to be continued.
- a shadow mask 8 can be applied to the subsequent blue and green emitter surface. The red area remains free.
- a first electrochemical detachment process is then carried out and a first porosification is produced for the red emitter surface. Then this electrochemical detachment process is stopped, the mask is removed over the green area and then the electrochemical detachment process continues. Accordingly, the red and the green area (or the layer 2, which later lies under the multiple quantum well) is further porosified. This allows a different degree of porosity to be achieved in the respective areas.
- additional layers can be provided which produce differences in the porosification and can thus be used to form the differently colored areas.
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US20090001416A1 (en) * | 2007-06-28 | 2009-01-01 | National University Of Singapore | Growth of indium gallium nitride (InGaN) on porous gallium nitride (GaN) template by metal-organic chemical vapor deposition (MOCVD) |
WO2010112980A1 (en) * | 2009-04-02 | 2010-10-07 | Philips Lumileds Lighting Company, Llc | Iii-nitride light emitting device including porous semiconductor layer |
EP2731149B1 (de) * | 2012-11-07 | 2017-03-29 | LG Innotek Co., Ltd. | Lichtemittierende Vorrichtung |
US20170237234A1 (en) * | 2014-09-30 | 2017-08-17 | Yale University | A method for gan vertical microcavity surface emitting laser (vcsel) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2024134081A1 (fr) * | 2022-12-21 | 2024-06-27 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de porosification de mésa facilitant la reprise de contact |
FR3144413A1 (fr) * | 2022-12-21 | 2024-06-28 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de porosification de mésa facilitant la reprise de contact |
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CN116490984A (zh) | 2023-07-25 |
JP2023547246A (ja) | 2023-11-09 |
US20230411556A1 (en) | 2023-12-21 |
DE102020128680A1 (de) | 2022-05-05 |
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