WO2014015536A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2014015536A1
WO2014015536A1 PCT/CN2012/079694 CN2012079694W WO2014015536A1 WO 2014015536 A1 WO2014015536 A1 WO 2014015536A1 CN 2012079694 W CN2012079694 W CN 2012079694W WO 2014015536 A1 WO2014015536 A1 WO 2014015536A1
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Prior art keywords
contact
sacrificial layer
source
contact sacrificial
gate
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French (fr)
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尹海洲
张珂珂
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/416,698 priority Critical patent/US20150187892A1/en
Publication of WO2014015536A1 publication Critical patent/WO2014015536A1/zh
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    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
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    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0225—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate using an initial gate mask complementary to the prospective gate location, e.g. using dummy source and drain electrodes
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    • H10D30/0616—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs using processes wherein the final gate is made before the completion of the source and drain regions, e.g. gate-first processes
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    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/795—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in lateral device isolation regions, e.g. STI
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    • H10D62/113—Isolations within a component, i.e. internal isolations
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
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    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
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    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
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    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
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    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a method of fabricating a MOSFET having an increased contact area. Background technique
  • the source/drain regions of the contact region (or contact hole, CA) and the gate spacers still have a large spacing, electron/hole carriers from The distance from the source region to the drain region reaching the drain region is still large, so the parasitic resistance is still not effectively reduced, and the device performance improvement is limited.
  • the object of the present invention is to replace the conventional replacement gate process by a new manufacturing method to contact the sacrificial layer process, thereby greatly reducing the spacing between the contact region and the gate, thereby effectively reducing device parasitic resistance.
  • the above object of the present invention is to provide a semiconductor device manufacturing method including: forming a contact sacrificial layer on a substrate, etching a contact sacrificial layer to form a contact sacrificial pattern, wherein the contact sacrificial pattern covers a source region and a drain a region and having a gate trench exposing the substrate; forming a gate spacer and a gate stack structure in the gate trench; partially or completely etching to remove a contact sacrificial pattern covering the source region and the drain region, forming source-drain contact a trench; a source-drain contact is formed in the source-drain contact trench.
  • contacting the sacrificial layer includes a first contact sacrificial layer and a second contact sacrificial layer.
  • the first contact sacrificial layer includes strains S i, S iGe, S i: C, polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, silicon nitride, and combinations thereof
  • the second contact The sacrificial layer includes single crystal silicon, polycrystalline silicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, silicon nitride, and combinations thereof.
  • the step of forming the source/drain contact trench comprises: partially etching the second contact sacrificial layer; or completely etching the second contact sacrificial layer and partially etching the first contact sacrificial layer; or completely etching Removing the second contact sacrificial layer and the first contact sacrificial layer; or completely etching away the second contact sacrificial layer and the first contact sacrificial layer and partially etching the substrate.
  • the contact sacrificial layer is formed by epitaxial growth and the doping has a first conductivity type.
  • the etch contact sacrificial layer and the substrate form a shallow trench, and the shallow trench is filled with an insulating material to form shallow trench isolation.
  • the shallow trench isolation is etched to tilt toward the isolation region in the width direction of the active region.
  • lightly doped source and drain regions are formed in the substrate on both sides of the gate trench.
  • forming the gate stack structure includes depositing a gate insulating layer of a high-k material, a work function adjusting layer of the metal nitride, and a metal resistance adjusting layer in the gate trench.
  • the step of forming a source-drain contact further comprises: forming a metal silicide in the source-drain contact trench; sequentially depositing a liner layer and a fill layer on the metal silicide; planarizing the fill layer and the liner layer until exposed Gate stack structure.
  • the spacing between the gate spacer and the contact region is effectively reduced by the double-layer contact sacrificial layer process, and the contact region area is increased, thereby effectively reducing the parasitic resistance of the device. . DRAWINGS
  • FIG. 1 to 9 are cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention.
  • FIG. 10 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • a contact sacrificial pattern is formed on the substrate, covering the source and drain regions and exposing the gate region.
  • a first contact sacrificial layer 2 and a second contact sacrificial layer 3 are sequentially formed on a substrate 1.
  • the substrate 1 is provided, and the material thereof may be (body) S i (for example, single crystal Si wafer), S0I, single crystal Ge, GeOI (Ge on insulator), or other compound semiconductors such as GaAs, S iGe, GeSn. , InP, InSb, GaN, etc.
  • the substrate 1 is selected from a body S i or SOI for compatibility with a CMOS process.
  • the first contact sacrificial layer 2 is epitaxially grown on the substrate 1 by conventional methods such as LPCVD, PECVD, HDPCVD, M0CVD, MBE, ALD, evaporation, sputtering, and the like, and the process parameters are appropriately controlled.
  • the first contact sacrificial layer 2 is used for the actual source and drain regions of the device later (as part of the boost source drain), and the material thereof may be the strains S i , S iGe , S i: C and combinations thereof, and the thickness thereof is, for example, 10 ⁇ 100nm.
  • the first contact sacrificial layer 2 has a first conductivity type, such as n or p, by epitaxial growth while in-situ doping or an additional ion implantation process after epitaxial growth.
  • the first contact sacrificial layer 2 may also be polysilicon, amorphous silicon, microcrystalline silicon, amorphous carbon, silicon oxide, silicon nitride, etc., at this time, the first contact sacrificial layer 2 will be shown later in FIG. Complete removal during the formation of the source and drain contact trenches.
  • a second contact sacrificial layer 3 is epitaxially formed on the first contact sacrificial layer 2 by a similar epitaxial process for defining a region where a source/drain contact is to be formed later, and a dummy gate in the back gate process
  • the pole acts similarly and can therefore also be referred to as a false source/drain contact zone.
  • the material of the second contact sacrificial layer 3 may be the same as the substrate 1, for example, S i (which may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, or partially used as a part of the source/drain region), and the material may be different.
  • the second contact sacrificial layer 3 completely removes the etching in a subsequent process until the first contact sacrificial layer 2 is exposed).
  • the second contact sacrificial layer 3 is thicker than the first contact sacrificial layer 2, and is preferably 40 to 500 nm.
  • the sum of the thicknesses of the first contact sacrificial layer 2 and the second contact sacrificial layer 3 is larger than the height of the gate to be formed later, for example, 50 to 500 nm.
  • the second contact sacrificial layer 3 material comprises S i (that is, when a portion is to be reserved later for use as part of the lift source/drain region)
  • additional ion implantation is performed by epitaxial growth while in-situ doping or epitaxial growth.
  • the process is such that the second contact sacrificial layer 3 also has a first conductivity type and a higher concentration, such as n+ or P +.
  • shallow trench isolation (STI) 4 is formed.
  • the second contact sacrificial layer 3, the first contact sacrificial layer 2, and the partially etched substrate 1 are sequentially etched by a conventional photolithography/etching technique to form shallow trenches (not shown).
  • An insulating film made of silicon oxide or silicon oxynitride is deposited in a shallow trench by PECVD, HDPCVD, RT0 (rapid thermal oxidation), MBE, ALD, etc. to form shallow trench isolation (STI) 4 .
  • the filled isolation oxide of STI 4 may also be a giant thermal expansion dielectric material having an absolute value of a linear volume expansion coefficient greater than 10-7 k at a temperature of 100 K, for example including . .
  • the cross-sectional shape of the STI 4 is not limited to the upper and lower narrow trapezoids shown in Fig. 2, and may be a rectangular shape having an upper and lower width, or a trapezoid having an upper narrow width and a lower width (to increase the stress in the lower portion of the active region).
  • the second contact sacrificial layer 3 and the first contact sacrificial layer 2 are etched to expose the gate region through the gate trench 6, thereby forming a contact sacrificial pattern.
  • the photoresist layer 5 is spin-coated over the entire device and exposed to light to form a photoresist pattern, exposing only regions where the gate stack structure is to be formed in the future.
  • anisotropic etching such as plasma etching, reactive ion etching, or the like, or TMAH (for S i materials), strong acid (HF), and strong oxidizing agents (sulfuric acid, hydrogen peroxide) are used (for S
  • TMAH for S i materials
  • strong acid HF
  • strong oxidizing agents sulfuric acid, hydrogen peroxide
  • the width of the gate trench 6 is equal to the sum of the actual width of the gate stack structure (gate insulating layer and gate conductive layer) to be formed later and the width of the gate spacer.
  • the remaining second contact sacrificial layer 3 and the first contact sacrificial layer 2 continue to cover the source and drain regions of future devices.
  • a source-drain light doping process is performed to form a source-drain lightly doped region in the substrate.
  • the photoresist pattern 5 and the contact sacrificial layer 3/2 under it are used as masks, and low-dose, low-energy oblique source-drain ion implantation is used to control the dopant implantation position by the shadow effect to form a light
  • a rapid anneal (such as laser rapid annealing) is then performed to activate the dopant.
  • the type, dose, and concentration of the dopant ions are set according to the electrical performance requirements of the device.
  • a sidewall spacer containing a diffusion source is formed, and a lightly doped source-drain extension region 1A is formed by an example diffusion, and then the layer is subsequently formed. The side wall is removed.
  • FIG. 4 a top view after removing the top photoresist pattern 5 is shown in FIG. Among them, execution
  • the STI etch process causes the side of the STI 4 exposed to the gate trench 6 as shown in the figure to be tilted toward the shallow trench isolation region instead of tilting toward the gate trench 6 to avoid forming a gate side on the STI 4 wall.
  • a gate spacer 7 is formed in the gate trench 6.
  • An insulating material such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC) is deposited by PECVD HDPCVD, MBE ALD, (magnetron) sputtering, etc., and then etched to form gate spacers 7
  • the gate trenches 6 are on both sides along the length direction of the active region (the direction of the channel region), and are in contact with the first and second contact sacrificial layers 2/3.
  • the insulating material on both sides is completely etched without forming the gate spacer.
  • the thickness of the gate spacer 7 is set according to the insulation isolation performance of the gate, for example, 5 ⁇ 30
  • a gate stack structure 8 / 9 is formed in the gate trench 6.
  • a gate insulating layer 8 is deposited on the surface of the gate trench 6 in contact with the substrate 1 by a method such as PECVD HDPCVD, MOCVD, MBE ALD or the like.
  • the material of the gate insulating layer 8 is a high-k material, including but not limited to nitride (for example, S iN A1N TiN ), metal oxide (mainly sub-group and lanthanide metal element oxide, such as A1 2 0 3 Ta 2 0 5 Ti0 2 ZnO Zr0 2 Hf0 2 Ce0 2 Y 2 0 3 La 2 0 3 ), perovskite phase oxide (eg PbZrxTihO PZT ) Ba x Sr!-Ji0 3 ( BST ) 0 Subsequently, by PECVD M0CVD MBE ALD A method of evaporating, sputtering, or the like deposits a gate conductive layer 9 on the second contact sacrificial layer 3 and in the gate trench 6.
  • nitride for example, S iN A1N TiN
  • metal oxide mainly sub-group and lanthanide metal element oxide, such as A1 2 0 3 Ta 2 0 5
  • the gate conductive layer 9 preferably includes a work function adjusting layer 9A made of a metal nitride such as TiN TaN, and a resistance adjusting layer 9B made of a metal such as Cu Al Ti Mo Ta W.
  • the gate insulating layer 8 and the gate conductive layer 9 A / 9B together constitute a gate stack structure.
  • the gate conductive layer 9A/9B is then planarized by a etch back process or a CMP process until the second contact sacrificial layer 3 is exposed. Referring to FIGS. 10 and 7, the contact sacrificial pattern is partially or completely removed, a source/drain contact trench is formed, and a metal silicide is formed in the source/drain contact trench.
  • an anisotropic wet etching solution such as TMAH is used to etch away the second contact sacrificial layer 3 of a silicon-based material such as single crystal silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon, or amorphous by oxygen plasma etching.
  • the second contact of the carbon material contacts the sacrificial layer 3.
  • the source/drain contact trench 3A is left, and the remaining second contact sacrificial layer and the gate spacer 7 are exposed.
  • the depth of the source/drain contact trench 3A as shown in FIG.
  • the second contact sacrificial layer 3 will be used as part of the future source/drain region or as one of the source and drain contacts, so the material is preferably a silicon-based material.
  • the depth of the source/drain contact trench 3A may be greater than the original thickness of the second contact sacrificial layer 3.
  • the second contact sacrificial layer 3 may be completely removed (not shown, the second contact sacrificial layer 3 may be other materials such as amorphous carbon, or even silicon nitride), and some or all of the etching may be further removed by etching.
  • the first contact sacrificial layer 2 (not shown, the first contact sacrificial layer 2 will no longer be used for a part of the source and drain regions, so the material does not have to be S iGe, S iC, etc.), and even the partial lining can be further etched and removed.
  • the substrate exposed in the source/drain contact trench 3A is heavily doped to form a heavily doped region of n+ or p+ type, As a source and drain heavily doped region.
  • a thin metal layer (not shown) is formed by sputtering and evaporation in the source/drain contact trench 3A, for example, Ni, Pt, Co, Ti, and combinations thereof, followed by rapid annealing or low temperature annealing (400 to 600). °C), causing the thin metal layer to react with Si in the source and drain regions to form a metal silicide 10 for further reducing the contact resistance. Strip a thin layer of unreacted metal. At this time, since the STI4 of the oxide material and the gate spacer 7 of the silicon nitride material do not react with the thin metal layer, the metal silicide 10 is formed only in the source and drain regions.
  • a barrier layer 11A (pad layer) of materials of TiN, TaN, and materials such as W, Al, Mo, Ti, etc. are sequentially deposited on the metal silicide 10 in the source/drain contact trench 3A.
  • the filling layer 1 IB is formed to form the source-drain contact 11.
  • the barrier layer 11 A / the filling layer 11 B is planarized by a process such as CMP. Until the gate conductive layer 9 (resistance adjusting layer 9B) of the gate stack structure is exposed.
  • the distance between the source/drain contact 11 and the gate stack structure is only the thickness of the gate spacer 7, and the pitch is greatly reduced; in addition, the source/drain contact 11 covers the entire source and drain regions, and the area thereof is compared.
  • the existing technology has been greatly improved. Therefore, such a large-area source-drain contact in accordance with the present invention effectively reduces parasitic resistance.
  • silicon oxide, silicon nitride, and an interlayer dielectric layer (ILD) 12 of a low-k material are deposited on the entire device, the ILD 12 is etched to form a source-drain contact hole, and the source-drain contact hole is filled with a metal material to form a second source/drain.
  • Contact 11C depositing a second ILD 13 such as silicon oxide, silicon nitride or other low-k material and different from ILD 12 material on the entire device, etching to form interconnect holes, and depositing Al, T i in the interconnect holes
  • the metal forms the interconnect 14 .
  • the spacing between the gate spacer and the contact region is effectively reduced by the double-layer contact sacrificial layer process, and the contact region area is increased, thereby effectively reducing the parasitic resistance of the device. .

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  • Electrodes Of Semiconductors (AREA)

Abstract

公开了一种半导体器件制造方法。该方法包括：在衬底（1）上形成接触牺牲层（2、3），刻蚀接触牺牲层（2、3）形成接触牺牲图形，其中接触牺牲图形覆盖源区与漏区并且具有暴露衬底（1）的栅极沟槽；在栅极沟槽中形成栅极侧墙（7）和栅极堆叠结构（8、9A、9B）；部分或者完全刻蚀去除覆盖源区与漏区的接触牺牲图形；形成源漏接触沟槽；在源漏接触沟槽中形成源漏接触（10、11A、11B）。该方法通过双层接触牺牲层工艺有效降低了栅极侧墙与接触区域之间的间距，并且增大了接触区域面积，从而有效减小了器件寄生电阻。

Description

半导体器件制造方法
[0001]本申请要求了 2012月 7月 24日提交的、 申请号为 201210258807.6、发明 名称为"半导体器件制造方法 "的中国专利申请的优先权， 其全部内容通过引 用结合在本申请中。 技术领域
[0002]本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种具有增大 接触区域的 M0SFET的制造方法。 背景技术
[0003] 随着 M0SFET的特征尺寸持续缩减，寄生电阻在器件的总电阻中占据的 比重越来越大， 严重制约了小尺寸器件性能的提升。 现有的降低寄生电阻的 结构 /方法包括形成提升源漏、 在源漏区中 /上形成金属硅化物、 提高接触面 积等等。
[0004]然而，无论采用何种结构 /方法， 源 /漏区的接触区域（或接触孔， CA ) 与栅极侧墙之间仍然有较大的间距， 电子 /空穴的载流子从源区穿越沟道区 达到漏区的距离仍然较大， 因此寄生电阻依然无法有效的减小， 器件性能提 升程度有限。 发明内容
[0005]有鉴于此，本发明的目的在于采用新的制造方法以接触牺牲层工艺代 替传统的替代栅工艺， 大幅减小接触区域与栅极之间的间距， 从而有效地减 小器件寄生电阻。
[0006] 实现本发明的上述目的，是通过提供一种半导体器件制造方法，包括： 在衬底上形成接触牺牲层， 刻蚀接触牺牲层形成接触牺牲图形， 其中接触牺 牲图形覆盖源区与漏区并且具有暴露衬底的栅极沟槽； 在栅极沟槽中形成栅 极侧墙和栅极堆叠结构； 部分或者完全刻蚀去除覆盖源区与漏区的接触牺牲 图形， 形成源漏接触沟槽； 在源漏接触沟槽中形成源漏接触。 [0007]其中， 接触牺牲层包括第一接触牺牲层和第二接触牺牲层。
[0008]其中， 第一接触牺牲层包括应变 S i、 S iGe、 S i: C、 多晶硅、 非晶硅、 微晶硅、 非晶碳、 氧化硅、 氮化硅及其组合， 第二接触牺牲层包括单晶硅、 多晶硅、 非晶硅、 微晶硅、 非晶碳、 氧化硅、 氮化硅及其组合。
[ 0009]其中，形成源漏接触沟槽的步骤包括：部分刻蚀去除第二接触牺牲层； 或者完全刻蚀去除第二接触牺牲层以及部分刻蚀去除第一接触牺牲层； 或者 完全刻蚀去除第二接触牺牲层和第一接触牺牲层； 或者完全刻蚀去除第二接 触牺牲层和第一接触牺牲层以及部分刻蚀衬底。
[0010]其中， 通过外延生长形成接触牺牲层并且掺杂具有第一导电类型。
[0011]其中， 形成接触牺牲层之后， 刻蚀接触牺牲层以及衬底形成浅沟槽， 在浅沟槽中填充绝缘材料形成浅沟槽隔离。
[0012]其中，形成栅极沟槽之后，刻蚀浅沟槽隔离使其在有源区宽度方向上 向隔离区倾斜。
[0013]其中，刻蚀形成接触牺牲图形之后，在栅极沟槽两侧衬底中形成轻掺 杂源漏区。
[0014]其中， 形成栅极堆叠结构包括在栅极沟槽中沉积高 k材料的栅极绝缘 层、 金属氮化物的功函数调节层以及金属的电阻调节层。
[0015]其中，形成源漏接触的步骤进一步包括： 在源漏接触沟槽中形成金属 硅化物； 在金属硅化物上依次沉积衬垫层和填充层； 平坦化填充层和衬垫层 直至暴露栅极堆叠结构。
[0016]依照本发明的半导体器件制造方法，通过双层接触牺牲层工艺有效降 低了栅极侧墙与接触区域之间的间距， 并且增大了接触区域面积， 从而有效 减小了器件寄生电阻。 附图说明
[0017] 以下参照附图来详细说明本发明的技术方案， 其中：
[0018] 图 1至图 9为根据本发明的半导体器件制造方法各个步骤的剖视图；以 及
[0019] 图 10为根据本发明的半导体器件制造方法的流程图。 具体实施方式
[0020] 以下参照附图并结合示意性的实施例来详细说明本发明技术方案的 特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本申 请中所用的术语 "第一"、 "第二"、 "上"、 "下"、 "厚"、 "薄" 等等可用于修 饰各种器件结构。 这些修饰除非特别说明并非暗示所修饰器件结构的空间、 次序或层级关系。
[0021]参照图 10以及图 1〜图 4 ,在衬底上形成接触牺牲图形，覆盖源区与漏 区并且暴露栅极区域。
[0022]如图 1所示， 在衬底 1上依次形成第一接触牺牲层 2和第二接触牺牲层 3。 提供衬底 1 , 其材质可以是（体） S i (例如单晶 S i晶片）、 S0I、 单晶 Ge、 GeOI (绝缘体上 Ge ), 也可以是其他化合物半导体， 例如 GaAs、 S iGe、 GeSn、 InP、 InSb、 GaN等等。 优选地， 衬底 1选用体 S i或 SOI , 以便与 CMOS工艺兼容。
[0023]采用 LPCVD、 PECVD、 HDPCVD、 M0CVD、 MBE、 ALD、 蒸发、 溅射等常规 方法并合理控制工艺参数， 在衬底 1上外延生长了第一接触牺牲层 2。 第一接 触牺牲层 2用于稍后器件的实际源漏区（作为提升源漏的一部分）， 其材质可 以是应变 S i、 S iGe、 S i: C及其组合， 其厚度例如是 10 ~ 100nm。 由于第一接 触牺牲层 2的材质与衬底 1的材质之间晶格常数不同， 可以向沟道区引入应 力， 因此有助于提高载流子迁移率进而提高器件驱动能力。 优选地， 通过外 延生长同时原位掺杂或者外延生长后额外的离子注入工艺，使得第一接触牺 牲层 2具有第一导电类型， 例如 n或者 p。 此外， 第一接触牺牲层 2还可以是多 晶硅、 非晶硅、 微晶硅、 非晶碳、 氧化硅、 氮化硅等， 此时第一接触牺牲层 2将在稍后的图 7所示形成源漏接触沟槽的过程中完全去除。
[0024] 随后， 通过类似的外延工艺， 在第一接触牺牲层 2之上再外延形成第 二接触牺牲层 3 , 用于限定稍后要形成源漏接触的区域， 与后栅工艺中假栅 极所起的作用类似， 因此也可以称作假源漏接触区。 第二接触牺牲层 3材质 可以与衬底 1相同例如均为 S i (可以是单晶硅， 也可以是多晶硅、 非晶硅、 部分用作提升源漏区的一部分）， 材质也可以不同， 例如为非晶碳、 氮化硅、 氧化硅、 氮氧化硅（此时第二接触牺牲层 3在后续工艺中将刻蚀完全去除而 直至暴露第一接触牺牲层 2 )。 第二接触牺牲层 3厚度要大于第一接触牺牲层 2 , 并且优选的是 40 ~ 500nm。 第一接触牺牲层 2与第二接触牺牲层 3的厚度之 和要大于稍后要形成的栅极的高度， 例如是 50 ~ 500nm。 优选地， 当第二接 触牺牲层 3材质包括 S i时 （也即稍后将要保留一部分用作提升源漏区的一部 分时）， 通过外延生长同时原位掺杂或者外延生长后额外的离子注入工艺， 使得第二接触牺牲层 3也具有第一导电类型并且浓度更高， 例如 n+或者 P+。
[0025]如图 2所示， 形成浅沟槽隔离 （STI ) 4。 利用传统的光刻 /刻蚀技术， 依次刻蚀穿透第二接触牺牲层 3、 第一接触牺牲层 2 , 以及部分刻蚀衬底 1 , 形成浅沟槽（未示出）。 通过 PECVD、 HDPCVD、 RT0 (快速热氧化）、 MBE、 ALD 等方法， 在浅沟槽中沉积填充氧化硅或者氮氧化硅材质的绝缘膜， 从而构成 浅沟槽隔离（STI ) 4。 此外优选地， STI 4的填充的隔离氧化物还可以是 100K 的温度下线性体积膨胀系数的绝对值大于 10— 7κ的巨热膨胀介质材料， 例如 包括^。.951^。.。5 03、 BiNi03、 ZrWA等的钙钛矿型氧化物，或者诸如 Ag3 [Co (CN) 6： 的框架材料。 这些巨热膨胀介质材料可以向有源区施加应力， 进一步增大载 流子迁移率， 提高器件性能。 STI 4的剖面形状不限于图 2中所示的上宽下窄 的梯形， 还可以是上下等宽的矩形、 或者是上窄下宽的梯形（以增大有源区 下部的应力）。
[0026]如图 3所示，刻蚀第二接触牺牲层 3和第一接触牺牲层 2通过栅极沟槽 6 暴露栅极区域， 而形成了接触牺牲图形。 在整个器件上旋涂光刻胶层 5并曝 光显影形成光刻胶图形， 仅暴露未来要形成栅极堆叠结构的区域。 随后， 采 用各向异性的刻蚀， 例如等离子刻蚀、 反应离子刻蚀等干法刻蚀， 或者 TMAH (针对 S i材料）、 强酸（HF ) 与强氧化剂 （硫酸、 双氧水）组合（针对 S iGe 材料）等湿法刻蚀， 刻蚀第二接触牺牲层 3以及第一接触牺牲层 2直至暴露衬 底 1 , 形成了栅极沟槽 6。 其中， 栅极沟槽 6的宽度要等于稍后要形成的栅极 堆叠结构（栅极绝缘层以及栅极导电层 )的实际宽度与栅极侧墙的宽度之和。 剩余的第二接触牺牲层 3和第一接触牺牲层 2继续覆盖了未来器件的源区和 漏区。
[0027]优选地， 执行源漏轻掺杂工艺， 在衬底中形成源漏轻掺杂区。 例如以 光刻胶图形 5及其下方的接触牺牲层 3/2为掩模， 采用低剂量、 低能量的倾 斜源漏离子注入， 利用阴影效应 （Shadow Effect )控制了掺杂剂注入位置 而形成了轻掺杂的源漏延伸区 1A、 以及源漏延伸区 1A下方衬底中的晕状 ( Ha lo )源漏掺杂区 1B。 随后快速退火（例如激光快速退火）以激活掺杂剂。 掺杂离子的种类、 剂量、 浓度依照器件电学性能需要而设定。 此外， 可选地， 在栅极沟槽 6中在接触牺牲层 3/2两侧， 形成含有扩散源的侧墙， 通过例子 扩散作用形成轻掺杂的源漏延伸区 1A, 随后将该层侧墙去除。
[0028]如图 4所示， 为图 3去除顶部光刻胶图形 5之后的顶视图。 其中， 执行
STI刻蚀工艺，使得如图中所示的 STI4暴露于栅极沟槽 6部分的侧面向浅沟槽 隔离区倾斜而不是向栅极沟槽 6倾斜， 以避免在 STI 4上形成栅极侧墙。
[0029]参照图 10以及图 5 , 在栅极沟槽 6中形成栅极侧墙 7。 通过 PECVD HDPCVD, MBE ALD、 （磁控） 溅射等方法沉积例如为氮化硅、 氮氧化硅、 类 金刚石无定形碳（DLC )的绝缘材质并且随后刻蚀形成了栅极侧墙 7 , 位于栅 极沟槽 6中沿有源区长度方向 （沟道区方向） 的两个侧面上， 并且与第一和 第二接触牺牲层 2/ 3接触。 由于栅极沟槽 6中沿有源区宽度方向（器件延伸方 向）的 STI4向浅沟槽隔离区倾斜， 两个侧面上的绝缘材质被完全刻蚀， 而不 会形成栅极侧墙。 栅极侧墙 7的厚度依照栅极绝缘隔离性能需要而设定， 例 如为 5 ~ 30
[0030]参照图 10以及图 6 ,在栅极沟槽 6中形成栅极堆叠结构 8 / 9。通过 PECVD HDPCVD, MOCVD, MBE ALD等方法， 在栅极沟槽 6底部与衬底 1接触的面上沉 积形成栅极绝缘层 8。 栅极绝缘层 8的材质为高 k材料， 包括但不限于氮化物 (例如 S iN A1N TiN )、 金属氧化物 （主要为副族和镧系金属元素氧化物， 例如 A1203 Ta205 Ti02 ZnO Zr02 Hf02 Ce02 Y203 La203 )、 钙钛矿相氧 化物（例如 PbZrxTihO PZT ) BaxSr!-Ji03 ( BST ) )0随后，通过 PECVD M0CVD MBE ALD, 蒸发、 溅射等方法在第二接触牺牲层 3上以及栅极沟槽 6中沉积栅 极导电层 9。 栅极导电层 9优选地包括材质为 TiN TaN等金属氮化物的功函数 调节层 9A, 以及材质为 Cu Al Ti Mo Ta W等金属的电阻调节层 9B。 栅 极绝缘层 8与栅极导电层 9 A/ 9B共同构成栅极堆叠结构。 随后采用回刻工艺或 者 CMP工艺， 平坦化栅极导电层 9A/9B直至暴露第二接触牺牲层 3 [0031]参照图 10以及图 7 , 部分或者完全去除接触牺牲图形， 形成源漏接触 沟槽， 在源漏接触沟槽中形成金属硅化物。 例如采用 TMAH等各向异性的湿法 腐蚀液， 刻蚀去除单晶硅、 多晶硅、 非晶硅、 微晶硅等硅基材质的第二接触 牺牲层 3 ,或者采用氧等离子刻蚀去除非晶碳材质的第二接触牺牲层 3。由此， 部分（或者完全）去除了第二接触牺牲层 3之后， 留下了源漏接触沟槽 3A, 暴露了剩余的第二接触牺牲层以及栅极侧墙 7。 根据本发明一个实施例的如 图 7所示的源漏接触沟槽 3A深度小于第二接触牺牲层 3的原始厚度，也即仅部 分去除了第二接触牺牲层 3 (此时剩余的部分第二接触牺牲层 3将要作为未来 源漏区的一部分或者作为源漏接触之一， 因此其材质优选的为硅基材质）。 但是在本发明其他实施例中， 源漏接触沟槽 3A的深度可以大于第二接触牺牲 层 3的原始厚度。 具体地， 可以完全去除第二接触牺牲层 3 (未示出， 此时第 二接触牺牲层 3可以是非晶碳等其他材质， 甚至可以是氮化硅）， 还可以继续 刻蚀去除部分或者全部的第一接触牺牲层 2 (未示出， 此时第一接触牺牲层 2 将不再用于源漏区一部分， 因此材质不必为 S iGe、 S iC等）， 甚至可以进一步 刻蚀去除部分衬底 1 , 形成的源漏接触沟槽 3 A深入衬底（此时可以在深沟槽 中外延形成 S iGe、 S iC并且进一步形成提升源漏）。
[0032]特别地， 若完全去除第二接触牺牲层 3及第一接触牺牲层 2 (或外延生 长接触牺牲层 2 / 3过程中没有进行原位掺杂并且外延生长后没有进行额外的 离子注入）， 对源漏接触沟槽 3A中暴露的衬底（或第二接触牺牲层 3和 /或第 一接触牺牲层 2 )进行重掺杂， 使其形成 n+或者 p+型的重掺杂区， 以作为源 漏重掺杂区。
[0033]此后， 在源漏接触沟槽 3A中溅射、 蒸发形成金属薄层（未示出）， 例 如是 Ni、 Pt、 Co、 Ti及其组合， 然后快速退火或者低温退火（ 400 ~ 600 °C ), 使得金属薄层与源漏区中的 S i反应形成金属硅化物 10 ,用于进一步降低接触 电阻。 剥除未反应的金属薄层。 此时由于氧化物材料的 STI4、 氮化硅材质的 栅极侧墙 7与金属薄层不反应， 因此金属硅化物 10仅形成在源漏区中。
[0034]参照图 10和图 8 , 在源漏接触沟槽 3A中金属硅化物 10上依次沉积 T iN、 TaN的材质的阻挡层 11A (衬垫层） 以及 W、 Al、 Mo、 Ti等材质的填充层 1 IB, 以形成了源漏接触 11。优选地，采用 CMP等工艺平坦化阻挡层 11 A/填充层 11 B , 直至暴露栅极堆叠结构的栅极导电层 9 (电阻调节层 9B )。 此时， 源漏接触 11 与栅极堆叠结构之间的间距仅为栅极侧墙 7的厚度， 该间距大幅减小了； 此 外， 源漏接触 11覆盖了整个源漏区， 其面积较之现有技术大幅提升。 因此， 依照本发明的这种大面积源漏接触有效降低了寄生电阻。
[0035]参照图 10和图 9 , 完成后续工艺。 例如在整个器件上沉积氧化硅、 氮 化硅、 低 k材质的层间介质层（ILD ) 12 , 刻蚀 ILD 12形成源漏接触孔， 在源 漏接触孔中填充金属材料形成第二源漏接触 11C , 在整个器件上沉积例如为 氧化硅、 氮化硅或者其他低 k材料并且与 ILD 12材质不同的第二 ILD 13 , 刻 蚀形成互连孔， 在互连孔中沉积 Al、 T i等金属形成互连线 14。
[0036]依照本发明的半导体器件制造方法，通过双层接触牺牲层工艺有效降 低了栅极侧墙与接触区域之间的间距， 并且增大了接触区域面积， 从而有效 减小了器件寄生电阻。
[0037]尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可 以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变 和等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材料的 修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作为用于实现 本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造 方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括：
在衬底上形成接触牺牲层， 刻蚀接触牺牲层形成接触牺牲图形， 其中接 触牺牲图形覆盖源区与漏区并且具有暴露衬底的栅极沟槽；
在栅极沟槽中形成栅极侧墙和栅极堆叠结构；
部分或者完全刻蚀去除覆盖源区与漏区的接触牺牲图形，形成源漏接触 沟槽；
在源漏接触沟槽中形成源漏接触。
2. 如权利要求 1的半导体器件制造方法， 其中， 接触牺牲层包括第一 接触牺牲层和第二接触牺牲层。
3. 如权利要求 2的半导体器件制造方法， 其中， 第一接触牺牲层包括 应变 S i、 S iGe、 S i: C、 多晶硅、 非晶硅、 微晶硅、 非晶碳、 氧化硅、 氮化硅 及其组合， 第二接触牺牲层包括单晶硅、 多晶硅、 非晶硅、 微晶硅、 非晶碳、 氧化硅、 氮化硅及其组合。
4. 如权利要求 2的半导体器件制造方法， 其中， 形成源漏接触沟槽的 步骤包括： 部分刻蚀去除第二接触牺牲层； 或者完全刻蚀去除第二接触牺牲 层以及部分刻蚀去除第一接触牺牲层； 或者完全刻蚀去除第二接触牺牲层和 第一接触牺牲层； 或者完全刻蚀去除第二接触牺牲层和第一接触牺牲层以及 部分刻蚀衬底。
5. 如权利要求 1的半导体器件制造方法， 其中， 通过外延生长形成接 触牺牲层并且掺杂具有第一导电类型。
6. 如权利要求 1的半导体器件制造方法，其中，形成接触牺牲层之后， 刻蚀接触牺牲层以及衬底形成浅沟槽，在浅沟槽中填充绝缘材料形成浅沟槽 隔离。
7. 如权利要求 6的半导体器件制造方法， 其中， 形成栅极沟槽之后， 刻蚀浅沟槽隔离使其在有源区宽度方向上向隔离区倾斜。
8. 如权利要求 1的半导体器件制造方法， 其中， 刻蚀形成接触牺牲图 形之后， 在栅极沟槽两侧衬底中形成轻掺杂源漏区。
9. 如权利要求 1的半导体器件制造方法， 其中， 形成栅极堆叠结构包 括在栅极沟槽中沉积高 k材料的栅极绝缘层、 金属氮化物的功函数调节层以 及金属的电阻调节层。
10. 如权利要求 1的半导体器件制造方法， 其中， 形成源漏接触的步骤 进一步包括：
在源漏接触沟槽中形成金属硅化物；
在金属硅化物上依次沉积衬垫层和填充层；
平坦化填充层和衬垫层直至暴露栅极堆叠结构。
PCT/CN2012/079694 2012-07-24 2012-08-03 半导体器件制造方法 Ceased WO2014015536A1 (zh)

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