WO2014008732A1 - 发光控制电路、发光控制方法和移位寄存器 - Google Patents

发光控制电路、发光控制方法和移位寄存器 Download PDF

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Publication number
WO2014008732A1
WO2014008732A1 PCT/CN2012/084973 CN2012084973W WO2014008732A1 WO 2014008732 A1 WO2014008732 A1 WO 2014008732A1 CN 2012084973 W CN2012084973 W CN 2012084973W WO 2014008732 A1 WO2014008732 A1 WO 2014008732A1
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Prior art keywords
thin film
film transistor
source
gate
signal
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PCT/CN2012/084973
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English (en)
French (fr)
Inventor
金泰逵
金馝奭
王颖
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/126,640 priority Critical patent/US9113534B2/en
Priority to EP12880722.9A priority patent/EP2874140B1/en
Publication of WO2014008732A1 publication Critical patent/WO2014008732A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/60—Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • Illumination control circuit Illumination control circuit, illumination control method and shift register
  • the present invention relates to the field of organic light emitting display, and more particularly to an illumination control circuit, an illumination control method, and a shift register. Background technique
  • OLEDs Organic light-emitting display diodes
  • PMOLEDs passive matrix organic light-emitting display diodes
  • ITO Indium Tin Oxide
  • AMOLED active matrix organic light-emitting display diode
  • the state control signal of the light emitting display diode is a positive level signal for the AMOLED display backplane formed by the P type transistor to ensure that the OLED device is turned off during the writing of the display data into the pixel unit, and the display data is written to the pixel. After the unit, the OLED device turns on the illumination to ensure that the displayed image does not flicker due to the unstable state of the pixel circuit at the time of data writing.
  • the main object of the present invention is to provide an illumination control circuit, an illumination control method, and a shift register, which can ensure that an OLED device is in a closed state during display data writing into a pixel unit, and an OLED is displayed after the display data is written into the pixel unit.
  • the device turns on the illumination, thereby ensuring that the displayed image does not flicker due to the unstable state of the pixel circuit in the writing of data.
  • an embodiment of the present invention provides an illumination control circuit for generating an illumination control signal for controlling illumination of an OLED in an AMOLED, the illumination control signal being inverted from a gate drive signal;
  • the illumination control circuit includes an input end, an input sampling unit, an output unit, a reset unit, Output pull-down unit and illumination control signal output, wherein
  • the output pull-down unit is connected to the light-emitting control signal output end
  • the input sampling unit is respectively connected to the input end, the first clock signal input end and the output pull-down unit, for sampling the input signal under the control of the first clock signal, and The obtained signal is transmitted to the output of the illumination control signal through the output pull-down unit;
  • the output unit is respectively connected to the input sample unit, the second clock signal input end and the illumination control signal output end, After the input signal is sampled by the input sampling unit, generating an illumination control signal under the control of the second clock signal, and transmitting the illumination control signal to the output of the illumination control signal;
  • the reset unit is respectively connected to the third clock signal input end and the output pull-down unit, and is configured to send a reset control signal to the output pull-down unit under the control of the third clock signal;
  • the output pull-down unit is configured to reset the illumination control signal according to the reset control signal.
  • the input sampling unit comprises a first thin film transistor and a second thin film transistor
  • a first thin film transistor a gate connected to the first clock signal input terminal, a source connected to the output unit, and a drain connected to the input end;
  • the second thin film transistor has a gate connected to the first clock signal input terminal, a source connected to the output unit, and a drain connected to the low level output terminal of the driving power source.
  • the output unit includes a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a first capacitor, and a second capacitor;
  • a third thin film transistor having a gate connected to a source of the first thin film transistor, a source connected to a gate of the fourth thin film transistor, and a drain connected to the second clock signal input end;
  • a fourth thin film transistor having a gate connected to a source of the third thin film transistor, a source connected to a gate of the sixth thin film transistor, and a drain connected to a low level output terminal of the driving power source;
  • the gate is connected to the second clock signal input end, the source is connected to the high level output end of the driving power source, and the drain is connected to the source of the second thin film transistor;
  • the source is connected to a high level output terminal of the driving power source, and the drain is connected to a source of the twelfth thin film transistor;
  • the gate is connected to the second clock signal input terminal, and the source and the driving power source a high level output terminal is connected, and a drain is connected to a source of the thirteenth thin film transistor;
  • the second capacitor is connected between the gate of the sixth thin film transistor and the low level output terminal of the driving power source.
  • the reset unit includes an eighth thin film transistor and a ninth thin film transistor
  • An eighth thin film transistor the gate is connected to the third clock signal input end, the source is connected to the high level output end of the driving power source, and the drain is connected to the source of the first thin film transistor;
  • the ninth thin film transistor has a gate connected to the third clock signal input terminal, a source connected to the source of the second thin film transistor, and a drain connected to the low level output terminal of the driving power source.
  • the output pull-down unit includes a tenth thin film transistor, an eleventh thin film transistor, a twelfth thin film transistor, a thirteenth thin film transistor, a third capacitor, a fourth capacitor, a fifth capacitor, and a Six capacitors;
  • a tenth thin film transistor having a gate connected to a gate of the eleventh thin film transistor, a source connected to a high level output terminal of the driving power source, and a drain connected to a source of the third thin film transistor;
  • An eleventh thin film transistor the source is connected to a high level output terminal of the driving power source, and the drain is connected to a source of the fourth thin film transistor;
  • a twelfth thin film transistor having a gate connected to a source of the second thin film transistor, a source connected to a drain of the sixth thin film transistor, and a drain connected to a low level output terminal of the driving power source;
  • the gate is connected to the gate of the tenth thin film transistor, the source is connected to the output end of the light emission control signal, and the drain is connected to the low level output end of the driving power source;
  • a fifth capacitor connected between the gate of the tenth thin film transistor and the low level output terminal of the driving power source
  • the sixth capacitor is connected between the output of the light-emitting control signal and the low-level output of the driving power source.
  • An illumination control circuit in accordance with an embodiment of the present invention further includes an inverting output;
  • a gate of the fourth thin film transistor is connected to the inverted output end
  • a signal output from the inverting output is inverted from the illumination control signal.
  • the tube, the eighth thin film transistor, the ninth thin film transistor, the tenth thin film transistor, the eleventh thin film transistor, the twelfth thin film transistor, and the thirteenth thin film transistor are p-type TFTs.
  • An embodiment of the present invention further provides an illumination control method, which is applied to the above illumination control circuit, for generating an illumination control signal for controlling illumination of an OLED in an AMOLED, wherein the illumination control signal is inverted from a gate drive signal;
  • the illumination control method includes the following steps:
  • Input sample step The input sample unit samples the input signal under the control of the first clock signal, and transmits the sampled signal to the output of the illumination control signal through the output pull-down unit;
  • Output step At the input ⁇ After the sample unit samples the input signal, the output unit generates an illumination control signal under the control of the second clock signal, and transmits the illumination control signal to the output end of the illumination control signal;
  • Reset step The reset unit resets the illumination control signal through the output pull-down unit under the control of the third clock signal.
  • Embodiments of the present invention also provide a shift register including a plurality of stages of the above illumination control circuit
  • the input signal of the nth stage illumination control circuit is a signal inverted from the illumination control signal of the (n-2)th stage illumination control circuit, except for the first stage illumination control circuit and the second stage illumination control circuit;
  • the input signal of the illumination control circuit and the input signal of the second-stage illumination control circuit are start signals;
  • n is an integer greater than 2 and less than or equal to N, and N is the number of stages of the illumination control circuit included in the shift register.
  • the illumination control circuit, the illumination control method, and the shift register of the embodiment of the present invention are combined with the illumination control signal for generating the gate drive signal inversion so that the display data is written into the pixel unit.
  • the OLED device is turned off, and after the display data is written into the pixel unit, the OLED device turns on the light, thereby ensuring that the display image does not flicker due to the unstable state of the pixel circuit in the writing of data.
  • FIG. 1 is a circuit diagram of an illumination control circuit according to a first embodiment of the present invention
  • Figure 2 is a circuit diagram of a light emission control circuit of a second embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present invention
  • 4 is an operation timing chart in the light emission control circuit of the second embodiment of the present invention
  • FIG. 5 is an operation timing chart of the shift register shown in FIG. detailed description
  • a gate drive circuit is used to generate row gate control of the pixel circuit array.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the OLED is a current-driven device, so controlling the current path into the OLED can control the illumination of the OLED device. Therefore, in order to accurately control the illumination of the OLED in an AMOLED (Active Matrix Organic Light Emitting Diode) display, embodiments of the present invention provide an illumination control circuit, an illumination control method, and a shift register.
  • the illumination control circuit of the embodiment of the present invention works in conjunction with a conventional gate drive circuit for performing separate control of the operational states of the OLED and the pixel circuit.
  • the illumination control circuit of the first embodiment of the present invention is configured to generate an illumination control signal for controlling illumination of an OLED in an AMOLED, wherein the illumination control signal is inverted with a gate drive signal; and the illumination control circuit includes Input terminal Input, input sample unit 11, output unit 12, reset unit 13, output pull-down unit 14, and light-emission control signal output terminal EM[n], wherein
  • the input sampling unit 11 is respectively connected to the input terminal Input, the output unit 12, the first clock signal input end and the output pull-down unit 14 for inputting under the control of the first clock signal
  • the signal is sampled, and the signal obtained by the sample is transmitted to the light emission control signal output terminal EM[n] through the output pull-down unit 14;
  • the output unit 12 is respectively connected to the input sampling unit 11, the second clock signal input end and the illumination control signal output end EM[n], and is configured to perform an input signal on the input sampling unit 11 After the sample is generated, the illumination control signal is generated under the control of the second clock signal, and the illumination control signal is transmitted to the illumination control signal output terminal EM[n];
  • the reset unit 13 is respectively connected to the third clock signal input end and the output pull-down unit 14 for issuing a reset control signal to the output pull-down unit under the control of the third clock signal; a low unit 14 connected to the illumination control signal output terminal EM[n] for resetting the illumination control signal according to the reset control signal;
  • the first clock signal CK1 is input from the first clock signal input terminal
  • the second clock signal CK2 is input from the second clock signal input terminal
  • the third clock signal CK3 is input from the third clock signal input terminal.
  • the illumination control circuit of the first embodiment of the present invention can generate an illumination control signal for controlling the illumination of the OLED in the AMOLED, and the illumination control signal is inverted from the gate drive signal, and
  • the AMOLED (Active Matrix Organic Light Emitting Diode) display accurately controls the illumination of the OLED so that the OLED device is turned off during the process of writing the display data into the pixel unit, and the OLED device is after the display data is written into the pixel unit.
  • the illumination is turned on, thereby ensuring that the display image does not flicker due to the unstable state of the pixel circuit in the writing of data.
  • Fig. 2 is a circuit diagram of a light emission control circuit of a second embodiment of the present invention. As shown in Fig. 2, the illumination control circuit of the second embodiment of the present invention is based on the illumination control circuit of the first embodiment of the present invention. In the illumination control circuit of the second embodiment of the present invention,
  • the input sampling unit includes a first thin film transistor T1 and a second thin film transistor T2;
  • the output unit includes a third thin film transistor T3, a fourth thin film transistor ⁇ 4, a fifth thin film transistor ⁇ 5, a sixth thin film transistor ⁇ 6, a seventh thin film transistor ⁇ 7, a first capacitor C1 and a second capacitor C2;
  • the reset unit includes an eighth thin film transistor ⁇ 8 and a ninth thin film transistor ⁇ 9;
  • the output pull-down unit includes a tenth thin film transistor ⁇ 10, an eleventh thin film transistor T11, a twelfth thin film transistor ⁇ 12, a thirteenth thin film transistor ⁇ 13, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a Six capacitor C6;
  • the first thin film transistor T1 has a gate connected to the first clock signal input end, a source connected to the gate of the third thin film transistor T3, and a drain connected to the input terminal Input;
  • the second thin film transistor T2 has a gate connected to the first clock signal input end, a source connected to the drain of the fifth thin film transistor T5, and a drain connected to the low level output end of the driving power source;
  • the third thin film transistor T3 has a source connected to the gate of the fourth thin film transistor T4, and a drain connected to the second clock signal input end;
  • a fourth thin film transistor T4 the source is connected to the gate of the sixth thin film transistor T6, and the drain is connected to the low level output terminal of the driving power source;
  • a fifth thin film transistor T5 the gate is connected to the second clock signal input end, and the source is connected to the high level output end of the driving power source;
  • a sixth thin film transistor the source is connected to a high level output terminal of the driving power source, and the drain is connected to a source of the twelfth thin film transistor T12; a seventh thin film transistor T7, the gate is connected to the second clock signal input end, the source is connected to the high level output end of the driving power source, and the drain is connected to the source of the thirteenth thin film transistor T13;
  • the eighth thin film transistor T8 has a gate connected to the third clock signal input end, a source connected to the high level output terminal of the driving power source, and a drain connected to the source of the first thin film transistor T1;
  • a ninth thin film transistor T9 the gate is connected to the third clock signal input end, the source is connected to the source of the second thin film transistor T2, and the drain is connected to the low level output end of the driving power source;
  • a tenth thin film transistor T10 a gate connected to a gate of the eleventh thin film transistor T11, a source connected to a high level output terminal of the driving power source, and a drain connected to a source of the third thin film transistor T3;
  • the transistor T11 has a source connected to a high level output terminal of the driving power source, and a drain connected to a source of the fourth thin film transistor T4;
  • a twelfth thin film transistor T12 a gate connected to a source of the second thin film transistor T2, a source connected to a drain of the sixth thin film transistor T6, and a drain connected to a low level output end of the driving power source;
  • the transistor T13 has a gate connected to the gate of the tenth thin film transistor T10, the source is connected to the light emission control signal output terminal EM[n], and the drain is connected to the low level output end of the driving power source;
  • the first capacitor C1 is connected to Between the gate and the source of the third thin film transistor T3;
  • the second capacitor C2 is connected between the gate of the sixth thin film transistor T6 and the low level output terminal of the driving power source;
  • the third capacitor C3 is connected between the gate and the source of the twelfth thin film transistor T12; the fourth capacitor C4 is connected between the gate and the source of the thirteenth thin film transistor T13; the fifth capacitor C5 is connected Between the gate of the tenth thin film transistor T10 and the low level output terminal of the driving power source;
  • a sixth capacitor C6 connected between the output control terminal EM[n] of the illumination power supply and the low level output terminal of the driving power supply;
  • the N1 point is a node connected to the gate of the third thin film transistor T3;
  • the N2 point is a node connected to the gate of the fourth thin film transistor T4;
  • the N3 point is a node connected to the gate of the sixth thin film transistor T6;
  • N4 point is a node connected to the gate of the twelfth thin film transistor T12;
  • N5 point is a node connected to the gate of the thirteenth thin film transistor T13;
  • the N2 point (ie, the inverting output terminal EM_Out) is connected to the next stage shift register unit circuit to provide an input signal for the next stage shift register unit circuit;
  • the signal output from the inverting output terminal EM_Out is inverted from the illumination control signal; wherein Cl, C3 and C4 are bootstrap capacitors, C2, C4 and C6 are storage capacitors; bootstrap capacitors are mainly used for lifting The level of the node is high or low, and the storage capacitor is mainly used to maintain the level of the node.
  • the thin film transistor ⁇ 9, the tenth thin film transistor ⁇ 10, the eleventh thin film transistor T11, the twelfth thin film transistor T12, and the thirteenth thin film transistor T13 are p-type TFTs.
  • a shift register according to an embodiment of the present invention includes a plurality of stages of the illumination control circuit of the second embodiment of the present invention
  • the input terminal Input of the nth stage illumination control circuit is coupled to the inverting output terminal EM_Out of the (n-2)th stage illumination control circuit;
  • the input end of the first stage illumination control circuit and the input end of the second stage illumination control circuit are connected to the start signal input end;
  • n is an integer greater than 2 and less than or equal to N, where N is the number of stages of the illumination control circuit included in the shift register;
  • STAGE-1, STAGE-2, STAGE-3, STAGE-4, STAGE-5, STAGE-6, STAGE-7, and STAGE-8 indicate the first-level illumination control circuit and the second stage, respectively.
  • first clock signal, the second clock signal, and the third clock signal connected to the odd-numbered illumination control circuit are: CLK1-1, CLKl-2, CLK1-3;
  • the first clock signal, the second clock signal, and the third clock signal connected to the even-numbered illumination control circuit are: CLK2-1, CLK2-2, CLK2-3.
  • the pulse width of STV is twice the pulse width of CK1, the pulse width of CK2, and the pulse width of CK3;
  • the first falling edge of CK1 is aligned with the falling edge of STV;
  • the first falling edge of CK2 is aligned with the first rising edge of CK1;
  • the first falling edge of CK3 is aligned with the rising edge of STV;
  • the duty cycle of CK1, the duty cycle of CK2, and the duty cycle of CK3 are 1/3.
  • the tl phase is the input sampling phase.
  • the input signal STV is also low, and CK1 is low, T1 is turned on, and CK3 is high, T8 is off, then N1 is at this time.
  • the level of the point is pulled down to VGL+ I Vthp I ; at the same time, since CK1 is low level, T2 is turned on, N4 is low level, T12 is turned on, and point N5 is low level, on the one hand, T10 and T11 are turned on.
  • the levels of points N2 and N3 are high, transistors T4 and T6 are turned off, the levels of points N3 and N5 are ensured, and on the other hand, T13 is turned on, and the output of the illumination control signal output terminal EM[n] is output.
  • the light emission control signal is low level; wherein, Vthp is a threshold voltage of the p-type thin film transistor;
  • the t2 phase is the output phase, CK1 and CK3 are high level, and the transistors T1, T3, T2, and T9 are all turned off. Due to the bootstrap action of the capacitor C1, the N1 point level will be pulled down correspondingly, T3 is turned on, and the CK2 signal is Low level, at this time, the N2 level is low, then T4 is turned on, and the N3 level is pulled low. Correspondingly, T6 is turned on, point N5 is high, T13 is off; since CK2 is low, When T7 is turned on, the illumination control signal outputted by the illumination control signal output terminal EM[n] is a high level signal, and provides an on signal for the OLED device;
  • the t3 phase is the reset phase, and CK3 is low.
  • T8 and ⁇ 9 are turned on, and the point N1 level is pulled high, and the point ⁇ 4 level is pulled low.
  • T12 is turned on, and the level of ⁇ 5 is low.
  • T10 and Til are turned on.
  • Pull points N2 and N3 high, T4 and T6 are turned off to ensure the level of points N3 and N5; since point N5 is low level and T13 is turned on, then the illumination control of the output of EM[n] at the output of illumination control signal The signal is pulled low again to complete the reset of the illumination control signal.
  • EM_out-1, EM_out-2, EM_out-n indicate the first-level illumination control circuit, respectively.
  • EM-1, EM-2, EM-n indicate the illumination control signal output by the first-level illumination control circuit, the illumination control signal output by the second-stage illumination control circuit, and the illumination control signal output by the n-th illumination control circuit. ;
  • n is an integer equal to or smaller than the number of stages of the light emission control circuit included in the shift register
  • Pulse width of CLK1-1, pulse width of CLK1-2, pulse width of CLK1-3, pulse width of CLK2-1, CLK2-2 The pulse width is the same as the pulse width of CLK2-3;
  • the pulse width of the start signal STV is the pulse width of CLK1-1, the pulse width of CLK1-2, the pulse width of CLK1-3, the pulse width of CLK2-1, the pulse width of CLK2-2, and the CLK2-3. Double the pulse width; the first falling edge of CLK1-1 is aligned with the falling edge of STV;
  • the first falling edge of CLK1-2 is aligned with the first rising edge of CLK1-1;
  • the first falling edge of CLK1-3 is aligned with the rising edge of STV;
  • the first falling edge of CLK2-1 is located at 1/4 of the STV pulse width, which is 1/2 of the pulse width of CLK1-1 itself;
  • the first falling edge of CLK2-2 is aligned with the first rising edge of CLK2-1;
  • the first falling edge of CLK2-3 is aligned with the first rising edge of CLK2-2;
  • the duty cycle of CLK1-1, the duty cycle of CLK1-2, the duty cycle of CLK1-3, the duty cycle of CLK2-1, the duty cycle of CLK2-2, and the duty cycle of CLK2-3 are 1/ 3.
  • An embodiment of the present invention further provides an illumination control method for generating an illumination control signal for controlling illumination of an OLED in an AMOLED, the illumination control signal being inverted with a gate drive signal; and the illumination control method includes the following steps:
  • Input sample step The input sample unit samples the input signal under the control of the first clock signal, and transmits the sampled signal to the output of the illumination control signal through the output pull-down unit;
  • Output step At the input ⁇ After the sample unit samples the input signal, the output unit generates an illumination control signal under the control of the second clock signal, and transmits the illumination control signal to the output of the illumination control signal; the illumination control signal is provided to the OLED device.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Electroluminescent Light Sources (AREA)

Abstract

一种发光控制电路、发光控制方法和移位寄存器。发光控制电路包括输入端（Input）、输入采样单元（11）、输出单元（12）、复位单元（13）、输出拉低单元（14）和发光控制信号输出端（EM[n]），输入采样单元（11）在第一时钟信号（CK1）的控制下对输入信号进行采样；输出单元（12）在输入采样单元（11）对输入信号进行采样后，在第二时钟信号（CK2）的控制下产生发光控制信号；复位单元（13）在第三时钟信号（CK3）的控制下通过输出拉低单元（14）对发光控制信号进行复位。在显示数据写入像素单元的过程中，OLED器件处于关闭状态，而显示数据写入像素单元后，OLED器件开启发光，从而确保显示图像不会由于像素电路在数据的写入的不稳定状态发生闪烁。

Description

发光控制电路、 发光控制方法和移位寄存器 技术领域
本发明涉及有机发光显示领域， 尤其涉及一种发光控制电路、 发光控制 方法和移位寄存器。 背景技术
有机发光显示二极管 （OLED ) 由于具有高亮度、 宽视角、 较快的响应 速度等优点， 已越来越多地被应用于高性能显示中。 传统的无源矩阵有机发 光显示二极管 （PMOLED ) 随着显示尺寸的增大， 需要更短的单个像素的驱 动时间， 因而需要增大瞬态电流， 增加功耗； 同时大电流的应用会造成 ITO 线上压降过大， 并使 OLED工作电压过高， 进而降低其效率。 而有源矩阵有 机发光显示二极管（AMOLED )通过开关管逐行扫描输入 OLED电流， 可以 很好地解决这些问题。
对于 AMOLED (有源矩阵有机发光二极管 )显示， 不仅需要产生行选通 信号， 控制与该栅线相连像素的开 /关状态， 还需要对于有机发光显示二极管 的开 /关状态进行控制， 该有机发光显示二极管的状态控制信号对于 P型晶体 管构成的 AMOLED显示背板是一正电平信号， 来确保在显示数据写入像素 单元的过程中， OLED器件处于关闭状态， 而当显示数据写入像素单元之后， OLED 器件开启发光， 以此来确保显示图像不会由于像素电路在数据的写入 时的不稳定状态发生闪烁。 发明内容
本发明的主要目的在于提供一种发光控制电路、 发光控制方法和移位寄 存器， 可以确保在显示数据写入像素单元的过程中， OLED 器件处于关闭状 态， 而显示数据写入像素单元后， OLED 器件开启发光， 从而确保显示图像 不会由于像素电路在数据的写入的不稳定状态发生闪烁。
为了达到上述目的， 本发明的实施例提供了一种发光控制电路， 用于产 生在 AMOLED中控制 OLED发光的发光控制信号， 所述发光控制信号与栅 极驱动信号反相；
所述发光控制电路包括输入端、 输入釆样单元、 输出单元、 复位单元、 输出拉低单元和发光控制信号输出端， 其中，
所述输出拉低单元与所述发光控制信号输出端连接；
所述输入釆样单元， 分别与所述输入端、 第一时钟信号输入端和所述输 出拉低单元连接， 用于在第一时钟信号的控制下对输入信号进行釆样， 并将 釆样得到的信号通过所述输出拉低单元传送至所述发光控制信号输出端； 所述输出单元， 分别与所述输入釆样单元、 第二时钟信号输入端和所述 发光控制信号输出端连接，用于在所述输入釆样单元对输入信号进行釆样后， 在第二时钟信号的控制下产生发光控制信号， 并将该发光控制信号传送至所 述发光控制信号输出端；
所述复位单元， 分别与第三时钟信号输入端和所述输出拉低单元连接， 用于在第三时钟信号的控制下向所述输出拉低单元发出复位控制信号；
所述输出拉低单元， 用于根据该复位控制信号对所述发光控制信号进行 复位。
根据本发明的实施例， 所述输入釆样单元包括第一薄膜晶体管和第二薄 膜晶体管；
第一薄膜晶体管， 栅极与第一时钟信号输入端连接， 源极与所述输出单 元连接， 漏极与所述输入端连接；
第二薄膜晶体管， 栅极与第一时钟信号输入端连接， 源极与输出单元连 接， 漏极与驱动电源的低电平输出端连接。
根据本发明的实施例， 所述输出单元包括第三薄膜晶体管、 第四薄膜晶 体管、 第五薄膜晶体管、 第六薄膜晶体管、 第七薄膜晶体管、 第一电容和第 二电容；
第三薄膜晶体管， 栅极与第一薄膜晶体管的源极连接， 源极与第四薄膜 晶体管的栅极连接， 漏极与第二时钟信号输入端连接；
第四薄膜晶体管， 栅极与第三薄膜晶体管的源极连接， 源极与第六薄膜 晶体管的栅极连接， 漏极与驱动电源的低电平输出端连接；
第五薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第二薄膜晶体管的源极连接；
第六薄膜晶体管， 源极与驱动电源的高电平输出端连接， 漏极与第十二 薄膜晶体管的源极连接；
第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第十三薄膜晶体管的源极连接；
第一电容， 连接于第三薄膜晶体管的栅极与源极之间；
第二电容， 连接于第六薄膜晶体管的栅极和驱动电源的低电平输出端之 间。
根据本发明的实施例， 所述复位单元包括第八薄膜晶体管和第九薄膜晶 体管；
第八薄膜晶体管， 栅极与第三时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第一薄膜晶体管的源极连接；
第九薄膜晶体管， 栅极与第三时钟信号输入端连接， 源极与第二薄膜晶 体管的源极连接， 漏极与驱动电源的低电平输出端连接。
根据本发明的实施例， 所述输出拉低单元包括第十薄膜晶体管、 第十一 薄膜晶体管、 第十二薄膜晶体管、 第十三薄膜晶体管、 第三电容、 第四电容、 第五电容和第六电容；
第十薄膜晶体管， 栅极与第十一薄膜晶体管的栅极连接， 源极与驱动电 源的高电平输出端连接， 漏极与第三薄膜晶体管的源极连接；
第十一薄膜晶体管， 源极与驱动电源的高电平输出端连接， 漏极与第四 薄膜晶体管的源极连接；
第十二薄膜晶体管， 栅极与第二薄膜晶体管的源极连接， 源极与第六薄 膜晶体管的漏极连接， 漏极与驱动电源的低电平输出端连接；
第十三薄膜晶体管， 栅极与第十薄膜晶体管的栅极连接， 源极与发光控 制信号输出端连接， 漏极与驱动电源的低电平输出端连接；
第三电容， 连接于第十二薄膜晶体管的栅极和源极之间；
第四电容， 连接于第十三薄膜晶体管的栅极和源极之间；
第五电容， 连接于第十薄膜晶体管的栅极与驱动电源的低电平输出端之 间；
第六电容，连接于发光控制信号输出端与驱动电源的低电平输出端之间。 根据本发明的实施例的发光控制电路还包括反相输出端；
所述第四薄膜晶体管的栅极与所述反相输出端连接；
从所述反相输出端输出的信号与所述发光控制信号反相。
根据本发明的实施例， 第一薄膜晶体管、 第二薄膜晶体管、 第三薄膜晶 体管、 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜晶体管、 第七薄膜晶体 管、 第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜晶体管、 第十一薄膜晶体 管、 第十二薄膜晶体管和第十三薄膜晶体管是 p型 TFT。
本发明的实施例还提供了一种发光控制方法， 应用于上述的发光控制电 路， 用于产生在 AMOLED中控制 OLED发光的发光控制信号， 所述发光控 制信号与栅极驱动信号反相；
所述发光控制方法包括以下步骤：
输入釆样步骤： 输入釆样单元在第一时钟信号的控制下对输入信号进行 釆样， 并将釆样得到的信号通过输出拉低单元传送至发光控制信号输出端； 输出步骤： 在输入釆样单元对输入信号进行釆样后， 输出单元在第二时 钟信号的控制下产生发光控制信号， 并将该发光控制信号传送至发光控制信 号输出端；
复位步骤： 复位单元在第三时钟信号的控制下通过输出拉低单元对发光 控制信号进行复位。
本发明的实施例还提供了一种移位寄存器， 包括多级上述的发光控制电 路；
除了第一级发光控制电路和第二级发光控制电路之外， 第 n级发光控制 电路的输入信号为与第 （n-2 )级发光控制电路的发光控制信号反相的信号； 第一级发光控制电路的输入信号和第二级发光控制电路的输入信号为起 始信号；
n为大于 2而小于等于 N的整数， N为所述移位寄存器包括的发光控制 电路的级数。
与现有技术相比， 本发明的实施例的发光控制电路、 发光控制方法和移 位寄存器， 与产生栅极驱动信号反相的发光控制信号， 以使得在显示数据写 入像素单元的过程中， OLED 器件处于关闭状态， 而显示数据写入像素单元 后， OLED 器件开启发光， 从而确保显示图像不会由于像素电路在数据的写 入的不稳定状态发生闪烁。 附图说明
图 1是本发明第一实施例的发光控制电路的电路图；
图 2是本发明第二实施例的发光控制电路的电路图；
图 3是本发明一实施例的移位寄存器的电路图； 图 4是本发明第二实施例的发光控制电路中的工作时序图； 以及 图 5是如图 3所示的移位寄存器的工作时序图。 具体实施方式
为了使本发明实施例的目的、 技术方案和优点更加明白， 下面结合实施 例和附图， 对本发明的实施例做进一步详细的说明。 在此， 本发明的示意性 实施例以及说明用于解释本发明， 但不作为对本发明的限定。
对于有源矩阵液晶显示器（AMLCD ), 栅极驱动电路用于产生像素电路 阵列的行选通控制。然而对于 AMOLED (有源矩阵有机发光二极管）显示器， OLED为电流驱动器件 ,因此控制流入 OLED的电流通路，即可以控制 OLED 器件的发光。 所以为了在 AMOLED (有源矩阵有机发光二极管）显示器中对 OLED的发光进行准确的控制， 本发明的实施例提供了一种发光控制电路、 发光控制方法和移位寄存器。
本发明的实施例的发光控制电路与传统的栅极驱动电路配合工作， 用于 完成 OLED和像素电路工作状态的分别控制。
如图 1所示， 本发明第一实施例的发光控制电路， 用于产生在 AMOLED 中控制 OLED发光的发光控制信号，所述发光控制信号与栅极驱动信号反相； 所述发光控制电路包括输入端 Input、 输入釆样单元 11、 输出单元 12、 复位单元 13、 输出拉低单元 14和发光控制信号输出端 EM[n] , 其中，
所述输入釆样单元 11 , 分别与所述输入端 Input、 所述输出单元 12、 第 一时钟信号输入端和所述输出拉低单元 14连接，用于在第一时钟信号的控制 下对输入信号进行釆样，并将釆样得到的信号通过所述输出拉低单元 14传送 至所述发光控制信号输出端 EM[n];
所述输出单元 12, 分别与所述输入釆样单元 11、 第二时钟信号输入端和 所述发光控制信号输出端 EM[n]连接， 用于在所述输入釆样单元 11对输入信 号进行釆样后， 在第二时钟信号的控制下产生发光控制信号， 并将该发光控 制信号传送至所述发光控制信号输出端 EM[n];
所述复位单元 13 , 分别与第三时钟信号输入端和所述输出拉低单元 14 连接，用于在第三时钟信号的控制下向所述输出拉低单元发出复位控制信号； 所述输出拉低单元 14, 与所述发光控制信号输出端 EM[n]连接， 用于根 据该复位控制信号对所述发光控制信号进行复位； 从第一时钟信号输入端输入第一时钟信号 CK1 , 从第二时钟信号输入端 输入第二时钟信号 CK2, 从第三时钟信号输入端输入第三时钟信号 CK3。
本发明第一实施例的发光控制电路能产生在 AMOLED中控制 OLED发 光的发光控制信号， 所述发光控制信号与栅极驱动信号反相， 可以在
AMOLED (有源矩阵有机发光二极管 )显示器中对 OLED的发光进行准确的 控制， 以使得在显示数据写入像素单元的过程中， OLED器件处于关闭状态， 而显示数据写入像素单元后， OLED器件开启发光， 从而确保显示图像不会 由于像素电路在数据的写入的不稳定状态发生闪烁。
图 2是本发明第二实施例的发光控制电路的电路图。 如图 2所示， 本发 明第二实施例的发光控制电路基于本发明第一实施例的发光控制电路。 在本 发明第二实施例的发光控制电路中，
所述输入釆样单元包括第一薄膜晶体管 T1和第二薄膜晶体管 T2;
所述输出单元包括第三薄膜晶体管 T3、 第四薄膜晶体管 Τ4、 第五薄膜 晶体管 Τ5、 第六薄膜晶体管 Τ6、 第七薄膜晶体管 Τ7、 第一电容 C1和第二 电容 C2;
所述复位单元包括第八薄膜晶体管 Τ8和第九薄膜晶体管 Τ9;
所述输出拉低单元包括第十薄膜晶体管 Τ10、第十一薄膜晶体管 Tll、第 十二薄膜晶体管 Τ12、 第十三薄膜晶体管 Τ13、 第三电容 C3、 第四电容 C4、 第五电容 C5和第六电容 C6;
第一薄膜晶体管 T1 , 栅极与第一时钟信号输入端连接， 源极与所述第三 薄膜晶体管 T3的栅极连接， 漏极与所述输入端 Input连接；
第二薄膜晶体管 T2, 栅极与第一时钟信号输入端连接， 源极与第五薄膜 晶体管 T5的漏极连接， 漏极与驱动电源的低电平输出端连接；
第三薄膜晶体管 T3 , 源极与第四薄膜晶体管 T4的栅极连接， 漏极与第 二时钟信号输入端连接；
第四薄膜晶体管 T4, 源极与第六薄膜晶体管 T6的栅极连接， 漏极与驱 动电源的低电平输出端连接；
第五薄膜晶体管 T5, 栅极与第二时钟信号输入端连接， 源极与驱动电源 的高电平输出端连接；
第六薄膜晶体管， 源极与驱动电源的高电平输出端连接， 漏极与第十二 薄膜晶体管 T12的源极连接； 第七薄膜晶体管 T7, 栅极与第二时钟信号输入端连接， 源极与驱动电源 的高电平输出端连接， 漏极与第十三薄膜晶体管 T13的源极连接；
第八薄膜晶体管 T8, 栅极与第三时钟信号输入端连接， 源极与驱动电源 的高电平输出端连接， 漏极与第一薄膜晶体管 T1的源极连接；
第九薄膜晶体管 T9, 栅极与第三时钟信号输入端连接， 源极与第二薄膜 晶体管 T2的源极连接， 漏极与驱动电源的低电平输出端连接；
第十薄膜晶体管 T10, 栅极与第十一薄膜晶体管 T11的栅极连接， 源极 与驱动电源的高电平输出端连接， 漏极与第三薄膜晶体管 T3的源极连接； 第十一薄膜晶体管 T11 , 源极与驱动电源的高电平输出端连接， 漏极与 第四薄膜晶体管 T4的源极连接；
第十二薄膜晶体管 T12, 栅极与第二薄膜晶体管 T2的源极连接， 源极与 第六薄膜晶体管 T6的漏极连接， 漏极与驱动电源的低电平输出端连接； 第十三薄膜晶体管 T13 , 栅极与第十薄膜晶体管 T10的栅极连接， 源极 与发光控制信号输出端 EM[n]连接， 漏极与驱动电源的低电平输出端连接； 第一电容 C1 , 连接于第三薄膜晶体管 T3的栅极与源极之间；
第二电容 C2, 连接于第六薄膜晶体管 T6的栅极和驱动电源的低电平输 出端之间；
第三电容 C3 , 连接于第十二薄膜晶体管 T12的栅极和源极之间； 第四电容 C4, 连接于第十三薄膜晶体管 T13的栅极和源极之间； 第五电容 C5 ,连接于第十薄膜晶体管 T10的栅极与驱动电源的低电平输 出端之间；
第六电容 C6, 连接于发光控制信号输出端 EM[n]与驱动电源的低电平输 出端之间；
从第一时钟信号输入端输入第一时钟信号 CK1 , 从第二时钟信号输入端 输入第二时钟信号 CK2, 从第三时钟信号输入端输入第三时钟信号 CK3; 驱动电源的高电平输出端的输出电压为 VGH,驱动电源的低电平输出端 的输出电压为 VGL;
N1点是与所述第三薄膜晶体管 T3的栅极连接的节点；
N2点是与所述第四薄膜晶体管 T4的栅极连接的节点；
N3点是与所述第六薄膜晶体管 T6的栅极连接的节点；
N4点是与所述第十二薄膜晶体管 T12的栅极连接的节点； N5点是与所述第十三薄膜晶体管 T13的栅极连接的节点；
N2点 （即反相输出端 EM— Out )与下一级移位寄存器单元电路连接， 为 下一级移位寄存器单元电路提供输入信号；
从所述反相输出端 EM— Out输出的信号与所述发光控制信号反相； 其中， Cl、 C3和 C4为自举电容， C2、 C4和 C6为存储电容； 自举电容 主要用于抬高或者拉低节点的电平， 而存储电容主要用于保持节点的电平。
第一薄膜晶体管 Tl、 第二薄膜晶体管 Τ2、 第三薄膜晶体管 Τ3、 第四薄 膜晶体管 Τ4、第五薄膜晶体管 Τ5、第六薄膜晶体管 Τ6、第七薄膜晶体管 Τ7、 第八薄膜晶体管 Τ8、 第九薄膜晶体管 Τ9、 第十薄膜晶体管 Τ10、 第十一薄膜 晶体管 Tll、 第十二薄膜晶体管 T12和第十三薄膜晶体管 T13是 ρ型 TFT。
如图 3所示， 本发明一实施例的移位寄存器包括多级本发明第二实施例 的发光控制电路；
除了第一级发光控制电路和第二级发光控制电路之外， 第 n级发光控制 电路的输入端 Input为与第 （ n-2 )级发光控制电路的反相输出端 EM_Out连 接；
第一级发光控制电路的输入端 Input和第二级发光控制电路的输入端 Input与起始信号输入端连接；
从所述起始信号输入端输入起始信号 STV;
n为大于 2而小于等于 N的整数， N为所述移位寄存器包括的发光控制 电路的级数；
在图 3中， STAGE— 1、 STAGE— 2、 STAGE— 3、 STAGE— 4、 STAGE— 5、 STAGE— 6、 STAGE— 7、 STAGE— 8指示的分别是第一级发光控制电路、 第二级 发光控制电路、 第一级发光控制电路、 第二级发光控制电路、 第三级发光控 制电路、 第四级发光控制电路、 第五级发光控制电路、 第六级发光控制电路、 第七级发光控制电路、 第八级发光控制电路；
并且， 与奇数级发光控制电路连接的第一时钟信号、 第二时钟信号、 第 三时钟信号分别为： CLK1-1、 CLKl-2、 CLK1-3;
与偶数级发光控制电路连接的第一时钟信号、 第二时钟信号、 第三时钟 信号分别为： CLK2-1、 CLK2-2、 CLK2-3。
图 4是本发明第二实施例的发光控制电路中的工作时序图， 该发光控制 电路为移位寄存器中的第一级发光控制电路； STV的脉宽是 CK1的脉宽、 CK2的脉宽和 CK3的脉宽的两倍；
CK1的第一个下降沿和 STV的下降沿对齐；
CK2的第一个下降沿与 CK1的第一个上升沿对齐；
CK3的第一个下降沿与 STV的上升沿对齐；
CK1的占空比、 CK2的占空比和 CK3的占空比为 1/3。
如图 4所示， tl阶段为输入釆样阶段， 此时输入信号 STV亦为低电平， 同时 CK1为低电平， T1导通， 同时 CK3为高电平， T8关闭， 则此时 N1点 的电平被拉低为 VGL+ I Vthp I ； 同时由于 CK1为低电平， T2导通， N4点 为低电平， T12导通， 点 N5为低电平， 一方面开启 T10和 T11 , 相应的， 点 N2和 N3的电平为高电平， 晶体管 T4和 T6关闭， 确保了点 N3和 N5的电 平， 另一方面使 T13导通， 发光控制信号输出端 EM[n]输出的发光控制信号 为低电平； 其中， Vthp是 p型薄膜晶体管的阔值电压；
t2阶段为输出阶段， CK1 , CK3为高电平， 晶体管 Tl , T3 , T2, T9均 关闭， 由于电容 C1的自举作用， N1点电平将被相应拉低， T3导通， CK2 信号为低电平， 此时 N2点电平为低， 则 T4导通， 将 N3点电平拉低， 相应 的， T6导通， 点 N5为高电平， T13关闭； 由于 CK2为低电平， T7导通， 则 发光控制信号输出端 EM[n]输出的发光控制信号为高电平信号， 为 OLED器 件提供开启信号；
t3阶段为复位阶段， CK3为低， 相应的， T8、 Τ9导通， 将点 N1电平拉 高， 点 Ν4电平拉低。 此时 T12导通， 点 Ν5电平为低电平。 此时 T10、 Til 导通。 将点 N2和 N3拉高， T4和 T6关闭， 确保点 N3和 N5的电平； 由于 点 N5为低电平， T13导通， 则此时发光控制信号输出端 EM[n]输出的发光 控制信号重新被拉低， 完成发光控制信号的复位。
图 5是如图 3所示的移位寄存器的工作时序图， 在图 5中， EM— out— 1、 EM— out— 2、 EM— out— n指示的分别是第一级发光控制电路的反相输出端、 第 二级发光控制电路的反相输出端、 第 n级发光控制电路的反相输出端；
EM— 1、 EM— 2、 EM—n指示的分别是第一级发光控制电路输出的发光控 制信号、 第二级发光控制电路输出的发光控制信号、 第 n级发光控制电路输 出的发光控制信号；
n是小于等于移位寄存器包括的发光控制电路的级数的整数；
CLK1-1的脉宽、 CLK1-2的脉宽、 CLK1-3的脉宽、 CLK2-1的脉宽、 CLK2-2 的脉宽和 CLK2-3的脉宽相同；
所述起始信号 STV的脉宽分别是 CLK1-1的脉宽、 CLK1-2的脉宽、 CLK1-3的脉宽、 CLK2-1的脉宽、 CLK2-2的脉宽和 CLK2-3的脉宽的两倍； CLK1-1的第一个下降沿和 STV的下降沿对齐；
CLK1-2的第一个下降沿与 CLK1-1的第一个上升沿对齐；
CLK1-3的第一个下降沿与 STV的上升沿对齐；
CLK2-1的第一个下降沿位于 STV脉宽的 1/4处，即位于 CLK1-1 自身脉 宽的 1/2处；
CLK2-2的第一个下降沿与 CLK2-1的第一个上升沿对齐；
CLK2-3的第一个下降沿与 CLK2-2的第一个上升沿对齐；
CLK1-1的占空比、 CLK1-2的占空比、 CLK1-3的占空比、 CLK2-1的占 空比、 CLK2-2的占空比和 CLK2-3的占空比为 1/3。
本发明的实施例还提供了一种发光控制方法， 用于产生在 AMOLED中 控制 OLED发光的发光控制信号， 所述发光控制信号与栅极驱动信号反相； 所述发光控制方法包括以下步骤：
输入釆样步骤： 输入釆样单元在第一时钟信号的控制下对输入信号进行 釆样， 并将釆样得到的信号通过输出拉低单元传送至发光控制信号输出端； 输出步骤： 在输入釆样单元对输入信号进行釆样后， 输出单元在第二时 钟信号的控制下产生发光控制信号， 并将该发光控制信号传送至发光控制信 号输出端； 所述发光控制信号为提供给 OLED器件的驱动 TFT的开启信号； 复位步骤： 复位单元在第三时钟信号的控制下通过输出拉低单元对发光 控制信号进行复位。
以上说明对本发明而言只是说明性的， 而非限制性的， 本领域普通技术 人员理解， 在不脱离所附权利要求所限定的精神和范围的情况下， 可做出许 多修改、 变化或等效， 但都将落入本发明的保护范围内。

Claims

权 利 要 求 书
1、一种发光控制电路， 用于产生在 AMOLED中控制 OLED发光的发光 控制信号， 所述发光控制信号与栅极驱动信号反相；
所述发光控制电路包括输入端、 输入釆样单元、 输出单元、 复位单元、 输出拉低单元和发光控制信号输出端， 其中，
所述输出拉低单元与所述发光控制信号输出端连接；
所述输入釆样单元， 分别与所述输入端、 第一时钟信号输入端和所述输 出拉低单元连接， 用于在第一时钟信号的控制下对输入信号进行釆样， 并将 釆样得到的信号通过所述输出拉低单元传送至所述发光控制信号输出端； 所述输出单元， 分别与所述输入釆样单元、 第二时钟信号输入端和所述 发光控制信号输出端连接，用于在所述输入釆样单元对输入信号进行釆样后， 在第二时钟信号的控制下产生发光控制信号， 并将该发光控制信号传送至所 述发光控制信号输出端；
所述复位单元， 分别与第三时钟信号输入端和所述输出拉低单元连接， 用于在第三时钟信号的控制下向所述输出拉低单元发出复位控制信号；
所述输出拉低单元， 用于根据该复位控制信号对所述发光控制信号进行 复位。
2、 如权利要求 1所述的发光控制电路， 其中，
所述输入釆样单元包括第一薄膜晶体管和第二薄膜晶体管；
第一薄膜晶体管， 栅极与第一时钟信号输入端连接， 源极与所述输出单 元连接， 漏极与所述输入端连接；
第二薄膜晶体管， 栅极与第一时钟信号输入端连接， 源极与输出单元连 接， 漏极与驱动电源的低电平输出端连接。
3、 如权利要求 2所述的发光控制电路， 其中，
所述输出单元包括第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、 第六薄膜晶体管、 第七薄膜晶体管、 第一电容和第二电容；
第三薄膜晶体管， 栅极与第一薄膜晶体管的源极连接， 源极与第四薄膜 晶体管的栅极连接， 漏极与第二时钟信号输入端连接；
第四薄膜晶体管， 栅极与第三薄膜晶体管的源极连接， 源极与第六薄膜 晶体管的栅极连接， 漏极与驱动电源的低电平输出端连接； 第五薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第二薄膜晶体管的源极连接；
第六薄膜晶体管， 源极与驱动电源的高电平输出端连接， 漏极与第十二 薄膜晶体管的源极连接；
第七薄膜晶体管， 栅极与第二时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第十三薄膜晶体管的源极连接；
第一电容， 连接于第三薄膜晶体管的栅极与源极之间；
第二电容， 连接于第六薄膜晶体管的栅极和驱动电源的低电平输出端之 间。
4、 如权利要求 3所述的发光控制电路， 其中，
所述复位单元包括第八薄膜晶体管和第九薄膜晶体管；
第八薄膜晶体管， 栅极与第三时钟信号输入端连接， 源极与驱动电源的 高电平输出端连接， 漏极与第一薄膜晶体管的源极连接；
第九薄膜晶体管， 栅极与第三时钟信号输入端连接， 源极与第二薄膜晶 体管的源极连接， 漏极与驱动电源的低电平输出端连接。
5、 如权利要求 4所述的发光控制电路， 其中，
所述输出拉低单元包括第十薄膜晶体管、 第十一薄膜晶体管、 第十二薄 膜晶体管、 第十三薄膜晶体管、 第三电容、 第四电容、 第五电容和第六电容； 第十薄膜晶体管， 栅极与第十一薄膜晶体管的栅极连接， 源极与驱动电 源的高电平输出端连接， 漏极与第三薄膜晶体管的源极连接；
第十一薄膜晶体管， 源极与驱动电源的高电平输出端连接， 漏极与第四 薄膜晶体管的源极连接；
第十二薄膜晶体管， 栅极与第二薄膜晶体管的源极连接， 源极与第六薄 膜晶体管的漏极连接， 漏极与驱动电源的低电平输出端连接；
第十三薄膜晶体管， 栅极与第十薄膜晶体管的栅极连接， 源极与发光控 制信号输出端连接， 漏极与驱动电源的低电平输出端连接；
第三电容， 连接于第十二薄膜晶体管的栅极和源极之间；
第四电容， 连接于第十三薄膜晶体管的栅极和源极之间；
第五电容， 连接于第十薄膜晶体管的栅极与驱动电源的低电平输出端之 间；
第六电容，连接于发光控制信号输出端与驱动电源的低电平输出端之间。
6、 如权利要求 5所述的发光控制电路， 还包括反相输出端； 所述第四薄膜晶体管的栅极与所述反相输出端连接；
从所述反相输出端输出的信号与所述发光控制信号反相。
7、 如权利要求 5或 6所述的发光控制电路， 第一薄膜晶体管、 第二薄膜 晶体管、 第三薄膜晶体管、 第四薄膜晶体管、 第五薄膜晶体管、 第六薄膜晶 体管、 第七薄膜晶体管、 第八薄膜晶体管、 第九薄膜晶体管、 第十薄膜晶体 管、 第十一薄膜晶体管、 第十二薄膜晶体管和第十三薄膜晶体管是 p型 TFT。
8、一种发光控制方法，应用于如权利要求 1至 7中任一权利要求所述的 发光控制电路， 用于产生在 AMOLED中控制 OLED发光的发光控制信号， 其特征在于， 所述发光控制信号与栅极驱动信号反相；
所述发光控制方法包括以下步骤：
输入釆样步骤： 输入釆样单元在第一时钟信号的控制下对输入信号进行 釆样， 并将釆样得到的信号通过输出拉低单元传送至发光控制信号输出端； 输出步骤： 在输入釆样单元对输入信号进行釆样后， 输出单元在第二时 钟信号的控制下产生发光控制信号， 并将该发光控制信号传送至发光控制信 号输出端；
复位步骤： 复位单元在第三时钟信号的控制下通过输出拉低单元对发光 控制信号进行复位。
9、一种移位寄存器， 包括多级如权利要求 1至 7中任一权利要求所述的 发光控制电路；
除了第一级发光控制电路和第二级发光控制电路之外， 第 n级发光控制 电路的输入信号为与第 （n-2 )级发光控制电路的发光控制信号反相的信号； 第一级发光控制电路的输入信号和第二级发光控制电路的输入信号为起 始信号；
n为大于 2而小于等于 N的整数， N为所述移位寄存器包括的发光控制 电路的级数。
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